[PATCH] D151433: [Clang][SVE2.1] Add builtins for Multi-vector load and store

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thanks @CarolineConcatto, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151433/new/ https://reviews.llvm.org/D151433

[PATCH] D151433: [Clang][SVE2.1] Add builtins for Multi-vector load and store

kmclaughlin added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:1920 + +def SVST1B_X2 : MInst<"svst1[_{2}_x2]", "v}p2", "cUc", [IsStructStore,], MemEltTyDefault, "aarch64_sve_st1_pn_x2">; +def SVST1H_X2 : MInst<"svst1[_{2}_x2]", "v}p2", "sUshb",

[PATCH] D151307: [Clang][SVE2.1] Add svwhile (predicate-as-counter) builtins

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151307/new/ https://reviews.llvm.org/D151307

[PATCH] D151197: [Clang][SVE2p1] Add svpsel builtins

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thank you for updating this @CarolineConcatto, LGTM Comment at: clang/include/clang/Basic/arm_sve.td:1886 + + nit: extra whitespace

[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thank you @bryanpkc, this LGTM Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c:2 +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1

[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

kmclaughlin added a comment. Hi @bryanpkc, thank you for updating this patch & applying the previous review comments here too. I just have a couple of minor suggestions: Comment at: clang/include/clang/Basic/arm_sme.td:103 +def NAME # _H : SInst<"svwrite_hor_" # n_suffix

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thank you for checking and removing EltTypeBool128. I think you have addressed all of the other comments on this patch too, so it looks good to me! Please can you update the commit

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

kmclaughlin added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:8874 case SVETypeFlags::EltTyBool64: + case SVETypeFlags::EltTyBool128: return Builder.getInt1Ty(); Is it necessary to add an `EltTypeBool128`? I think the

[PATCH] D70253: [AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics

kmclaughlin added inline comments. Comment at: llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll:31 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.flogb.nxv2f64( %a, + %pg,

[PATCH] D108138: [WIP] Remove switch statements before vectorization

kmclaughlin abandoned this revision. kmclaughlin added a comment. I just wanted to give an update on this patch, which I'm abandoning for the time being: @lebedev.ri raised some good questions about the approach taken and whether the additional compile time spent would be worth the additional

[PATCH] D108138: [WIP] Remove switch statements before vectorization

kmclaughlin added a comment. Hi all, I've updated this to take a different approach - the new patch runs LowerSwitch just before the vectoriser, where it will only consider simple switches which are part of a loop. For these switches, the pass will create a series of branches and compares

[PATCH] D108138: [WIP] Remove switch statements before vectorization

kmclaughlin updated this revision to Diff 372706. kmclaughlin retitled this revision from "[SimplifyCFG] Remove switch statements before vectorization" to "[WIP] Remove switch statements before vectorization". kmclaughlin edited the summary of this revision. kmclaughlin added a comment. Herald

[PATCH] D108138: [SimplifyCFG] Remove switch statements before vectorization

kmclaughlin added a comment. Thanks all for the suggestions on this patch :) I had a look at the LowerSwitch pass as suggested by @junparser, and I did find that running it before vectorisation transforms the switch and allows the same loops to be vectorised. However, I did find that if the

[PATCH] D108138: [SimplifyCFG] Remove switch statements before vectorization

kmclaughlin created this revision. kmclaughlin added reviewers: david-arm, fhahn, dmgreen, craig.topper, lebedev.ri. Herald added subscribers: ctetreau, ormris, wenlei, steven_wu, hiraditya, kristof.beyls. kmclaughlin requested review of this revision. Herald added projects: clang, LLVM. Herald

[PATCH] D100294: [AArch64][SVE] Fix dup/dupq intrinsics for C++.

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100294/new/ https://reviews.llvm.org/D100294

[PATCH] D82943: [SVE] Add more warnings checks to clang and LLVM SVE tests

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82943/new/ https://reviews.llvm.org/D82943

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rGedcfef8fee13: [AArch64][SVE] Add bfloat16 support to store intrinsics (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82448/new/

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin updated this revision to Diff 273331. kmclaughlin added a comment. - Added HasSVE to Predicates in AArch64SVEInstrInfo.td - Removed unnecessary indentation changes in AArch64SVEInstrInfo.td - Removed hasBF16 variable from performST1Combine/performSTNT1Combine CHANGES SINCE LAST

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin marked 4 inline comments as done. kmclaughlin added a comment. Thanks for reviewing this again, @fpetrogalli! Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c:4 +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin updated this revision to Diff 273092. kmclaughlin added a comment. - Added [HasBF16] predicate to new store pattern in AArch64SVEInstrInfo.td - Check hasBF16() is true for bfloat16 types in performST1Combine/performSTNT1Combine - Added bfloat16 test to

[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, fpetrogalli, efriedma, stuij, david-arm. Herald added subscribers: llvm-commits, cfe-commits, danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added projects: clang, LLVM. Bfloat16

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rG3d6cab271c7c: [AArch64][SVE] Add bfloat16 support to load intrinsics (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82298/new/

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

kmclaughlin updated this revision to Diff 272759. kmclaughlin added a comment. - Moved bfloat tests into separate files - Added checks to the bfloat test files which test the warnings given when ARM_FEATURE_SVE_BF16 is omitted in the RUN line CHANGES SINCE LAST ACTION

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rG508050317403: [SVE][CodeGen] Legalisation of vsetcc with scalable types (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79167/new/

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

kmclaughlin updated this revision to Diff 272483. kmclaughlin added a comment. Added tests to llvm-ir-to-intrinsic.ll which check the results of compare instructions CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79167/new/ https://reviews.llvm.org/D79167 Files:

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

kmclaughlin added a comment. In D79167#2098774 , @efriedma wrote: > Is it possible to write tests for this that don't result in a "max" or "min" > operation? Or does that fail for some other reason? > > Otherwise LGTM. Thanks for reviewing this,

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, efriedma, stuij, fpetrogalli, david-arm. Herald added subscribers: llvm-commits, cfe-commits, danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added projects: clang, LLVM. Bfloat16

[PATCH] D79167: [SVE][CodeGen] Legalisation of vsetcc with scalable types

kmclaughlin updated this revision to Diff 271391. kmclaughlin retitled this revision from "[SVE][CodeGen] Legalise scalable vector types for vsetcc & vselect" to "[SVE][CodeGen] Legalisation of vsetcc with scalable types". kmclaughlin edited the summary of this revision. kmclaughlin added a

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rG89fc0166f532: [CodeGen][SVE] Legalisation of extends with scalable types (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 268246. kmclaughlin added a comment. - Use APInt::trunc to truncate the constant in performSVEAndCombine CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/ https://reviews.llvm.org/D79587 Files: llvm/include/llvm/CodeGen/ValueTypes.h

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267919. kmclaughlin marked 2 inline comments as done. kmclaughlin added a comment. - Added a truncate of ExtVal in performSVEAndCombine - Changed the assert added to performSignExtendInRegCombine in the previous revision CHANGES SINCE LAST ACTION

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin marked an inline comment as not done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10676 +ConstantSDNode *C = dyn_cast(Dup->getOperand(0)); +uint64_t ExtVal = C->getZExtValue(); + efriedma

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin marked 2 inline comments as done. kmclaughlin added a comment. Thanks for taking another look at this, @efriedma! Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10676 +ConstantSDNode *C = dyn_cast(Dup->getOperand(0)); +uint64_t ExtVal =

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267695. kmclaughlin marked 7 inline comments as done. kmclaughlin added a comment. - Restricted the illegal types which should be lowered for EXTRACT_SUBVECTOR to those handled in this patch (nxv8i8, nxv4i16 & nxv2i32) - Removed unnecessary changes in

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267280. kmclaughlin added a comment. - Replaced uses of getVectorNumElements() with getVectorElementCount() - Moved the new tests into the existing sve-sext-zext.ll file CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin updated this revision to Diff 267183. kmclaughlin edited the summary of this revision. kmclaughlin added a comment. - Removed ReplaceExtensionResults and instead try to use extract_subvector as much as possible to legalise the result - Added ReplaceExtractSubVectorResults, which

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, david-arm. Herald added subscribers: psnobl, rkruppe, hiraditya, tschuett. Herald added a project: LLVM. This patch adds legalisation of extensions where the operand of the extend is a legal scalable type but the

[PATCH] D79478: [CodeGen][SVE] Lowering of shift operations with scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rG3bcd3dd4734d: [CodeGen][SVE] Lowering of shift operations with scalable types (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D79478?vs=262333=262600#toc Repository: rG

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

This revision was automatically updated to reflect the committed changes. Closed by commit rGa31f4c52bf85: [SVE][CodeGen] Fix legalisation for scalable types (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78812?vs=260603=262580#toc Repository: rG LLVM Github

[PATCH] D79478: [CodeGen][SVE] Lowering of shift operations with scalable types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, ctetreau, huihuiz. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. kmclaughlin added a parent revision: D78812:

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

This revision was automatically updated to reflect the committed changes. Closed by commit rG19f5da9c1d69: [SVE][Codegen] Lower legal min max operations (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D79087?vs=261462=261787#toc Repository: rG LLVM Github

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin marked an inline comment as done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:3851 + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _S)>; + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _D)>; } efriedma wrote: >

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin updated this revision to Diff 261462. kmclaughlin added a comment. - Added tests for the intrinsics where the second operand is an immediate - Changed the range SelectSVESignedArithImm checks for, as the range for the immediates of smin & smax is -128 to +127 (inclusive) CHANGES

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin marked an inline comment as done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:3851 + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _S)>; + def : SVE_1_Op_Imm_Arith_Pred_Pat(NAME # _D)>; } efriedma wrote: >

[PATCH] D79167: [SVE][CodeGen] Legalise scalable vector types for vsetcc & vselect

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, dancgr. Herald added subscribers: psnobl, rkruppe, hiraditya, tschuett. Herald added a project: LLVM. kmclaughlin added a parent revision: D79087: [SVE][Codegen] Lower legal min & max operations. The visitSelect

[PATCH] D79087: [SVE][Codegen] Lower legal min & max operations

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, dancgr. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. This patch adds AArch64ISD nodes for [S|U]MIN_PRED and

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin marked an inline comment as done. kmclaughlin added inline comments. Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:1429 + !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) { +EltCnt.Min >>= 1; NumVectorRegs <<= 1; I will

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin marked 2 inline comments as done. kmclaughlin added inline comments. Comment at: llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll:107 + ret %div +} efriedma wrote: > Maybe also worth adding a testcase for ``, assuming that > doesn't expose

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin updated this revision to Diff 260603. kmclaughlin added a comment. - Use ElementCount with getVectorVT CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78812/new/ https://reviews.llvm.org/D78812 Files: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, huntergr. Herald added subscribers: psnobl, rkruppe, hiraditya, tschuett. Herald added a project: LLVM. This patch handles illegal scalable types when lowering IR operations, addressing several places where the

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

kmclaughlin added a comment. Thank you both for your comments on this patch, @efriedma & @sdesmalen! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78569/new/ https://reviews.llvm.org/D78569 ___

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

This revision was automatically updated to reflect the committed changes. kmclaughlin marked an inline comment as done. Closed by commit rG53dd72a87aeb: [SVE][CodeGen] Lower SDIV UDIV to SVE intrinsics (authored by kmclaughlin). Changed prior to commit:

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

kmclaughlin updated this revision to Diff 259610. kmclaughlin added a comment. - Removed changes to handle legalisation from this patch (this will be included in a follow up) - Added AArch64ISD nodes for SDIV_PRED & UDIV_PRED - Changed LowerDIV to use the new ISD nodes rather than lowering to

[PATCH] D77871: [AArch64] Armv8.6-a Matrix Mult Assembly + Intrinsics

kmclaughlin accepted this revision. kmclaughlin added a comment. This revision is now accepted and ready to land. Thanks for the updates, @LukeGeeson, LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77871/new/ https://reviews.llvm.org/D77871

[PATCH] D77871: [AArch64] Armv8.6-a Matrix Mult Assembly + Intrinsics

kmclaughlin added inline comments. Comment at: clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c:3 +// RUN: -fallow-half-arguments-and-returns -S -disable-O0-optnone -emit-llvm -o - %s \ +// RUN: | opt -S -mem2reg \ +// RUN: | FileCheck %s Is it possible to

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

This revision was automatically updated to reflect the committed changes. Closed by commit rG17f6e18acf5b: [AArch64][SVE] Add SVE intrinsic for LD1RQ (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76929/new/

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin updated this revision to Diff 259035. kmclaughlin marked an inline comment as done. kmclaughlin added a comment. - Use Load.getValue(0) when creating a bitcast in performLD1RQCombine CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76929/new/ https://reviews.llvm.org/D76929

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622 + if (VT.isFloatingPoint()) +Load = DAG.getNode(ISD::BITCAST, DL, VT, Load); + sdesmalen wrote: > kmclaughlin wrote: > > sdesmalen wrote: > > > I'd expect

[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, efriedma, cameron.mcinally. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. This patch maps IR operations for sdiv &

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

This revision was automatically updated to reflect the committed changes. Closed by commit rG0df40d6ef8b8: [AArch64][SVE] Add addressing mode for contiguous loads stores (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78509?vs=258954=258965#toc Repository: rG

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

kmclaughlin added a comment. Thanks for taking a look at this, @fpetrogalli! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78509/new/ https://reviews.llvm.org/D78509 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

kmclaughlin updated this revision to Diff 258954. kmclaughlin marked 5 inline comments as done. kmclaughlin added a comment. - Renamed ld1nf multiclass to ldnf1 - Split out existing reg+imm tests into their own files - Renamed 'offset' to 'index' in reg+reg tests CHANGES SINCE LAST ACTION

[PATCH] D78509: [AArch64][SVE] Add addressing mode for contiguous loads & stores

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, fpetrogalli, efriedma. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. This patch adds the register + register

[PATCH] D78204: [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store

This revision was automatically updated to reflect the committed changes. Closed by commit rG33ffce5414ec: [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D78204?vs=257702=258694#toc Repository:

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622 + if (VT.isFloatingPoint()) +Load = DAG.getNode(ISD::BITCAST, DL, VT, Load); + sdesmalen wrote: > I'd expect this to then use `Load.getValue(0)` ? I think

[PATCH] D78204: [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, efriedma, cameron.mcinally, c-rhodes. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. The SVE masked load and

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin updated this revision to Diff 257657. kmclaughlin marked an inline comment as done. kmclaughlin added a comment. Ensure LoadChain is always preserved in performLD1RQCombine CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76929/new/ https://reviews.llvm.org/D76929 Files:

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin updated this revision to Diff 257349. kmclaughlin marked 4 inline comments as done. kmclaughlin edited the summary of this revision. kmclaughlin added a comment. Simplified performLD1RQCombine method & added negative tests where the immediate is out of range. CHANGES SINCE LAST

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin marked 2 inline comments as done. kmclaughlin added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11592 +static SDValue performLD1RQCombine(SDNode *N, SelectionDAG ) { + SDLoc DL(N); andwar wrote: > [Nit] I think

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

This revision was automatically updated to reflect the committed changes. Closed by commit rG36c76de6789c: [AArch64][SVE] Add a pass for SVE intrinsic optimisations (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76078/new/

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin added a comment. Ping :) CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76078/new/ https://reviews.llvm.org/D76078 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D77054: [AArch64][SVE] Add SVE intrinsics for saturating add & subtract

This revision was automatically updated to reflect the committed changes. Closed by commit rG944e322f8897: [AArch64][SVE] Add SVE intrinsics for saturating add subtract (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D77054: [AArch64][SVE] Add SVE intrinsics for saturating add & subtract

kmclaughlin updated this revision to Diff 254742. kmclaughlin added a comment. Moved patterns for the new intrinsics into the// sve_int_bin_cons_arit_0// and //sve_int_arith_imm0// multiclasses CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77054/new/ https://reviews.llvm.org/D77054

[PATCH] D77054: [AArch64][SVE] Add SVE intrinsics for saturating add & subtract

kmclaughlin updated this revision to Diff 254558. kmclaughlin added a comment. Added patterns to AArch64SVEInstrInfo.td to support llvm.[s|u]add & llvm.[s|u]sub again, which was removed by my previous patch CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77054/new/

[PATCH] D77054: [AArch64][SVE] Add SVE intrinsics for saturating add & subtract

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, c-rhodes, dancgr, efriedma, cameron.mcinally. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Adds the following

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

kmclaughlin created this revision. kmclaughlin added reviewers: andwar, sdesmalen, efriedma, cameron.mcinally, dancgr. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Adds the following

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin updated this revision to Diff 252575. kmclaughlin marked an inline comment as done. kmclaughlin added a comment. Use SmallSetVector for the list of functions gathered by runOnModule to preserve the order of iteration CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76078/new/

[PATCH] D76688: [AArch64][SVE] Add SVE intrinsics for masked loads & stores

This revision was automatically updated to reflect the committed changes. Closed by commit rG05606329e235: [AArch64][SVE] Add SVE intrinsics for masked loads stores (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76688/new/

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin updated this revision to Diff 252368. kmclaughlin marked 3 inline comments as done. kmclaughlin added a comment. Use SmallPtrSet instead of SmallVector for storing functions found by runOnModule Add more comments to clarify the purpose of the pass and some of the negative

[PATCH] D76688: [AArch64][SVE] Add SVE intrinsics for masked loads & stores

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, andwar, efriedma, cameron.mcinally, dancgr. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Implements the

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin added a comment. Thanks for reviewing this, @efriedma & @andwar! Comment at: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp:441 + // Expand any SVE vector library calls that we can't code generate directly. + bool ExpandToOptimize = (TM->getOptLevel() !=

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin updated this revision to Diff 251643. kmclaughlin marked 13 inline comments as done. kmclaughlin added a comment. - Changed this from a function pass to a module pass & now check if any of the relevant SVE intrinsics are declared first before iterating over functions - Added more

[PATCH] D75690: [SVE][Inline-Asm] Add constraints for SVE ACLE types

This revision was automatically updated to reflect the committed changes. Closed by commit rGaf64948e2a05: [SVE][Inline-Asm] Add constraints for SVE ACLE types (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D75690?vs=249092=250720#toc Repository: rG LLVM Github

[PATCH] D76078: [AArch64][SVE] Add a pass for SVE intrinsic optimisations

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, andwar, efriedma, cameron.mcinally, c-rhodes. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett, mgorny. Herald added a reviewer: rengolin. Herald added a project: LLVM. Creates

[PATCH] D75858: [AArch64][SVE] Add SVE intrinsics for address calculations

This revision was automatically updated to reflect the committed changes. Closed by commit rG0bba37a32024: [AArch64][SVE] Add SVE intrinsics for address calculations (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75858/new/

[PATCH] D75858: [AArch64][SVE] Add SVE intrinsics for address calculations

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, andwar, efriedma, dancgr, cameron.mcinally. Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Adds the

[PATCH] D75690: [SVE][Inline-Asm] Add constraints for SVE ACLE types

kmclaughlin updated this revision to Diff 249092. kmclaughlin added a comment. - Added -emit-llvm to the RUN line of aarch64-sve-inline-asm-datatypes.c test. Added some more tests here for the Upl & y constraints and removed aarch64-sve-inline-asm-vec-low.c. - Addressed formatting suggestions

[PATCH] D75690: [SVE][Inline-Asm] Add constraints for SVE ACLE types

kmclaughlin marked 2 inline comments as done. kmclaughlin added a comment. Thanks for reviewing this, @efriedma! Comment at: clang/lib/Basic/Targets/AArch64.h:95 +case 'U': // Three-character constraint; add "@3" hint for later parsing. + R = std::string("@3") +

[PATCH] D75690: [SVE][Inline-Asm] Add constraints for SVE ACLE types

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, huntergr, rovka, cameron.mcinally, efriedma. Herald added subscribers: cfe-commits, psnobl, rkruppe, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. kmclaughlin added a parent revision: D75297:

[PATCH] D75160: [AArch64][SVE] Add SVE2 intrinsic for xar

This revision was automatically updated to reflect the committed changes. Closed by commit rGf5502c7035a9: [AArch64][SVE] Add SVE2 intrinsic for xar (authored by kmclaughlin). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75160/new/

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

kmclaughlin added a comment. Thanks for reviewing this, @sdesmalen & @efriedma! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74912/new/ https://reviews.llvm.org/D74912 ___ cfe-commits mailing list

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

This revision was automatically updated to reflect the committed changes. Closed by commit rG9c859fc54d92: [AArch64][SVE] Add SVE2 intrinsics for bit permutation table lookup (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D74912?vs=246487=246661#toc Repository:

[PATCH] D75160: [AArch64][SVE] Add SVE2 intrinsic for xar

kmclaughlin created this revision. kmclaughlin added reviewers: andwar, c-rhodes, dancgr, efriedma. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Implements the @llvm.aarch64.sve.xar intrinsic

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

kmclaughlin updated this revision to Diff 246487. kmclaughlin added a comment. Addressed review comments: - Removed SelectTableSVE2 from AArch64ISelDAGToDAG.cpp and added tablegen patterns for the tbl2 intrinsic - Updated tests to use operands that are not consecutive to ensure that the result

[PATCH] D74734: [AArch64][SVE] Add the SVE dupq_lane intrinsic

This revision was automatically updated to reflect the committed changes. kmclaughlin marked an inline comment as done. Closed by commit rGf87f23c81cae: [AArch64][SVE] Add the SVE dupq_lane intrinsic (authored by kmclaughlin). Changed prior to commit:

[PATCH] D74734: [AArch64][SVE] Add the SVE dupq_lane intrinsic

kmclaughlin marked 4 inline comments as done. kmclaughlin added a comment. Thanks for taking a look at this, @sdesmalen! Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7496 + auto CIdx = dyn_cast(Idx128); + if (CIdx && (CIdx->getZExtValue() <= 3)) { +auto CI

[PATCH] D74833: [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions

This revision was automatically updated to reflect the committed changes. Closed by commit rGf2ff153401fa: [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D74833?vs=245393=246171#toc Repository:

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

kmclaughlin marked 4 inline comments as done. kmclaughlin added a comment. Thanks for reviewing this, @andwar! Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:2035 + +def int_aarch64_sve_bdep_x : AdvSIMD_2VectorArg_Intrinsic; +def int_aarch64_sve_bext_x :

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

kmclaughlin updated this revision to Diff 245835. kmclaughlin added a comment. - Removed NumVecs parameter from SelectTableSVE2 as the value is always the same (2) - Removed unnecessary -asm-verbose=0 from the RUN line of sve2-intrinsics-bit-permutation.ll CHANGES SINCE LAST ACTION

[PATCH] D74912: [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup

kmclaughlin created this revision. kmclaughlin added reviewers: sdesmalen, andwar, dancgr, cameron.mcinally, efriedma. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: LLVM. Implements the following

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