[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-11-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. @kadircet Proposed fix: D138429 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124730/new/ https://reviews.llvm.org/D124730 ___ cfe-commits

[PATCH] D138287: [clang][RISCV] Drop caching from RVVType as it introduces data races

2022-11-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Proposed fix: D138429 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138287/new/ https://reviews.llvm.org/D138287 ___ cfe-commits mailing

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

2022-11-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. kito-cheng added reviewers: ilya-biryukov, kadircet, sammccall, khchen. Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D138287: [clang][RISCV] Drop caching from RVVType as it introduces data races

2022-11-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Apparently I missed those comments during llvm dev meeting, I'll figure out a fix soon. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138287/new/ https://reviews.llvm.org/D138287

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-11-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked 2 inline comments as done. kito-cheng added a comment. @kadircet ooops, sorry for missing your comment, let me figure out how to fix that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124730/new/

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

2022-11-10 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:469 +if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) { + LLVM_DEBUG(dbgs() << "Trying Vemtama custom opcode table:\n"); + Result =

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

2022-11-04 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136930/new/ https://reviews.llvm.org/D136930

[PATCH] D136817: [RISCV] Add H extension

2022-11-04 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked an inline comment as done. kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

2022-10-31 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2190 CmdArgs.push_back("-tune-cpu"); -CmdArgs.push_back(A->getValue()); +if (strcmp(A->getValue(), "native") == 0) +

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

2022-10-31 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Maybe we could add test like aarch64? https://github.com/llvm/llvm-project/blob/main/clang/test/Driver/aarch64-mcpu.c#L20 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136930/new/ https://reviews.llvm.org/D136930

[PATCH] D136817: [RISCV] Add H extension

2022-10-28 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: llvm/docs/RISCVUsage.rst:54 ``F``Supported + ``H``Supported ``M``Supported reames wrote: > If I'm reading the code

[PATCH] D136817: [RISCV] Add H extension

2022-10-28 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 471701. kito-cheng added a comment. Changes: - Update doc, H is support assembly only. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files:

[PATCH] D136817: [RISCV] Add H extension

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/test/MC/RISCV/rvi-aliases-valid.s:270 -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 Note: Those testcase are moved to `rv32ih-aliases-valid.s`, not just removed. Repository: rG LLVM Github Monorepo

[PATCH] D136817: [RISCV] Add H extension

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 471386. kito-cheng added a comment. Update instructions which are belong H extension now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files:

[PATCH] D136817: [RISCV] Add H extension

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng planned changes to this revision. kito-cheng added a comment. Let me do that within this patch :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817

[PATCH] D136812: [RISCV] Drop single letter b extension support

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rGae116f43ff14: [RISCV] Drop single letter b extension support (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136812/new/

[PATCH] D134050: [clang][RISCV][NFC][WIP/RFC] Move riscv-abi.cpp and riscv32-*abi.c tests to use update_cc_test_checks.py

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Oh, it's still `[WIP/RFC]`, but anyway that's really good way to go. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134050/new/ https://reviews.llvm.org/D134050 ___ cfe-commits mailing list

[PATCH] D134050: [clang][RISCV][NFC][WIP/RFC] Move riscv-abi.cpp and riscv32-*abi.c tests to use update_cc_test_checks.py

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, manually update such testcase is really painful! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134050/new/ https://reviews.llvm.org/D134050

[PATCH] D136817: [RISCV] Add H extension

2022-10-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. kito-cheng added reviewers: asb, craig.topper, reames. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D136812: [RISCV] Drop single letter b extension support

2022-10-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal,

[PATCH] D136570: [RISCV] Add Svnapot extension

2022-10-23 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136570/new/ https://reviews.llvm.org/D136570

[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

2022-09-06 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and +1 for the error message improvement, but could be separated patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D132192/new/

[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

2022-09-06 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. > I'm not sure how the issues with datalayout in particular end up being an > issue in practice. > > clang shouldn't be writing out object files without a datalayout. > The code to infer alignment on load/store/etc. only exists for compatibility > with old

[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

2022-09-05 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a subscriber: khchen. kito-cheng added a comment. This is dump from my mailbox, few month ago I written a offlist mail to describe about RISC-V LTO status: --- LTO for RISC-V is really kind of a long long story. @khchen has been fighting for that for a long time, but he is no

[PATCH] D121779: [RISCV] Add zihintntl compressed instructions

2022-08-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Herald added subscribers: sunshaoce, StephenFan, shiva0217. Comment at: llvm/test/MC/RISCV/rv32zihintntlc-valid.s:42 +# CHECK-ASM: encoding: [0x16,0x90] +c.ntl.all Could you add an invalid check for `c.ntl` instruction to make

[PATCH] D121670: [RISCV] Add zihintntl instructions

2022-08-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121670/new/ https://reviews.llvm.org/D121670

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

2022-08-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, result has compared with GCC for `rv32gc/ilp32d` and `rv64gc/lp64d`. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131677/new/ https://reviews.llvm.org/D131677

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

2022-08-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:27 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s -// MTUNE-ROCKET-64: "-tune-cpu" "rocket-rv64" - -// RUN: %clang --target=riscv32 -### -c

[PATCH] D131345: [RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

2022-08-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. > It relies on a runtime check: during init runtime makes > PR_{SET,GET}_TAGGED_ADDR_CTRL calls and if they're not supported, it fails > with an error. So burden of checking if J extension is present is on Linux > kernel. Sounds

[PATCH] D131345: [RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

2022-08-10 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. I guess we should checking `J` extension is enabled somewhere when user trying to enable HWASAN? or checking that at HWASAN library at run-time? otherwise my understanding is user will get crash when enabling HWASAN if linux and/or HW don't support that?

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

2022-08-04 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Just realized the problem is trying to fixed the default value of `-mabi=`, currently `clang -target riscv32-elf -march=rv64gc -mabi=lp64d`/`riscv32-elf-clang -march=rv64gc -mabi=lp64d` is work, and match the behavior of GCC did, `riscv32-elf-gcc -march=rv64gc

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

2022-08-02 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:286 + // StrictFP support for vectors is incomplete. + if (ISAInfo->hasExtension("zve32x")) +HasStrictFP = false; craig.topper wrote: > reames wrote: > > craig.topper wrote: >

[PATCH] D126742: [RISCV][Clang] Support RVV policy functions.

2022-07-31 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126742/new/

[PATCH] D126750: [RISCV][Clang] Support policy function for all vector segment load.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: nlopes. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: nlopes. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: nlopes. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D126744: [RISCV][Clang] Support policy functions for vneg, vnot, vncvt, vwcvt, vwcvtu, vfabs and vfneg.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126744/new/

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits
This revision was not accepted when it landed; it landed in state "Needs Review". This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. kito-cheng marked an inline comment as done. Closed by commit rG7a5cb15ea6fa: [RISCV]

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked 9 inline comments as done. kito-cheng added a comment. @aaron.ballman thanks for your review! Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:400 + // Number of fields, greater than 1 if it's segment load/store. + uint8_t NF; +};

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-25 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. @aaron.ballman do you mind give few more look on this patch, we would like gather LGTM from both RISC-V folks and clang folks, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D130190: [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation

2022-07-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D130190/new/ https://reviews.llvm.org/D130190 ___ cfe-commits mailing list

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-13 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 444188. kito-cheng added a comment. Changes: - Correct filename for testcases. - Use forward declaration for llvm::raw_ostream Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-05 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 442431. kito-cheng added a comment. Changes: Restore the patch, I just accidentally updated wrong revision here... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-05 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 442429. kito-cheng added a comment. Changes: - Less invasive way to fix this issue. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Files:

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-04 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for clean this up :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129043/new/ https://reviews.llvm.org/D129043

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-04 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:100 +switch (Type->getElementBitwidth()) { +case 64: + QT = Context.DoubleTy; aaron.ballman wrote: > kito-cheng wrote: > > aaron.ballman wrote: > > > I almost

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-04 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 442025. kito-cheng marked 9 inline comments as done. kito-cheng added a comment. Changes: - Address @frasercrmck's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Parse/ParsePragma.cpp:3963 +<< PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'intrinsic'"; +return; + } aaron.ballman wrote: > It's fine to warn on this, but then you need to eat

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 441692. kito-cheng marked 18 inline comments as done. kito-cheng added a comment. Changes: - Address @aaron.ballman’s comment - Add 2 new testcase: - riscv-bad-intrnisic-pragma.c - riscv-intrnisic-pragma.c Repository: rG LLVM Github Monorepo

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 441684. kito-cheng added a comment. Changes: - Address @craig.topper's comment - Introduce RISCVIntrinsicManager.h and let it become member of Sema, that make sure the it won't outlive than Sema. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked an inline comment as done. kito-cheng added a comment. Oh, have one comment not address yet Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:114 bool operator>(const PrototypeDescriptor ) const { -return !(PD.PT <= PT && PD.VTM <= VTM && PD.TM <= TM); +if (PD.PT != PT) + return PD.PT > PT;

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-07-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 441610. kito-cheng marked 24 inline comments as done. kito-cheng added a comment. Changes: - Address @craig.topper's comment - Address @khchen's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-06-30 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 441320. kito-cheng added a comment. Changes: - Rebase - Address @khchen's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Files:

[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

2022-06-29 Thread Kito Cheng via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1b8cde9b6338: [RISCV][NFC] Move static global variables into static variable in function. (authored by kito-cheng). Repository: rG LLVM Github

[PATCH] D128625: [RISCV][Driver] Fix baremetal `GCCInstallation` paths

2022-06-29 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, `riscv*-unknown-unknown` match `riscv*-unknown-elf` sound make more sense than `riscv*-unknown-linux-gnu` :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

2022-06-29 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. My understanding is the reason why no global variable is because 1. the initialization order and 2. might increase the launch time of programs, moving that into function scope could resolve both issue: 1. initialized in deterministic order[1], 2. Initialized that

[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

2022-06-28 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD,

[PATCH] D128235: [RISCV] Add support for the Zawrs extension

2022-06-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:195 + if (ISAInfo->hasExtension("zawrs")) +Builder.defineMacro("__riscv_zawrs"); } You don't need this line, that would be defined automatically once you've add `zawrs` in

[PATCH] D127826: [Driver] Pass -X to ld for riscv*-{elf,freebsd,linux}

2022-06-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. ld's help message just confused me, that say `-X` is default, but actually default action is `Discard local temporary symbols in SEC_MERGE sections.` which is no option can enable

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-24 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:480 +// They are handled by riscv_vector.h +if (Name == "vsetvli" || Name == "vsetvlimax") + continue; khchen wrote: > I feel little tricky to checking the name

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-24 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 431646. kito-cheng marked 5 inline comments as done. kito-cheng added a comment. Changes: - Split out several NFC changes to individual NFC patchs. - Moving most code emission logic into RISCVVIntrinsicUtils to prevent require sync manually. - PCH

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

2022-05-24 Thread Kito Cheng via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb166aa833e44: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

2022-05-20 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 430911. kito-cheng added a comment. Changes: - Apply @craig.topper's suggestion. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125893/new/ https://reviews.llvm.org/D125893 Files:

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

2022-05-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 430391. kito-cheng added a comment. Changes: - clang-format has applied on unexpected part, remove that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125893/new/ https://reviews.llvm.org/D125893 Files:

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

2022-05-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 430390. kito-cheng added a comment. Changes: - Fix dumb typo... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125893/new/ https://reviews.llvm.org/D125893 Files:

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

2022-05-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. kito-cheng added a reviewer: khchen. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

2022-05-18 Thread Kito Cheng via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rG1467e01f8f69: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125886/new/

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

2022-05-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD,

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-16 Thread Kito Cheng via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rG7ff0bf576b84: [RISCV][NFC] Refactor RISC-V vector intrinsic utils. (authored by kito-cheng). Changed prior to commit: https://reviews.llvm.org/D124730?vs=429184=429620#toc Repository: rG LLVM Github

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-13 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:55 +// basic vector type, used to compute type info of arguments. +enum class PrimitiveType : uint8_t { + Invalid, khchen wrote: > I think vector is not a primitive

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-13 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 429184. kito-cheng marked 3 inline comments as done. kito-cheng added a comment. Changes: - Address @khchen's comment. - Use new hash scheme for cache the result of computeType. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaRVVLookup.cpp:91 +struct RVVIntrinsicDef { + std::string Name; + std::string GenericName; khchen wrote: > why do we need to declare Name as std::string here but RVVIntrinsicRecord use > `const

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 426285. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. Changes: - Minor tweak. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Files:

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 426284. kito-cheng marked 4 inline comments as done. kito-cheng added a comment. Changes: - Add more comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 426281. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. Changes: - Split out refactor part to D124730 . - Add more comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 426276. kito-cheng added a comment. Changes: - Extract more utils functions to RISCVVIntrinsicUtils Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124730/new/ https://reviews.llvm.org/D124730 Files:

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal,

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

2022-04-29 Thread Kito Cheng via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG41b951c92931: [RISCV] Fix int16 - __fp16 conversion code gen (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D124510: [RISCV] Precommit test for D124509

2022-04-29 Thread Kito Cheng via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG02c7de3a4c32: [RISCV] Precommit test for D124509 (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D124510: [RISCV] Precommit test for D124509

2022-04-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal,

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

2022-04-27 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal,

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

2022-04-26 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. > And I want to know that do you have any documents about intrinsic of bitmanip > extension, like RISC-V Vector Extension Intrinsic Document. No, we didn't a formal document for that, I expect we will have one once this finalized

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

2022-04-20 Thread Kito Cheng via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf26c41e8dd28: [RISCV] Moving RVV intrinsic type related util to clang/Support (authored by kito-cheng). Changed prior to commit:

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

2022-04-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. > Thank you for the explanation. I still don't think this is really "Support" > material, but I'm also struggling to think of a better place to put it in an > existing directory in Clang aside from Basic, but that would still be a bit > of a layering violation it

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

2022-04-14 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 422786. kito-cheng marked an inline comment as done. kito-cheng added a comment. Fix comment in RISCVVIntrinsicUtils.h...again :P Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

2022-04-14 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 422783. kito-cheng added a comment. Fix comment in RISCVVIntrinsicUtils.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/ https://reviews.llvm.org/D121984 Files:

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

2022-04-14 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Hi @aaron.ballman: > Why shouldn't this live in clang/utils/TableGen along with the others? We plan to use those stuffs on clang side in https://reviews.llvm.org/D111617, my original change was put those stuffs on `llvm/Support`, but actually those stuffs are only

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-04-08 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. @MaskRay I've move those stuffs into clang/Support which is introduce by this patch, and also keep those table gen stuffs in clang-tblgen, did you mind take a look? Thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-04-08 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 421477. kito-cheng added a comment. Changes: - Move those stuffs into clang/Support instead of llvm/Support - Keep table gen staffs in clang/utils/TableGen/RISCVVEmitter.cpp Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-04-08 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Oh, apology, I guess I just miss the discussion, let me revert that again. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/ https://reviews.llvm.org/D121984 ___

[PATCH] D122629: [RISCV] Add index check for vset/vget

2022-03-29 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122629/new/ https://reviews.llvm.org/D122629

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-03-28 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a subscriber: akuegel. kito-cheng added a comment. Hi @MaskRay, @akuegel has removed the `llvm/TableGen/*`, so I guess the issue you mentioned in https://github.com/llvm/llvm-project/commit/c0eb9b4cdef6049ebabb4018d3c9dcb0dc699868 is resolved by

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-03-28 Thread Kito Cheng via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGad57e10dbca2: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support (authored by kito-cheng). Changed prior to commit:

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

2022-03-20 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so here is note from my site: RISC-V psABI doc still say "we don't guarantee the stability of `ILP32E`", the reason is RV32E still not a ratified extension, but as psABI chair, what I can

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

2022-03-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. > If I understand correctly, E can't be combined with D in current > specification since E must use ILP32E calling convention. Calling convention and extensions are separated, calling convention are specify the how argument passing and the register convention, so

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-03-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng created this revision. Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal,

[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

2022-03-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added subscribers: s, arichardson. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121345/new/

[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

2022-03-13 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:727 + if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zhinx")) +return createStringError( Zvfh require `Zfhmin` rather than `Zfh` Spec: `The Zvfh extension

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