[PATCH] D97912: [doc] Document that __fp16 will apply default argument promotion rule.

kito-cheng created this revision. kito-cheng requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. ACLE didn't specify the default argument promotion rule on __fp16, but the current implementation both on GCC and clang are applied default

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

kito-cheng added a comment. Could you also update macros and attributes which implemented in https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94583/new/

[PATCH] D94403: [RISCV] Implement new architecture extension macros

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 ___ cfe-commits mailing list

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

kito-cheng added a comment. @jrtc27 just let you know I have same concern too, that's one major reason why we don't upstream those extension on GNU toolchain... we are intend to introduce an internal revision number on ELF attribute in near future, e.g. v-ext 0.9.1 / v0p9p1 to prevent

[PATCH] D94403: [RISCV] Implement new architecture extension macros

kito-cheng added a comment. In D94403#2512232 , @asb wrote: > @kito-cheng could you please confirm that this patch handles sub-extensions > in the same way GCC does. i.e. -march=rv32izbb0p92 defines `__riscv_zbb` but > NOT `__riscv_b`? Yes :)

[PATCH] D94403: [RISCV] Implement new architecture extension macros

kito-cheng accepted this revision. kito-cheng added a comment. I believe the behavior has aligned to GCC now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 ___

[PATCH] D94403: [RISCV] Implement new architecture extension macros

kito-cheng added a comment. Just note how current GCC implemented, GCC implement that like implied extension, e.g. `V` implied `Zvamo` and `Zvlsseg`, so `__riscv_zvamo` is naturally defined when `V`-ext is enabled. Comment at: clang/lib/Basic/Targets/RISCV.cpp:148 + if

[PATCH] D94403: [RISCV] Implement new architecture extension macros

kito-cheng added a comment. That's my fault, I didn't specify the behavior of sub-extension clearly on the spec, but I think it would be great if we also define sub-extension marcos, since it would be easier to check when some core only implement sub-extension, and the code can just check the

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

kito-cheng added a comment. Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related implementation, but I could be wrong since I am not LLVM expert, in case you have implemented, you need a test case for that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

kito-cheng added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:67 +RVV_VECTOR_TYPE_INT("__rvv_int8m2_t", RvvInt8m2, RvvInt8m2Ty, 16, 8, 1, true) +RVV_VECTOR_TYPE_INT("__rvv_int8m4_t", RvvInt8m4, RvvInt8m4Ty, 32, 8, 1, true)

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng marked an inline comment as done. kito-cheng added a comment. @MaskRay Thanks, that's first time I know the suffix `-SAME` :P CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89025/new/ https://reviews.llvm.org/D89025 ___

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng updated this revision to Diff 298293. kito-cheng added a comment. ChangeLog: - Update testcase according to MaskRay's suggestion. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89025/new/ https://reviews.llvm.org/D89025 Files: clang/include/clang/Driver/Options.td

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng marked 3 inline comments as done. kito-cheng added a comment. In D89025#2327749 , @luismarques wrote: > In D89025#2324334 , @khchen wrote: > >> RISCV supports `-mcpu` with default empty arch to align

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng updated this revision to Diff 298060. kito-cheng added a comment. ChangeLog - Fix wording in comment - Add more comment in testcase - Fix format issue. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89025/new/ https://reviews.llvm.org/D89025 Files:

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng added a comment. > If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or > unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang > with GCC. But I wonder if this might be too problematic, in terms of > compatibility. I am also working

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng created this revision. kito-cheng added reviewers: asb, evandro, lenary, khchen. kito-cheng added projects: LLVM, clang. Herald added subscribers: llvm-commits, cfe-commits, dang, luismarques, apazos, sameer.abuasal, pzheng, pengfei, s.egerton, Jim, benna, psnobl, jocewei, PkmX,

[PATCH] D71124: [RISCV] support clang driver to select cpu

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:478 // 1. Explicit choices using `--with-abi=` - // 2. A default based on `--with-arch=`, if provided - // 3. A default based on the target triple's arch + // 2. A default based on

[PATCH] D71124: [RISCV] support clang driver to select cpu

kito-cheng added a comment. Another proposal for -mcpu and -mtune: Decoupling the -mcpu and -mtune option, -mcpu only accept concrete CPU, and -mtune for micro-arch/pipeline model, they accept different option set. e.g. -mcpu=sifive-e24 # Imply -march=rv32imafc -mtune=sifive-2-series

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

kito-cheng added a comment. Seems like this patch mixed with LTO related changes? Could you clean it up? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72245/new/ https://reviews.llvm.org/D72245 ___ cfe-commits mailing list

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1548 +{M.gccSuffix(), + "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix()}); + }); It could be "riscv32-unknown-elf" other than

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:387 + +void riscv::addGoldOptions(const ToolChain , + const llvm::opt::ArgList , MaskRay wrote: > gold doesn't support RISC-V, does it? Gold

[PATCH] D67066: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal,

[PATCH] D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos, lewis-revill. Herald added subscribers: cfe-commits, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217,

[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

kito-cheng updated this revision to Diff 161990. kito-cheng added a comment. Herald added subscribers: jocewei, the_o, brucehoult, MartinMosbeck, mgrang, edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar. Changes: - Add test. https://reviews.llvm.org/D50043 Files:

[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, rkruppe, rogfer01, shiva0217, fedor.sergeev. RISC-V target using -fuse-init-array even for bare-mental target. Repository: rC Clang https://reviews.llvm.org/D50043 Files:

[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

kito-cheng added a comment. Herald added subscribers: rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, jrtc27. ping, Alex, could you commit that? Repository: rC Clang https://reviews.llvm.org/D46822 ___ cfe-commits mailing list

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

kito-cheng added inline comments. Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:130 + // which may override the defaults. + handleTargetFeaturesGroup(Args, Features, options::OPT_m_riscv_Features_Group); } This part should move to the begin of the

[PATCH] D45284: [RISCV] More validations on the input value of -march=

kito-cheng added a comment. Long time ago, GCC also accept upper case too, but I have no idea why Andrew change that? I guess one possible reason is because multi-lib? [1] https://github.com/riscv/riscv-gcc/commit/6531a11f03ec3a95cd8b9033daeab0ebf23b5472 https://reviews.llvm.org/D45284

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

kito-cheng updated this revision to Diff 140959. kito-cheng added a comment. Changes: - Reorder marco define into canonical order which specified in ISA manual. - Add missing test for marco. Repository: rC Clang https://reviews.llvm.org/D44727 Files: lib/Basic/Targets/RISCV.cpp

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

kito-cheng updated this revision to Diff 140913. kito-cheng added a comment. Changes: - Add testcase for TargetFeature: riscv, riscv32 and riscv64 Repository: rC Clang https://reviews.llvm.org/D44727 Files: lib/Basic/Targets/RISCV.cpp lib/Basic/Targets/RISCV.h

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

kito-cheng added a comment. Hi Eli: Thanks your advise, I've checked those marco are match with GCC :) Repository: rC Clang https://reviews.llvm.org/D44727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

kito-cheng updated this revision to Diff 140046. kito-cheng retitled this revision from "[RISCV] Implement getTargetDefines, handleTargetFeatures and hasFeature for RISCVTargetInfo" to "[RISCV] Extend getTargetDefines for RISCVTargetInfo". kito-cheng edited the summary of this revision.

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng marked 4 inline comments as done. kito-cheng added a comment. Hi Alex: Thanks for your input, check for repeated letter was missed in my last patch :) Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:34 + +// The canonical order specified in ISA manual. +

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 139256. kito-cheng added a comment. Update revision according Alex's review. Changes: - Add testcase for uppercase of -march string. - Add testcase for repeated letter in -march. - Add more comment. - Add several TODO item for diagnostic message

[PATCH] D44727: [RISCV] Implement getTargetDefines, handleTargetFeatures and hasFeature for RISCVTargetInfo

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, shiva0217, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar. kito-cheng added a dependency: D44189: [RISCV] Verify the input value of -march=. This patch implement

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 137970. kito-cheng added a comment. Add test cases for the correct inputs. https://reviews.llvm.org/D44189 Files: lib/Driver/ToolChains/Arch/RISCV.cpp test/Driver/riscv-arch.c Index: test/Driver/riscv-arch.c

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 137687. kito-cheng added a comment. This version only update variable name which changed in last version by accident. https://reviews.llvm.org/D44189 Files: lib/Driver/ToolChains/Arch/RISCV.cpp test/Driver/riscv-arch.c Index:

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng marked 2 inline comments as done. kito-cheng added inline comments. Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:48 + break; +default: + // First letter should be 'i' or 'g'. apazos wrote: > In the switch cases move default to first

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 137547. Repository: rC Clang https://reviews.llvm.org/D44189 Files: lib/Driver/ToolChains/Arch/RISCV.cpp test/Driver/riscv-arch.c Index: test/Driver/riscv-arch.c === --- /dev/null +++

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, shiva0217, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar. This patch doing more check and verify the -march= string and will issue and error if it's a invalid

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

kito-cheng added inline comments. Comment at: lib/Basic/Targets/RISCV.h:85 + bool hasInt128Type(const LangOptions ) const override { +return Opts.UseInt128; + } efriedma wrote: > Maybe make this a cross-platform flag, rather than riscv-specific? +1, then

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

kito-cheng added a comment. Hi Eli: > but you want to make int128_t opt-in to avoid the possibility of someone > getting a link error trying to link code built with clang against libgcc.a? Yes, that's the problem we want to avoid, and we actually get the problem if we built libc (newlib) with

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

kito-cheng added a comment. Hi Eli: We need that because compiler-rt implement 128 bits soft floating point with int128_t, and RISC-V need that but RV32 doesn't support int128_t, we know it's can be just return true to support that. but we don't want to bring any ABI contemptible issue

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