[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/michaelmaitland approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/95953 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

@@ -0,0 +1,91 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 --iterations=2 < %s | FileCheck %s --check-prefixes=CHECK,RV64 michaelmaitland wrote: Is

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

https://github.com/michaelmaitland approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

https://github.com/michaelmaitland edited https://github.com/llvm/llvm-project/pull/95427 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", FeatureStdExtC], [TuneNoDefaultUnroll]>; +def SYNTACORE_SCR3_RV32 :

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

https://github.com/michaelmaitland requested changes to this pull request. https://github.com/llvm/llvm-project/pull/95427 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

@@ -0,0 +1,266 @@ +//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +//

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

michaelmaitland wrote: Could you explain these numbers? It looks like data in some columns is missing. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

michaelmaitland wrote: I want to circle back to a comment made by @asb [here](https://github.com/llvm/llvm-project/pull/70294#issuecomment-1782282361): > it's obvious that commercial designs with active support should go in Since this is in BPi-F3, I think that it constitutes as a commercial

[clang] [clang] Distinguish unresolved templates in UnresolvedLookupExpr (PR #89019)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/89019 >From 89a5bbcc89c1e43ac7f2e60f3c234c2c42928c86 Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Wed, 17 Apr 2024 12:24:56 +0800 Subject: [PATCH 1/7] [clang] Distinguish unresolved templates in

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) { } } - if (T->isRVVSizelessBuiltinType()) -checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext)); + if (T->isRVVSizelessBuiltinType() && isa(CurContext)) { +const

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) { } } - if (T->isRVVSizelessBuiltinType()) -checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext)); + if (T->isRVVSizelessBuiltinType() && isa(CurContext)) { +const

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

https://github.com/michaelmaitland edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

https://github.com/michaelmaitland edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) { } } - if (T->isRVVSizelessBuiltinType()) -checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext)); + if (T->isRVVSizelessBuiltinType() && isa(CurContext)) { +const

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || +

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || +

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

https://github.com/michaelmaitland approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/michaelmaitland closed https://github.com/llvm/llvm-project/pull/79929 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79929 >From e5e34889db5d64e5b918f434f16408756e8cb90d Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 29 Jan 2024 12:33:59 -0800 Subject: [PATCH] [RISCV] Add support for RISC-V Pointer Masking This

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79929 >From fafae54117daf3d871e9df63cc4f1430a433edf0 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 29 Jan 2024 12:33:59 -0800 Subject: [PATCH 1/3] [RISCV] Add support for RISC-V Pointer Masking

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79929 >From bc844fb4e033063c0d7b5ab361c44e4823e76fa3 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 29 Jan 2024 12:33:59 -0800 Subject: [PATCH 1/3] [RISCV] Add support for RISC-V Pointer Masking

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

michaelmaitland wrote: > Should you also update the riscv32-toolchain-extra.c and > riscv64-toolchain-extra.c? It is not immediately obvious to me what you had in mind for changing those tests. Could you please clarify? https://github.com/llvm/llvm-project/pull/79929

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79929 >From 0d1c71afab487cc1028fcfc678c111205140ac21 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 29 Jan 2024 12:33:59 -0800 Subject: [PATCH 1/2] [RISCV] Add support for RISC-V Pointer Masking

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/79929 This patch implements the v0.8.1 specification. This patch reports version 0.8 in llvm since `RISCVISAInfo::ExtensionVersion` only has a `Major` and `Minor` version number. This patch includes includes

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires michaelmaitland wrote:

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland edited https://github.com/llvm/llvm-project/pull/79015 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79015 >From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 22 Jan 2024 07:53:55 -0800 Subject: [PATCH 1/6] [RISCV] Add sifive-p670 processor This is an OOO

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -1082,6 +1082,13 @@ def TuneShortForwardBranchOpt def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +// P670 requires a S2V transfer buffer to move scalars

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79015 >From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 22 Jan 2024 07:53:55 -0800 Subject: [PATCH 1/5] [RISCV] Add sifive-p670 processor This is an OOO

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -241,7 +241,17 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" -// + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck

[clang] [llvm] [RISCV] Add Zic64b, Ziccamoa, Ziccif, Zicclsm, Ziccrse, and Za64rs to sifive-p450. (PR #79030)

https://github.com/michaelmaitland approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/79030 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79015 >From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 22 Jan 2024 07:53:55 -0800 Subject: [PATCH 1/4] [RISCV] Add sifive-p670 processor This is an OOO

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79015 >From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 22 Jan 2024 07:53:55 -0800 Subject: [PATCH 1/3] [RISCV] Add sifive-p670 processor This is an OOO

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires michaelmaitland wrote:

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -237,6 +237,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, TuneLUIADDIFusion, TuneAUIPCADDIFusion]>; +def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670",

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland edited https://github.com/llvm/llvm-project/pull/79015 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79015 >From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 22 Jan 2024 07:53:55 -0800 Subject: [PATCH 1/2] [RISCV] Add sifive-p670 processor This is an OOO

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/79015 This is an OOO core that has a vector unit. For more information see https://www.sifive.com/cores/performance-p650-670. Scheduler model and other tuning will come in separate patches. >From

[llvm] [clang] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

@@ -482,5 +482,35 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { Ret.Tune = AttrString; } } + + StringRef MCPU = this->getTargetOpts().CPU; + StringRef MTune = this->getTargetOpts().TuneCPU; + + // attr-cpu override march only

[llvm] [clang] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

@@ -482,5 +482,35 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { Ret.Tune = AttrString; } } + + StringRef MCPU = this->getTargetOpts().CPU; + StringRef MTune = this->getTargetOpts().TuneCPU; + + // attr-cpu override march only

[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

@@ -482,5 +482,35 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { Ret.Tune = AttrString; } } + + StringRef MCPU = this->getTargetOpts().CPU; + StringRef MTune = this->getTargetOpts().TuneCPU; + + // attr-cpu override march only

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

michaelmaitland wrote: I think this was discussed in https://reviews.llvm.org/D150253?id=523696#inline-1464348 https://github.com/llvm/llvm-project/pull/77866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

https://github.com/michaelmaitland closed https://github.com/llvm/llvm-project/pull/76575 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

michaelmaitland wrote: > > The 'b' character is specified to use 'b'. > > Was this sentence supposed to say `bool`? yes, updated. https://github.com/llvm/llvm-project/pull/76575 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

https://github.com/michaelmaitland edited https://github.com/llvm/llvm-project/pull/76575 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/76575 Builtins.def says that bfloat should be represented by the 'y' character, not the 'b' character. The 'b' character is specified to use 'b'. The implementation currently uses 'b' correctly for boolean

[llvm] [clang] [mlir] [llvm][TypeSize] Consider TypeSize of '0' to be fixed/scalable-agnostic. (PR #72994)

michaelmaitland wrote: > Correct, but that is no reason to disallow a value of '0' for TypeSize. Fair enough! https://github.com/llvm/llvm-project/pull/72994 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [mlir] [llvm] [llvm][TypeSize] Consider TypeSize of '0' to be fixed/scalable-agnostic. (PR #72994)

michaelmaitland wrote: > TypeSize::Scalable(0) + TypeSize::Fixed(4) == TypeSize::Fixed(4) >From the [docs](https://llvm.org/docs/LangRef.html#t-vector) > The number of elements is a constant integer value larger than 0; elementtype > may be any integer, floating-point or pointer type. Vectors

[clang] [clang][analyzer] Support `fputc` in StreamChecker (PR #71518)

https://github.com/michaelmaitland closed https://github.com/llvm/llvm-project/pull/71518 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

@@ -78,7 +78,7 @@ def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; } // Predicates = [HasStdExtD] foreach Ext = DExts in { - let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in { + let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in {

[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>; } // Predicates = [HasStdExtF] foreach Ext = FExts in { - let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in { + let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -318,6 +345,16 @@ multiclass VPseudoVC_XVW { + def "Pseudo" # NAME # "_VV_" # mx : VPseudoTernaryNoMaskWithPolicy; michaelmaitland wrote: Is there an 80 character limitation for TableGen? IIRC we haven't set style guidelines for TableGen which is why theres

[clang] [RISCV][GISel] Select G_SELECT (PR #67614)

@@ -239,6 +245,11 @@ bool RISCVInstructionSelector::select(MachineInstr ) { } case TargetOpcode::G_SEXT_INREG: return selectSExtInreg(MI, MIB); + case TargetOpcode::G_SELECT: +if (!selectSelect(MI, MIB, MRI)) + return false; +MI.eraseFromParent();

[clang] [RISCV] Recognize veyron-v1 processor in clang driver. (PR #66703)

https://github.com/michaelmaitland approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/66703 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

michaelmaitland wrote: > > I think you can drop the merge commit using `git rebase -i`. You may have > > to pass `--rebase-merges` to have the ability to drop the merge commit. > > Then you can pull upstream and `git rebase upstream/main`. > > Thanks Michael, I tried but messed it up (I see

[clang-tools-extra] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/michaelmaitland resolved https://github.com/llvm/llvm-project/pull/65535 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

michaelmaitland wrote: > Is there a way to fix this now? I think you can drop the merge commit using `git rebase -i`. You may have to pass `--rebase-merges` to have the ability to drop the merge commit. Then you can pull upstream and `git rebase upstream/main`.

[clang-tools-extra] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

michaelmaitland wrote: > [Merge branch 'llvm:main' into > mgudim_veyron_def](https://github.com/llvm/llvm-project/pull/65535/commits/454b41eea50a3583ab5c29bffbd46bcd633b) The [LLVM GitHub User Guide](https://llvm.org/docs//GitHub.html) recommends to rebase on main instead of merge main.

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

@@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/michaelmaitland review_requested https://github.com/llvm/llvm-project/pull/65535 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)

https://github.com/michaelmaitland unlabeled https://github.com/llvm/llvm-project/pull/65283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)

https://github.com/michaelmaitland unlabeled https://github.com/llvm/llvm-project/pull/65283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)

https://github.com/michaelmaitland unlabeled https://github.com/llvm/llvm-project/pull/65283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 8394694 - [RISCV] Add sifive-x280 processor with all of its extensions

Author: Michael Maitland Date: 2023-05-05T10:02:28-07:00 New Revision: 839469436afcbdf5bb6dc9b081b1bcf3a1b22fea URL: https://github.com/llvm/llvm-project/commit/839469436afcbdf5bb6dc9b081b1bcf3a1b22fea DIFF:

[clang] 6e7ca68 - Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

Author: Michael Maitland Date: 2023-05-05T09:03:06-07:00 New Revision: 6e7ca6839def260e57334040a586934011f0098d URL: https://github.com/llvm/llvm-project/commit/6e7ca6839def260e57334040a586934011f0098d DIFF:

[clang] a11dfd0 - [RISCV] Add sifive-x280 processor with all of its extensions

Author: Michael Maitland Date: 2023-05-05T08:47:57-07:00 New Revision: a11dfd0fe6b1c38495f7de9858a2d1839d2902b9 URL: https://github.com/llvm/llvm-project/commit/a11dfd0fe6b1c38495f7de9858a2d1839d2902b9 DIFF:

[clang] d6bd4ea - Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

Author: Michael Maitland Date: 2023-05-05T08:20:18-07:00 New Revision: d6bd4ea35437b1d39933e9526779e8c6e03125e0 URL: https://github.com/llvm/llvm-project/commit/d6bd4ea35437b1d39933e9526779e8c6e03125e0 DIFF:

[clang] 55e196e - [RISCV] Add sifive-x280 processor with all of its extensions

Author: Michael Maitland Date: 2023-05-05T07:55:07-07:00 New Revision: 55e196e7718c543b4492f2949c13de003a4ba443 URL: https://github.com/llvm/llvm-project/commit/55e196e7718c543b4492f2949c13de003a4ba443 DIFF:

[clang] 003078b - [Clang][Driver] Add -mcpu=help and -mtune=help to clang

Author: Michael Maitland Date: 2023-02-28T10:45:35-08:00 New Revision: 003078b62d8d40fc000462a97c3b70e01cbe4458 URL: https://github.com/llvm/llvm-project/commit/003078b62d8d40fc000462a97c3b70e01cbe4458 DIFF: