@@ -11,7 +11,7 @@
//
s-barannikov wrote:
I guess this file should've been removed.
https://github.com/llvm/llvm-project/pull/93388
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https://github.com/s-barannikov approved this pull request.
https://github.com/llvm/llvm-project/pull/90338
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@@ -21,6 +21,12 @@ char f_int_4(char x) { return x; }
// CHECK-LABEL: define{{.*}} fp128 @f_ld(fp128 noundef %x)
long double f_ld(long double x) { return x; }
+// Empty struct is lowered as a placeholder word parameter.
+struct empty {};
+
+// CHECK-LABEL: define{{.*}} i64
@@ -21,6 +21,12 @@ char f_int_4(char x) { return x; }
// CHECK-LABEL: define{{.*}} fp128 @f_ld(fp128 noundef %x)
long double f_ld(long double x) { return x; }
+// Empty struct is lowered as a placeholder word parameter.
+struct empty {};
+
+// CHECK-LABEL: define{{.*}} i64
@@ -263,7 +263,10 @@ SparcV9ABIInfo::classifyType(QualType Ty, unsigned
SizeLimit) const {
CoerceBuilder CB(getVMContext(), getDataLayout());
CB.addStruct(0, StrTy);
- CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
+ // All structs, even empty ones, should
@@ -21,6 +21,12 @@ char f_int_4(char x) { return x; }
// CHECK-LABEL: define{{.*}} fp128 @f_ld(fp128 noundef %x)
long double f_ld(long double x) { return x; }
+// Empty struct is lowered as a placeholder word parameter.
+struct empty {};
+
+// CHECK-LABEL: define{{.*}} i64
https://github.com/s-barannikov closed
https://github.com/llvm/llvm-project/pull/68550
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https://github.com/llvm/llvm-project/pull/68550
>From 96dd0121b095f92cc66fcfc3ef08a19d0b2d6bec Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH 1/2] [clang] Differentiate between identifier and string
s-barannikov wrote:
Still LGTM
https://github.com/llvm/llvm-project/pull/74927
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s-barannikov wrote:
> Shorts are half an int, so HalfWidth and HalfAlign apply here.
This is not true for our downstream target where `short` has the same width as
`int` (note that the standard allows it).
It would be better to introduce `ShortWidth` / `ShortAlign` fields and
initialize them
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/68550
>From 96dd0121b095f92cc66fcfc3ef08a19d0b2d6bec Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH 1/2] [clang] Differentiate between identifier and string
@@ -82,6 +88,13 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isRegisterReserved(MCPhysReg PhysReg) const {
+if (PhysReg >= SP::G0 && PhysReg <= SP::O7)
+ return ReserveRegister[PhysReg - SP::G0];
@@ -82,6 +88,13 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isRegisterReserved(MCPhysReg PhysReg) const {
+if (PhysReg >= SP::G0 && PhysReg <= SP::O7)
+ return ReserveRegister[PhysReg - SP::G0];
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/74927
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https://github.com/llvm/llvm-project/pull/74927
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@@ -29,6 +29,12 @@ namespace llvm {
class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
+ // Reserve*Register[i] - *#i is not available as a general purpose register.
+ BitVector ReserveGRegister;
s-barannikov wrote:
I was thinking about
@@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
https://github.com/s-barannikov ready_for_review
https://github.com/llvm/llvm-project/pull/68550
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https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/68550
>From 96dd0121b095f92cc66fcfc3ef08a19d0b2d6bec Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH 1/2] [clang] Differentiate between identifier and string
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/68550
>From 96dd0121b095f92cc66fcfc3ef08a19d0b2d6bec Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH] [clang] Differentiate between identifier and string
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/68550
>From 96dd0121b095f92cc66fcfc3ef08a19d0b2d6bec Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH] [clang] Differentiate between identifier and string
@@ -29,6 +29,12 @@ namespace llvm {
class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
+ // Reserve*Register[i] - *#i is not available as a general purpose register.
+ BitVector ReserveGRegister;
s-barannikov wrote:
Can this be a single
@@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
@@ -80,6 +86,11 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isGRegisterReserved(size_t i) const { return ReserveGRegister[i]; }
+ bool isORegisterReserved(size_t i) const { return ReserveORegister[i]; }
+ bool
@@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
https://github.com/s-barannikov closed
https://github.com/llvm/llvm-project/pull/77425
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https://github.com/llvm/llvm-project/pull/77425
>From 13e6d0818659f0bb4c4f3a41796db2d1465cc82d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 9 Jan 2024 11:44:41 +0300
Subject: [PATCH 1/2] [GISel] Add RegState::Define to temporary defs in
@@ -5119,7 +5119,7 @@ def module_file_info : Flag<["-"], "module-file-info">,
Flags<[]>,
HelpText<"Provide information about a particular module file">;
def mthumb : Flag<["-"], "mthumb">, Group;
def mtune_EQ : Joined<["-"], "mtune=">, Group,
- HelpText<"Only supported on
@@ -5119,7 +5119,7 @@ def module_file_info : Flag<["-"], "module-file-info">,
Flags<[]>,
HelpText<"Provide information about a particular module file">;
def mthumb : Flag<["-"], "mthumb">, Group;
def mtune_EQ : Joined<["-"], "mtune=">, Group,
- HelpText<"Only supported on
@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
@@ -5119,7 +5119,7 @@ def module_file_info : Flag<["-"], "module-file-info">,
Flags<[]>,
HelpText<"Provide information about a particular module file">;
def mthumb : Flag<["-"], "mthumb">, Group;
def mtune_EQ : Joined<["-"], "mtune=">, Group,
- HelpText<"Only supported on
@@ -45,7 +45,8 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
public:
SparcSubtarget(const Triple , const std::string ,
- const std::string , const TargetMachine , bool is64bit);
+ const std::string , const std::string ,
https://github.com/s-barannikov approved this pull request.
https://github.com/llvm/llvm-project/pull/77195
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https://github.com/llvm/llvm-project/pull/77195
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s-barannikov wrote:
We do use this option with gcc, this is why I filed the issue.
https://github.com/llvm/llvm-project/pull/69114
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@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
s-barannikov wrote:
Rebased to resolve merge conflicts in Attr.td.
https://github.com/llvm/llvm-project/pull/68550
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https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/68550
>From 96dd0121b095f92cc66fcfc3ef08a19d0b2d6bec Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH] [clang] Differentiate between identifier and string
@@ -98,9 +98,52 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
@@ -1125,6 +1130,10 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ if
@@ -274,20 +274,27 @@ class DefaultIntArgument :
IntArgument {
}
// This argument is more complex, it includes the enumerator type name,
-// a list of strings to accept, and a list of enumerators to map them to.
-class EnumArgument values,
+// a list of possible values, and
s-barannikov wrote:
I think the choice whether or not to support Swift calling convention should be
made by individual targets without providing "safe" default. As pointed out in
the linked PR, supporting Swift CC is not only about enabling the attribute
support -- backend also needs
@@ -98,9 +98,52 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction ) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+// Mark both single register and
@@ -5730,6 +5730,18 @@ def mvis3 : Flag<["-"], "mvis3">,
Group;
def mno_vis3 : Flag<["-"], "mno-vis3">, Group;
def mhard_quad_float : Flag<["-"], "mhard-quad-float">,
Group;
def msoft_quad_float : Flag<["-"], "msoft-quad-float">,
Group;
+foreach i = {1-7} in
@@ -1125,6 +1130,19 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *MRI = Subtarget->getRegisterInfo();
+ unsigned
@@ -1125,6 +1130,19 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *MRI = Subtarget->getRegisterInfo();
@@ -1125,6 +1130,19 @@ Register SparcTargetLowering::getRegisterByName(const
char* RegName, LLT VT,
.Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7",
SP::G7)
.Default(0);
+ const SparcRegisterInfo *MRI = Subtarget->getRegisterInfo();
+ unsigned
https://github.com/s-barannikov approved this pull request.
https://github.com/llvm/llvm-project/pull/75668
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@@ -274,20 +274,27 @@ class DefaultIntArgument :
IntArgument {
}
// This argument is more complex, it includes the enumerator type name,
-// a list of strings to accept, and a list of enumerators to map them to.
-class EnumArgument values,
+// a list of possible values, and
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/68550
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@@ -886,7 +893,7 @@ def ARMInterrupt : InheritableAttr,
TargetSpecificAttr {
// MSP430Interrupt's, MipsInterrupt's and AnyX86Interrupt's spellings
// must match.
let Spellings = [GCC<"interrupt">];
- let Args = [EnumArgument<"Interrupt", "InterruptType",
+ let Args =
@@ -5474,7 +5474,8 @@ def _dyld_prefix_EQ : Joined<["--"], "dyld-prefix=">;
def _dyld_prefix : Separate<["--"], "dyld-prefix">, Alias<_dyld_prefix_EQ>;
def _encoding_EQ : Joined<["--"], "encoding=">, Alias;
def _encoding : Separate<["--"], "encoding">, Alias;
-def _entry :
https://github.com/s-barannikov approved this pull request.
Thanks, LGTM
(Please make sure to edit the description before merging so that `git log` does
not contain irrelevant information.)
https://github.com/llvm/llvm-project/pull/69114
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Author: Sergei Barannikov
Date: 2023-10-10T09:03:55+03:00
New Revision: 79f87be6888d13a94661be9d8908c83dd2229c9b
URL:
https://github.com/llvm/llvm-project/commit/79f87be6888d13a94661be9d8908c83dd2229c9b
DIFF:
@@ -248,7 +248,7 @@ class HashBuilder : public HashBuilderBase {
/// template
s-barannikov wrote:
This should've been updated too, I guess. Same below.
https://github.com/llvm/llvm-project/pull/68279
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https://github.com/llvm/llvm-project/pull/68550
>From 7199c73d5c9dc04c5c4a1915fc9f5bb0e824d40a Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 9 Oct 2023 01:38:33 +0300
Subject: [PATCH] [clang] Differentiate between identifier and string
@@ -45,7 +45,7 @@ int __attribute__((pcs("aapcs", "aapcs"))) pcs1(void); //
expected-error {{'pcs'
int __attribute__((pcs())) pcs2(void); // expected-error {{'pcs' attribute
takes one argument}}
int __attribute__((pcs(pcs1))) pcs3(void); // expected-error {{'pcs' attribute
s-barannikov wrote:
I'll add some test for 'interrupt' attribute that is the only attribute
affected by `emitClangAttrUnevaluatedStringLiteralList` changes.
https://github.com/llvm/llvm-project/pull/68550
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https://github.com/llvm/llvm-project/pull/68550
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https://github.com/s-barannikov created
https://github.com/llvm/llvm-project/pull/68550
EnumArgument may be a string or an identifier. If it is a string, it should be
parsed as unevaluated string literal. Add IsString flag to EnumArgument so that
the parser can choose the correct parsing
https://github.com/s-barannikov approved this pull request.
LGTM with the suggestion applied.
https://github.com/llvm/llvm-project/pull/68277
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@@ -3088,9 +3088,6 @@ void ItaniumCXXABI::EmitThreadLocalInitFuncs(
CharUnits Align = CGM.getContext().getDeclAlign(VD);
Val = Builder.CreateAlignedLoad(Var->getValueType(), Val, Align);
}
-if (Val->getType() != Wrapper->getReturnType())
- Val =
@@ -2138,6 +2138,8 @@ class IRBuilderBase {
return Insert(CastInst::CreatePointerCast(V, DestTy), Name);
}
+ // With opaque pointers enabled, this is same as CreateAddressSpaceCast.
s-barannikov wrote:
I'll try to rephrase @arsenm comment.
If the
@@ -3088,9 +3088,6 @@ void ItaniumCXXABI::EmitThreadLocalInitFuncs(
CharUnits Align = CGM.getContext().getDeclAlign(VD);
Val = Builder.CreateAlignedLoad(Var->getValueType(), Val, Align);
}
-if (Val->getType() != Wrapper->getReturnType())
- Val =
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?=
Message-ID:
In-Reply-To:
@@ -26,6 +28,66 @@ static_assert(number != 10, ""); // expected-error{{failed}}
\
//
s-barannikov wrote:
> Why don't just turn SLocEntry into a POD (if it is not yet already) and use
> SmallVector::resize_for_overwrite? That way the vector will not be
> initialized and the OS will only allocate physical memory on the first access
> to a page.
Never mind, it isn't "just", the
s-barannikov wrote:
Why don't just turn SLocEntry into a POD and use
SmallVector::resize_for_overwrite? That way the vector will not be initialized
and the OS will only allocate physical memory on the first access to a page.
https://github.com/llvm/llvm-project/pull/66430
Author: Sergei Barannikov
Date: 2023-09-05T19:14:09+03:00
New Revision: 18a628ec4ef72bcc005e2e9d5757445c31c6e2f8
URL:
https://github.com/llvm/llvm-project/commit/18a628ec4ef72bcc005e2e9d5757445c31c6e2f8
DIFF:
Author: Sergei Barannikov
Date: 2023-08-30T11:46:54+03:00
New Revision: a7eaaba69906d3305752cb738332b9365e666def
URL:
https://github.com/llvm/llvm-project/commit/a7eaaba69906d3305752cb738332b9365e666def
DIFF:
Author: Sergei Barannikov
Date: 2023-06-29T20:29:38+03:00
New Revision: 2348902268613a2120bc2d7f3fc8b683d4c114d7
URL:
https://github.com/llvm/llvm-project/commit/2348902268613a2120bc2d7f3fc8b683d4c114d7
DIFF:
Author: Youngsuk Kim
Date: 2023-06-18T04:13:15+03:00
New Revision: 44e63ffe2bf7e5c026b828054d67088239939e81
URL:
https://github.com/llvm/llvm-project/commit/44e63ffe2bf7e5c026b828054d67088239939e81
DIFF:
https://github.com/llvm/llvm-project/commit/44e63ffe2bf7e5c026b828054d67088239939e81.diff
Author: Sergei Barannikov
Date: 2023-06-17T07:14:43+03:00
New Revision: 63534779b4ef1816e2961246011e2ec3be110d27
URL:
https://github.com/llvm/llvm-project/commit/63534779b4ef1816e2961246011e2ec3be110d27
DIFF:
Author: Youngsuk Kim
Date: 2023-06-16T22:07:32+03:00
New Revision: 0f4d48d73d3941ed554ecd9d4bb285176ec01954
URL:
https://github.com/llvm/llvm-project/commit/0f4d48d73d3941ed554ecd9d4bb285176ec01954
DIFF:
https://github.com/llvm/llvm-project/commit/0f4d48d73d3941ed554ecd9d4bb285176ec01954.diff
Author: Sergei Barannikov
Date: 2023-06-04T14:35:32+03:00
New Revision: e8bd2a57849e1c193341db99186abb903eb9579d
URL:
https://github.com/llvm/llvm-project/commit/e8bd2a57849e1c193341db99186abb903eb9579d
DIFF:
Author: Sergei Barannikov
Date: 2023-05-19T23:55:08+03:00
New Revision: 940b02095bf986b5bcc365dc97667a27176c3b13
URL:
https://github.com/llvm/llvm-project/commit/940b02095bf986b5bcc365dc97667a27176c3b13
DIFF:
Author: Sergei Barannikov
Date: 2023-05-19T23:55:21+03:00
New Revision: f60cc01e9e75785dd2476c7e05da689be5a99839
URL:
https://github.com/llvm/llvm-project/commit/f60cc01e9e75785dd2476c7e05da689be5a99839
DIFF:
Author: Sergei Barannikov
Date: 2023-05-19T23:55:15+03:00
New Revision: 0a86e05d1da0f544920b1eff6656c5577fb6562f
URL:
https://github.com/llvm/llvm-project/commit/0a86e05d1da0f544920b1eff6656c5577fb6562f
DIFF:
Author: Sergei Barannikov
Date: 2023-05-19T23:55:02+03:00
New Revision: 5a646ed6835f2686cc0574047ce3c9bbaf323ea3
URL:
https://github.com/llvm/llvm-project/commit/5a646ed6835f2686cc0574047ce3c9bbaf323ea3
DIFF:
Author: Sergei Barannikov
Date: 2023-05-19T23:54:55+03:00
New Revision: f2492f7cf0b175d5d9403cbfc970a521adbde659
URL:
https://github.com/llvm/llvm-project/commit/f2492f7cf0b175d5d9403cbfc970a521adbde659
DIFF:
Author: Sergei Barannikov
Date: 2023-05-18T17:01:11+03:00
New Revision: 0bf5f632ed53cb8c986d69168589228014522e1b
URL:
https://github.com/llvm/llvm-project/commit/0bf5f632ed53cb8c986d69168589228014522e1b
DIFF:
Author: Sergei Barannikov
Date: 2023-05-18T04:29:16+03:00
New Revision: 7971d91bbf903b894936e663e67e03ffc0c29004
URL:
https://github.com/llvm/llvm-project/commit/7971d91bbf903b894936e663e67e03ffc0c29004
DIFF:
Author: Sergei Barannikov
Date: 2023-05-16T19:09:27+03:00
New Revision: 25729c87f4f93ab3902ed65dcdcbac824bda5385
URL:
https://github.com/llvm/llvm-project/commit/25729c87f4f93ab3902ed65dcdcbac824bda5385
DIFF:
Author: Sergei Barannikov
Date: 2023-05-15T19:56:28+03:00
New Revision: cc7dc90481d93734a56098470879189cb2e2c127
URL:
https://github.com/llvm/llvm-project/commit/cc7dc90481d93734a56098470879189cb2e2c127
DIFF:
Author: Sergei Barannikov
Date: 2023-02-16T15:19:24+03:00
New Revision: 574e417460cdfebb8157fbe61b6a015e44856f64
URL:
https://github.com/llvm/llvm-project/commit/574e417460cdfebb8157fbe61b6a015e44856f64
DIFF:
Author: Sergei Barannikov
Date: 2023-02-01T05:23:43+03:00
New Revision: a7fbca40805ca414a9dc37b91075e89e6a3b75d5
URL:
https://github.com/llvm/llvm-project/commit/a7fbca40805ca414a9dc37b91075e89e6a3b75d5
DIFF:
Author: Sergei Barannikov
Date: 2023-01-16T15:59:31+03:00
New Revision: 8a0e0c226018a77ea148e128c97c2592e6f25416
URL:
https://github.com/llvm/llvm-project/commit/8a0e0c226018a77ea148e128c97c2592e6f25416
DIFF:
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