Author: Wang Pengcheng
Date: 2024-04-08T14:59:17+08:00
New Revision: eaa063f0c6d51a3b561bc2007fe95420949f42d1
URL:
https://github.com/llvm/llvm-project/commit/eaa063f0c6d51a3b561bc2007fe95420949f42d1
DIFF:
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
wangpc-pp wrote:
Windows CI is passed now, many thanks to @AaronBallman @vgvassilev!
I may land this in a few days if there is no more comment. :-)
https://github.com/llvm/llvm-project/pull/83774
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@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/84448
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https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/84448
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84877
>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/84877
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https://github.com/wangpc-pp updated
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>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/5] [clang] Enable sized deallocation by default in C++14
onwards
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/4] [clang] Enable sized deallocation by default in C++14
onwards
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/3] [clang] Enable sized deallocation by default in C++14
onwards
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/2] [clang] Enable sized deallocation by default in C++14
onwards
Author: Wang Pengcheng
Date: 2024-03-22T23:21:11+08:00
New Revision: b44771f480385fa93ba7719a57e759e19747e709
URL:
https://github.com/llvm/llvm-project/commit/b44771f480385fa93ba7719a57e759e19747e709
DIFF:
Author: Wang Pengcheng
Date: 2024-03-22T18:49:25+08:00
New Revision: 6e755c51a916dc521ffe89738bcab47a5442ad06
URL:
https://github.com/llvm/llvm-project/commit/6e755c51a916dc521ffe89738bcab47a5442ad06
DIFF:
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/76357
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wangpc-pp wrote:
> > Not entirely certain what you're asking, but MSVC CRT does have a
> > definition for sized delete:
> > ```
> > _CRT_SECURITYCRITICAL_ATTRIBUTE
> > void __CRTDECL operator delete(void* const block, size_t const) noexcept
> > {
> > operator delete(block);
> > }
> > ```
>
wangpc-pp wrote:
> > > There is a Windows failure that I can't reproduce:
> > > https://buildkite.com/llvm-project/github-pull-requests/builds/46331 Can
> > > someone help me to figure out what is wrong?
> >
> >
> > I'm not certain what's going on yet, but it smells a bit like the
> >
wangpc-pp wrote:
This breaks CI `Test documentation build` like:
https://github.com/llvm/llvm-project/actions/runs/8339765845/job/22822367034
https://github.com/llvm/llvm-project/pull/83149
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https://github.com/llvm/llvm-project/pull/83774
>From 26245679b0f40b510e628aaed091739e9931c29c Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/5] [clang] Enable sized deallocation by default in C++14
onwards
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option
This PR
wangpc-pp wrote:
There is a Windows failure that I can't reproduce:
https://buildkite.com/llvm-project/github-pull-requests/builds/46331
Can someone help me to figure out what is wrong?
https://github.com/llvm/llvm-project/pull/83774
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@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option
This PR implements
wangpc-pp wrote:
> Should we use strings like ARM does so we can get register by name?
Good point! We may provide two kinds of builtins: one by name, and another by
CSR number.
We should continue @lenary's proposal and discuss it in
https://github.com/riscv-non-isa/riscv-toolchain-conventions
https://github.com/wangpc-pp approved this pull request.
LGTM. cc @asb @topperc
Some context of RISCV target:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/62
https://github.com/llvm/llvm-project/pull/85350
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wangpc-pp wrote:
GCC gained its `__arm_rsr` and `__arm_wsr` support last year (October, 2023):
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631855.html. So there is
no stable released GCC version that supports these builtins.
Clang supported these builtins about nine years ago:
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
wangpc-pp wrote:
> We discussed this on the sync-up call and @preames very rightly pointed out
> that we should take a step back here...from a user perspective, what does
> specifying a profile via `-mcpu` provide that specifying it via `-march`
> doesn't? We weren't able to answer that in
wangpc-pp wrote:
> > > I support adding these builtins personally, but I think we need more
> > > discussions on the design. We can achieve the same thing via inline
> > > assemblies, that's true. But, from the compiler side, inline assemblies
> > > are kind of barriers, we can't do a lot of
wangpc-pp wrote:
I support adding these builtins personally, but I think we need more
discussions on the design.
We can achieve the same thing via inline assemblies, that's true. But, from the
compiler side, inline assemblies are kind of barriers, we can't do a lot of
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option
This PR
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option
This PR
wangpc-pp wrote:
I think we will add attributes automatically?
```shell
~/workspace# cat a.S
.globl foo
.p2align1
.type foo,@function
foo:
ret
~/workspace# clang -march=rv64gcv -c a.S
~/workspace# llvm-readobj -A a.o
File: a.o
Format: elf64-littleriscv
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From 26245679b0f40b510e628aaed091739e9931c29c Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/4] [clang] Enable sized deallocation by default in C++14
onwards
wangpc-pp wrote:
> The `__cpp_sized_deallocation` feature test macro should be set to 201309L
This has been done.
https://github.com/llvm/llvm-project/blob/1d900e298449d43547312364751f730b7a0d07d1/clang/lib/Frontend/InitPreprocessor.cpp#L690C1-L692C1
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/83774
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@@ -2912,16 +2912,70 @@ static bool sdkSupportsBuiltinModules(const
Darwin::DarwinPlatformKind
}
}
-void Darwin::addClangTargetOptions(const llvm::opt::ArgList ,
- llvm::opt::ArgStringList ,
-
@@ -7105,10 +7105,15 @@ void Clang::ConstructJob(Compilation , const
JobAction ,
Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args,
options::OPT_fno_relaxed_template_template_args);
- // -fsized-deallocation is off by default, as
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/84877
As discussed in
https://github.com/llvm/llvm-project/pull/76357#discussion_r1518452608,
we may need to add generic CPUs for profiles.
I don't know if we need S-mode profile CPUs.
>From
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option
This PR implements
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
wangpc-pp
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/wangpc-pp commented:
The code is OK I think.
One question: how will these builtins be used? Are their semantics bound to
specific extensions that extend MOPs?
https://github.com/llvm/llvm-project/pull/79971
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@@ -89,5 +89,13 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
+// Zimop extension
wangpc-pp wrote:
You may
@@ -5588,6 +5588,14 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const
TargetInfo ,
// Check if rnum is in [0, 10]
case RISCV::BI__builtin_riscv_aes64ks1i:
return SemaBuiltinConstantArgRange(TheCall, 1, 0, 10);
+ // Check if n of mop.r.[n] is in [0, 31]
+ case
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From bd9b759d853d8196ae893a90442a3c3e7e5fa74d Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/83831
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/83831
This is used in profile, but somehow we missed it.
>From 7e0815dda185c635448bf08c150fc54d9f9d4b5f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Mon, 4 Mar 2024 19:51:15 +0800
Subject: [PATCH] [RISCV]
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/83774
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/83774
Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.
This is another try of
@@ -839,6 +860,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/wangpc-pp approved this pull request.
LGTM.
Will it be in LLVM 18? Or we need more time to examine its robustness?
https://github.com/llvm/llvm-project/pull/83195
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/82152
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From c7f2589692c4d310d4e61ebcbbceb3602b0ef227 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
wangpc-pp
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/llvm/llvm-project/pull/76357
>From c7f2589692c4d310d4e61ebcbbceb3602b0ef227 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/wangpc-pp ready_for_review
https://github.com/llvm/llvm-project/pull/76357
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wangpc-pp wrote:
> Can we implement this in `computeKnownBitsFromOperator/getRangeForIntrinsic`?
>
> https://github.com/llvm/llvm-project/blob/b21e3282864c9f7ad656c64bc375f5869ef76d19/llvm/lib/Analysis/ValueTracking.cpp#L1578-L1584
Thanks! We can implement this partly (will create another PR
wangpc-pp wrote:
Can this be tested? I don't know what the affects are.
https://github.com/llvm/llvm-project/pull/82152
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https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/80279
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wangpc-pp wrote:
> The changes seem reasonable to me but I'd feel more comfortable if the
> functionality was also being used (so that we'd get test coverage verifying
> its correctness). Do you think it would be reasonable to include the RISCV
> changes as well?
Yeah, I separated RISCV
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/80279
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wangpc-pp wrote:
Ping for comments.
https://github.com/llvm/llvm-project/pull/79975
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@@ -1612,6 +1613,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN: -o - | FileCheck
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/79248
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/79248
>From 63ca83d205a361464ec59e9c134fafa795b17cef Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 24 Jan 2024 11:22:03 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/80279
RISCV target will use this parameter, so we need a way to specify
it.
>From b0728e172ab9d6c139fc665b739d51af20a27bd2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 1 Feb 2024 19:47:46 +0800
wangpc-pp wrote:
> Also I guess most of RVV intrinsic could add `const` too, that could help
> some generic optimization work better like CSE.
This PR doesn't add the `const` attribute, I don't know if adding `const` may
help to optimize.
https://github.com/llvm/llvm-project/pull/79975
wangpc-pp wrote:
> I'm concerned that llvm.assume is handled differently than a branch to
> unreachable in the middle end.
Actually the CodeGen part is written by referring to the LLVM IR generated by
unreachable way (https://godbolt.org/z/vf1v7f744).
> Have you tested that these assumes
wangpc-pp wrote:
After some random thinking, I think these assumptions may need to be added to
vsetvli/vsetvlimax LLVM intrinsics instead of adding them in Clang CodeGen. In
this way, we can make other frontends like `flang/Rust/TVM/MLIR/...` benefit
from these assumptions. Is it possible? I
wangpc-pp wrote:
What's the status of Zalasr extension? Is it an official extension now?
https://github.com/llvm/llvm-project/pull/79911
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/79811
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wangpc-pp wrote:
Should we backport this to llvm 18?
https://github.com/llvm/llvm-project/pull/79811
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https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/78970
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/79409
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https://github.com/wangpc-pp approved this pull request.
Oh sorry, I was going to approve this before llvm 18 branch but I forgot.
Should we backport this to llvm 18?
https://github.com/llvm/llvm-project/pull/76551
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/6] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
https://github.com/wangpc-pp commented:
[Ssstrict](https://github.com/riscv/riscv-profiles/commit/962bcc6764f3b6ccfbdcfe030c77b05c6a475c5e)
too? I was going to add it but why not just hitchhike this PR? :-)
https://github.com/llvm/llvm-project/pull/79399
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
@@ -1307,6 +1309,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \
wangpc-pp wrote:
Sorry for that I forgot to
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
@@ -1082,6 +1082,13 @@ def TuneShortForwardBranchOpt
def HasShortForwardBranchOpt :
Predicate<"Subtarget->hasShortForwardBranchOpt()">;
def NoShortForwardBranchOpt :
Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
+// P670 requires a S2V transfer buffer to move scalars
@@ -241,7 +241,17 @@
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck
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