This revision was automatically updated to reflect the committed changes.
Closed by commit rGc88719483c69: [clang-format] Handle Verilog case statements
(authored by sstwcw).
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D128714/new/
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sstwcw updated this revision to Diff 443608.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128714/new/
https://reviews.llvm.org/D128714
Files:
clang/lib/Format/ContinuationIndenter.cpp
clang/lib/Format/Format.cpp
clang/lib/Format/FormatToken.h
HazardyKnusperkeks added inline comments.
Comment at: clang/lib/Format/Format.cpp:1265
LLVMStyle.IndentAccessModifiers = false;
- LLVMStyle.IndentCaseLabels = false;
+ LLVMStyle.IndentCaseLabels = LLVMStyle.isVerilog() ? true : false;
LLVMStyle.IndentCaseBlocks = false;
-
sstwcw created this revision.
sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, curdeius, owenpan.
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These statements are like switch statements in
