[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc86a878e8995: [RISCV] Add Syntacore SCR1 CPU model (authored by dnpetrov-sc, committed by anton-afanasyev). Repository: rG LLVM Github Monorepo

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc updated this revision to Diff 482455. dnpetrov-sc added a comment. - Fixes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302 Files: clang/test/Driver/riscv-cpus.c

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc updated this revision to Diff 482449. dnpetrov-sc marked an inline comment as done. dnpetrov-sc added a comment. - Added syntacore prefix Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

anton-afanasyev added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:14 +// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max). +// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base) +// configurations have essentially same

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added a comment. Should the names be prefixed with "syntacore-". I assume there could be an SCR2, etc. in the future? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

jrtc27 added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:22 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"}) +PROC(SCR1_BASE, {"scr1-base"}, FK_NONE, {"rv32ic"}) +PROC(SCR1_MAX, {"scr1-max"}, FK_NONE, {"rv32imc"})

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; dnpetrov-sc wrote: > craig.topper

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc updated this revision to Diff 480352. dnpetrov-sc edited the summary of this revision. dnpetrov-sc added a comment. - fixed new line at end-of-file in RISCVSchedSCR1.td; - dropped scr1-min (RV32E unsupported). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; craig.topper wrote: > Shouldn't

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:208 +} \ No newline at end of file Add new line Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; Shouldn't this also need

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc created this revision. dnpetrov-sc added reviewers: craig.topper, anton-afanasyev, asi-sc. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,