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This revision was automatically updated to reflect the committed changes.
Closed by commit rG96b52c1eec7b: [Clang][RISCV] Expose vlenb to user (authored
by eopXD).
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eopXD updated this revision to Diff 487302.
eopXD added a comment.
Update code: Avoid emit clang version in test case.
@pcwang-thead Thank you for checking and providing the corresponding
resolution. :)
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rG LLVM Github Monorepo
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pcwang-thead added inline comments.
Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c:33
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"clang version 16.0.0 (g...@github.com:llvm/llvm-project.git
e80f0cc0a318fe8473ba460d6a16166d81b303b1)"}
+//
eopXD updated this revision to Diff 487293.
eopXD marked 5 inline comments as done.
eopXD added a comment.
Address comments from Craig.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D141032/new/
https://reviews.llvm.org/D141032
Files:
pcwang-thead added inline comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:1579
+ llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+ return Builder.CreateCall(F, Metadata);
craig.topper wrote:
>
craig.topper added inline comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:1579
+ llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+ return Builder.CreateCall(F, Metadata);
pcwang-thead wrote:
>
pcwang-thead accepted this revision.
pcwang-thead added a comment.
This revision is now accepted and ready to land.
The code is OK to me, except that a few small comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:1579
+ llvm::Function *F =
+
eopXD marked 2 inline comments as done.
eopXD added inline comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:1565
+ unsigned long __rv = 0;
+ __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+ return __rv;
pcwang-thead wrote:
eopXD updated this revision to Diff 487206.
eopXD marked an inline comment as not done.
eopXD added a comment.
Update code. Apply suggestion from @pcwang-thead.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D141032/new/
pcwang-thead added inline comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:1565
+ unsigned long __rv = 0;
+ __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+ return __rv;
Inline assembly may not be elegant since it can't be
eopXD marked an inline comment as done.
eopXD added inline comments.
Comment at: clang/include/clang/Basic/riscv_vector.td:1559
__asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
break;
}
pcwang-thead wrote:
> Should we
eopXD updated this revision to Diff 486486.
eopXD edited the summary of this revision.
eopXD added a comment.
Update code. Add function `vlenb` instead of extending inside the `vread_csr`
function.
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eopXD added a comment.
Upon a second thought, with future extensions of the intrinsics, we will add
rounding mode and exception intrinsics. The exposure of vxsat, vxrm, and vcsr
in vread_csr and vwrite_csr will confuse user and we should remove them.
Furthermore, vstart is pretty much always
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