[PATCH] D141756: [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGecbf5db88d28: [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is… (authored by eopXD). Changed prior to commit:

[PATCH] D141756: [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141756/new/ https://reviews.llvm.org/D141756 ___ cfe-commits mailing list

[PATCH] D141756: [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke. LGTM, the condition of those predictor function more reasonable now Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION