[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-20 Thread Björn Schäpers via Phabricator via cfe-commits
HazardyKnusperkeks added inline comments. Comment at: clang/lib/Format/TokenAnnotator.cpp:2665 +if (Style.isVerilog() && Precedence == prec::Comma && +VerilogFirstOfType != nullptr) { + addFakeParenthesis(VerilogFirstOfType, prec::Comma);

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-19 Thread sstwcw via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6e473aeffdc1: [clang-format] Put ports on separate lines in Verilog module headers (authored by sstwcw). Changed prior to commit:

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-19 Thread Owen Pan via Phabricator via cfe-commits
owenpan added inline comments. Comment at: clang/lib/Format/TokenAnnotator.cpp:2665 +if (Style.isVerilog() && Precedence == prec::Comma && +VerilogFirstOfType != nullptr) { + addFakeParenthesis(VerilogFirstOfType, prec::Comma); sstwcw wrote: >

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-19 Thread sstwcw via Phabricator via cfe-commits
sstwcw added inline comments. Comment at: clang/lib/Format/TokenAnnotator.cpp:2665 +if (Style.isVerilog() && Precedence == prec::Comma && +VerilogFirstOfType != nullptr) { + addFakeParenthesis(VerilogFirstOfType, prec::Comma); owenpan wrote: >

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-18 Thread Owen Pan via Phabricator via cfe-commits
owenpan added inline comments. Comment at: clang/lib/Format/TokenAnnotator.cpp:2665 +if (Style.isVerilog() && Precedence == prec::Comma && +VerilogFirstOfType != nullptr) { + addFakeParenthesis(VerilogFirstOfType, prec::Comma); And other places

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-17 Thread MyDeveloperDay via Phabricator via cfe-commits
MyDeveloperDay accepted this revision. MyDeveloperDay added a comment. This revision is now accepted and ready to land. Thank you for adding the tests, as I don't know Verilog then I can't really comment on the correctness, as you are mostly in your own scoped verilog functions, I'm fine with

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-17 Thread sstwcw via Phabricator via cfe-commits
sstwcw updated this revision to Diff 498376. sstwcw marked 3 inline comments as done. sstwcw added a comment. - add tests Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143825/new/ https://reviews.llvm.org/D143825 Files:

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-17 Thread sstwcw via Phabricator via cfe-commits
sstwcw marked 3 inline comments as done. sstwcw added inline comments. Comment at: clang/lib/Format/TokenAnnotator.cpp:2836 + Tok = Tok->getNextNonComment(); + } else if (Tok->is(tok::hashhash)) { +// Concatenation. Skip. MyDeveloperDay

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-14 Thread MyDeveloperDay via Phabricator via cfe-commits
MyDeveloperDay added inline comments. Comment at: clang/lib/Format/TokenAnnotator.cpp:2836 + Tok = Tok->getNextNonComment(); + } else if (Tok->is(tok::hashhash)) { +// Concatenation. Skip. are we covering these cases in the unit tests

[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

2023-02-11 Thread sstwcw via Phabricator via cfe-commits
sstwcw created this revision. sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, curdeius, owenpan, rymiel. Herald added a project: All. sstwcw requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. New: module mh1 (input var