[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-18 Thread Pranav Kant via Phabricator via cfe-commits
pranavk added a comment. I forgot to update the differential link in the commit but this patch was merged as part of (https://github.com/llvm/llvm-project/commit/726785b1594c6b567c5c8ddd59075aee726590c6) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-18 Thread Pranav Kant via Phabricator via cfe-commits
pranavk added a comment. This has been superseded by https://reviews.llvm.org/D147266 I forgot to update the link in the final commit here (https://github.com/llvm/llvm-project/commit/726785b1594c6b567c5c8ddd59075aee726590c6) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-17 Thread Pranav Kant via Phabricator via cfe-commits
pranavk closed this revision. pranavk added a comment. > I noticed there was another instance of vbsl being reported recently in > https://github.com/llvm/llvm-project/issues/62642. Hopefully it can be > addresses via extra optimizations too. This is another InstCombine problem -- as soon as

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-16 Thread Dave Green via Phabricator via cfe-commits
dmgreen accepted this revision. dmgreen added a comment. Thanks. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 ___ cfe-commits mailing list

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-15 Thread Pranav Kant via Phabricator via cfe-commits
pranavk added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14361-14363 + for (unsigned Idx = 0; Idx < MainAnd->getNumOperands(); Idx++) { +if (MainAnd->getOperand(Idx) != IA) { +

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-15 Thread Pranav Kant via Phabricator via cfe-commits
pranavk added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14361-14363 + for (unsigned Idx = 0; Idx < MainAnd->getNumOperands(); Idx++) { +if (MainAnd->getOperand(Idx) != IA) { +

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-15 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 522309. pranavk marked 3 inline comments as done. pranavk added a comment. address reviewer comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 Files:

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-14 Thread Dave Green via Phabricator via cfe-commits
dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. Thanks. LGTM with a few extra suggestions. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14357 + // Non-mask operands of both Ands should also be in

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-11 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 521545. pranavk added a comment. More concise pattern matching Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 Files:

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-11 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 521505. pranavk added a comment. add test Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 Files: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-11 Thread Pranav Kant via Phabricator via cfe-commits
pranavk added a comment. tests coming Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-11 Thread Pranav Kant via Phabricator via cfe-commits
pranavk updated this revision to Diff 521474. pranavk edited the summary of this revision. pranavk added a comment. Address reviewer comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147266/new/ https://reviews.llvm.org/D147266 Files:

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-11 Thread Pranav Kant via Phabricator via cfe-commits
pranavk planned changes to this revision. pranavk marked 2 inline comments as done. pranavk added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14343 +// passed to this function. Starting pattern matching with any other +// instruction

[PATCH] D147266: [AArch64] Sink operands to allow for bitselect instructions

2023-05-11 Thread Dave Green via Phabricator via cfe-commits
dmgreen added a comment. Thanks for working on this. I noticed there was another instance of vbsl being reported recently in https://github.com/llvm/llvm-project/issues/62642. Hopefully it can be addresses via extra optimizations too. Can you add a testcase for the issues in