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This revision was automatically updated to reflect the committed changes.
Closed by commit rG74cc4389f37d: [clang-format] Add option for having one port
per line in Verilog (authored by sstwcw).
Repository:
rG LLVM Github Monorepo
sstwcw updated this revision to Diff 510385.
sstwcw added a comment.
- Use lambda
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147327/new/
https://reviews.llvm.org/D147327
Files:
clang/docs/ClangFormatStyleOptions.rst
owenpan added inline comments.
Comment at: clang/lib/Format/TokenAnnotator.cpp:1149-1191
+ if (Style.isVerilog()) {
+const FormatToken *Prev = Tok->getPreviousNonComment();
+const FormatToken *PrevPrev;
+// Identify the parameter list and port list
sstwcw updated this revision to Diff 510244.
sstwcw marked 2 inline comments as done.
sstwcw added a comment.
- Use shorter conditions
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147327/new/
https://reviews.llvm.org/D147327
Files:
HazardyKnusperkeks requested changes to this revision.
HazardyKnusperkeks added inline comments.
This revision now requires changes to proceed.
Comment at: clang/include/clang/Format/Format.h:4185
+ /// For Verilog, put each port on its own line in module instantiations.
+ ///
sstwcw updated this revision to Diff 510038.
sstwcw added a comment.
Generate doc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147327/new/
https://reviews.llvm.org/D147327
Files:
clang/docs/ClangFormatStyleOptions.rst
