[PATCH] D149352: [clang-format] Recognize Verilog type dimension in module header

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4134f836103e: [clang-format] Recognize Verilog type dimension in module header (authored by sstwcw). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D149352: [clang-format] Recognize Verilog type dimension in module header

sstwcw created this revision. sstwcw added a reviewer: curdeius. Herald added projects: All, clang, clang-format. Herald added a subscriber: cfe-commits. Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay. sstwcw requested review of this revision. We had the function