[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

michaelmaitland updated this revision to Diff 518923. michaelmaitland added a comment. Split adding sifive-x280 and vector model between this patch and https://reviews.llvm.org/D149710 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/

[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

craig.topper added a comment. All CPU name additions should be mentioned in the RISC-V section of llvm/docs/ReleaseNotes.rst Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/ https://reviews.llvm.org/D149495

[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:169 +def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, + [Feature64Bit, I would prefer that we add sifive-x280 in a