[PATCH] D151601: [NVPTX] Coalesce register classes for {i16,f16,bf16}, {i32,v2f16,v2bf16}

jlebar accepted this revision. jlebar added a comment. This revision is now accepted and ready to land. I cannot say that I 100% looked over every line, but in principle this seems fine, and if it's passing TF tests then that's pretty strong evidence this is working. Repository: rG LLVM

[PATCH] D151601: [NVPTX] Coalesce register classes for {i16,f16,bf16}, {i32,v2f16,v2bf16}

tra added a comment. I've tested the change on a bunch of tensorflow tests and the patch didn't cause any apparent issues. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151601/new/ https://reviews.llvm.org/D151601