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Closed by commit rG76482078cdd2: [RISCV][POC] Model frm control for vfadd
(authored by eopXD).
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eopXD added inline comments.
Comment at: clang/lib/Sema/SemaChecking.cpp:4816
+ case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tama:
+ case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tama:
craig.topper wrote:
>
craig.topper added inline comments.
Comment at: clang/lib/Sema/SemaChecking.cpp:4816
+ case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tama:
+ case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tama:
not related to
eopXD updated this revision to Diff 539413.
eopXD added a comment.
Change:
- Rebase to latest main
- let `hasPostISelHook = 1` for PseudoVFADD to trigger code under
`AdjustInstrPostInstrSelection`.
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eopXD updated this revision to Diff 539222.
eopXD added a comment.
Under RISCVInsertReadWriteCSR, add implicit depdendency to MI if rounding mode
is FRM_DYN.
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craig.topper added a comment.
I think this conflicts with https://reviews.llvm.org/D154245
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eopXD updated this revision to Diff 538748.
eopXD added a comment.
Fix bug, should be checking MI.readsRegister(RISCV::FRM) under
AdjustInstrPostInstrSelection.
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eopXD updated this revision to Diff 536964.
eopXD added a comment.
Resolve test case failure in llvm/test/CodeGen/RISCV/rvv/combine-vmv.ll
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eopXD updated this revision to Diff 536700.
eopXD added a comment.
Undo the previous diff. There was no bug in the code.
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eopXD updated this revision to Diff 536699.
eopXD added a comment.
Fix bug in ManualCodeGen of vfadd.
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eopXD updated this revision to Diff 536688.
eopXD added a comment.
Update suffix from
`vfadd_vv_i32m1_{policy_suffix, if any}_rm` to
`vfadd_vv_i32m1_rm_{policy_suffix, if any}`
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kito-cheng accepted this revision.
kito-cheng added a comment.
LGTM, Give my blessing, thanks for moving this forward :)
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craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM
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eopXD updated this revision to Diff 535446.
eopXD marked 2 inline comments as done.
eopXD added a comment.
Address more comments from Craig.
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:78
+
+// The value '7' is a hint to this pass to not alter the frm value.
+if (FRMImm == RISCVFPRndMode::DYN)
Don't write 7 here
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:21
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/MC/MCInstrDesc.h"
We can't include a CodeGen header in MCTargetDesc
eopXD updated this revision to Diff 535438.
eopXD marked 6 inline comments as done.
eopXD added a comment.
Address more comments from Craig.
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:78
+// The value '7' is a hint to this pass to not alter the frm value.
+if (FRMImm == 7)
+ continue;
Use `RISCVFPRndMode::DYN`?
eopXD updated this revision to Diff 535425.
eopXD marked 2 inline comments as done.
eopXD added a comment.
Address comment from Craig.
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:105
+.addImm(FRMImm);
+MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
+/*IsImp*/ true));
eopXD added a comment.
Gentle ping.
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eopXD updated this revision to Diff 532996.
eopXD added a comment.
Rebase to latest main.
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eopXD updated this revision to Diff 532839.
eopXD added a comment.
Add SemaChecking and corresponding test case.
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eopXD updated this revision to Diff 532836.
eopXD added a comment.
Rebase: Add `sew` parameter that other templates have added too.
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eopXD updated this revision to Diff 532800.
eopXD added a comment.
Fix ManualCodegen for vfadd.
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eopXD updated this revision to Diff 532797.
eopXD added a comment.
Remove unnecessary include-s.
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eopXD updated this revision to Diff 532796.
eopXD marked an inline comment as done.
eopXD added a comment.
Save and restore FRM in RISCVInsertReadWriteCSR.
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eopXD updated this revision to Diff 532536.
eopXD added a comment.
Herald added a subscriber: qcolombet.
Update code:
- Change value to indicate no rounding mode change from `99` to `7`.
- Add code under `RISCVDAGToDAGISel::performCombineVMergeAndVOps` to deal with
the extra rounding mode
eopXD added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:105
+
+BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRMImm))
+.addImm(FRMImm);
craig.topper wrote:
> Don't we need to restore the original
craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:105
+
+BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRMImm))
+.addImm(FRMImm);
Don't we need to restore the original FRM value after
eopXD updated this revision to Diff 531722.
eopXD added a comment.
Update code based on edit of parent revision.
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eopXD updated this revision to Diff 531701.
eopXD edited the summary of this revision.
eopXD added a comment.
Resolve test case failures.
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eopXD created this revision.
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