This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1a905e823892: [3/8][RISCV] Add rounding mode control variant
for vfmul, vfdiv, vfrdiv, vfwmul (authored by eopXD).
Repository:
rG LLVM Github
eopXD updated this revision to Diff 539434.
eopXD added a comment.
Change:
- Rebase upon latest main and updated parent revisions
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154631/new/
https://reviews.llvm.org/D154631
Files:
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM
Comment at: clang/lib/Sema/SemaChecking.cpp:4824
case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_ta:
+ case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_ta:
eopXD updated this revision to Diff 538004.
eopXD added a comment.
Bump CI.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154631/new/
https://reviews.llvm.org/D154631
Files:
clang/include/clang/Basic/riscv_vector.td
