[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

This revision was automatically updated to reflect the committed changes. Closed by commit rL367399: [RISCV] Add support for floating point registers in inlineasm (authored by simoncook, committed by ). Herald added subscribers: llvm-commits, s.egerton. Herald added a project: LLVM. Changed

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

lenary accepted this revision. lenary added a comment. This revision is now accepted and ready to land. Looks good to me! Thank you! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64737/new/ https://reviews.llvm.org/D64737

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

simoncook added a comment. As an aside, I've noticed a codegen issue when using floating point clobber lists, resulting in the implicit-defs not being added to INLINEASM instructions. I'm working on a fix for that now and will submit a second patch shortly. Repository: rG LLVM Github

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

simoncook created this revision. simoncook added a reviewer: asb. Herald added subscribers: cfe-commits, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso,