This revision was automatically updated to reflect the committed changes.
Closed by commit rGce3d1c6d61dc: [libunwind][RISCV] Add 64-bit RISC-V support
(authored by lenary).
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lenary added a comment.
Yeah, will do.
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mhorne added a comment.
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Thanks Sam and Luis for the review. Could I ask that one of you commit this if
you are able?
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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.
LGTM.
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lenary accepted this revision.
lenary added a comment.
LGTM! Thanks for correcting the preprocessor issues!
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mhorne updated this revision to Diff 232721.
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Files:
libunwind/include/__libunwind_config.h
libunwind/include/libunwind.h
libunwind/src/Registers.hpp
libunwind/src/UnwindCursor.hpp
abidh added inline comments.
Comment at: libunwind/src/Registers.hpp:3765
+inline void Registers_riscv::setFloatRegister(int regNum, double value) {
+#ifdef __riscv_flen == 64
+ assert(validFloatRegister(regNum));
I am building these changes and get the
mhorne added reviewers: compnerd, phosek.
mhorne marked 2 inline comments as done.
mhorne added a comment.
Add some libunwind contributors for additional review.
Comment at: libunwind/src/Registers.hpp:3756
+inline double Registers_riscv::getFloatRegister(int regNum) const {
lenary accepted this revision.
lenary added a comment.
Thanks for updating the patch.
I'm happy for this patch to land, but I would like you to wait for @luismarques
to approve it as well before landing it.
Comment at: libunwind/src/Registers.hpp:3756
+inline double
mhorne marked 3 inline comments as done.
mhorne added inline comments.
Comment at: libunwind/include/__libunwind_config.h:26
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 63
luismarques wrote:
>
mhorne updated this revision to Diff 228799.
mhorne marked an inline comment as done.
mhorne added a comment.
Convert checks for `__riscv_float_abi_double` to `__riscv_flen == 64`.
Fix `_LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV`.
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luismarques requested changes to this revision.
luismarques added inline comments.
This revision now requires changes to proceed.
Comment at: libunwind/include/__libunwind_config.h:26
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
+#define
luismarques added inline comments.
Comment at: libunwind/src/Registers.hpp:3545
+ void setSP(uint64_t value) { _registers[2] = value; }
+ uint64_t getIP() const { return _registers[1]; }
+ void setIP(uint64_t value) { _registers[1] = value; }
luismarques added inline comments.
Comment at: libunwind/src/Registers.hpp:3756
+inline double Registers_riscv::getFloatRegister(int regNum) const {
+#ifdef __riscv_float_abi_double
+ assert(validFloatRegister(regNum));
lenary wrote:
> mhorne wrote:
> > lenary
lenary added inline comments.
Comment at: libunwind/src/Registers.hpp:3756
+inline double Registers_riscv::getFloatRegister(int regNum) const {
+#ifdef __riscv_float_abi_double
+ assert(validFloatRegister(regNum));
mhorne wrote:
> lenary wrote:
> > Is this an
mhorne marked 2 inline comments as done.
mhorne added inline comments.
Comment at: libunwind/src/Registers.hpp:3756
+inline double Registers_riscv::getFloatRegister(int regNum) const {
+#ifdef __riscv_float_abi_double
+ assert(validFloatRegister(regNum));
lenary added a comment.
One query, but this patch is starting to look good.
I'm not a libunwind expert - it would be good to have one of the libunwind
contributors look over this patch yet. Can you add one as a reviewer?
Comment at: libunwind/src/Registers.hpp:3677
+ case
mhorne marked 5 inline comments as done.
mhorne added a comment.
Thanks for the review!
Comment at: libunwind/src/Registers.hpp:3585
+
+inline uint64_t Registers_riscv::getRegister(int regNum) const {
+ if (regNum == UNW_REG_IP)
lenary wrote:
> Do you want to
mhorne updated this revision to Diff 223971.
mhorne added a comment.
Address lenary's comments.
Add a check for __riscv_float_abi_double in getFloat/setFloat.
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Files:
lenary added a comment.
Nice! Thanks for adding support for RISC-V. I like the use of the ABI register
names rather than the numeric names.
I have a few queries/nits, below.
Comment at: libunwind/include/libunwind.h:835
+// 64-bit RISC-V registers
+enum {
mhorne created this revision.
Herald added subscribers: s.egerton, lenary, benna, psnobl, PkmX, rkruppe,
rogfer01, shiva0217, christof, kito-cheng, simoncook, krytarowski, aprantl.
Add unwinding support for 64-bit RISC-V.
This is from the FreeBSD implementation with the following minor
changes:
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