This revision was automatically updated to reflect the committed changes.
Closed by commit rG17f6e18acf5b: [AArch64][SVE] Add SVE intrinsic for LD1RQ
(authored by kmclaughlin).
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sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.
LGTM!
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kmclaughlin updated this revision to Diff 259035.
kmclaughlin marked an inline comment as done.
kmclaughlin added a comment.
- Use Load.getValue(0) when creating a bitcast in performLD1RQCombine
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kmclaughlin added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622
+ if (VT.isFloatingPoint())
+Load = DAG.getNode(ISD::BITCAST, DL, VT, Load);
+
sdesmalen wrote:
> kmclaughlin wrote:
> > sdesmalen wrote:
> > > I'd expect
sdesmalen added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622
+ if (VT.isFloatingPoint())
+Load = DAG.getNode(ISD::BITCAST, DL, VT, Load);
+
kmclaughlin wrote:
> sdesmalen wrote:
> > I'd expect this to then use
kmclaughlin added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622
+ if (VT.isFloatingPoint())
+Load = DAG.getNode(ISD::BITCAST, DL, VT, Load);
+
sdesmalen wrote:
> I'd expect this to then use `Load.getValue(0)` ?
I think
sdesmalen added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622
+ if (VT.isFloatingPoint())
+Load = DAG.getNode(ISD::BITCAST, DL, VT, Load);
+
I'd expect this to then use `Load.getValue(0)` ?
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kmclaughlin updated this revision to Diff 257657.
kmclaughlin marked an inline comment as done.
kmclaughlin added a comment.
Ensure LoadChain is always preserved in performLD1RQCombine
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sdesmalen added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11621
+ if (VT.isFloatingPoint()) {
+SDValue LoadChain = SDValue(Load.getNode(), 1);
+Load = DAG.getMergeValues(
It seems like the LoadChain is lost if VT is of
kmclaughlin updated this revision to Diff 257349.
kmclaughlin marked 4 inline comments as done.
kmclaughlin edited the summary of this revision.
kmclaughlin added a comment.
Simplified performLD1RQCombine method & added negative tests where the
immediate is out of range.
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kmclaughlin marked 2 inline comments as done.
kmclaughlin added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11592
+static SDValue performLD1RQCombine(SDNode *N, SelectionDAG ) {
+ SDLoc DL(N);
andwar wrote:
> [Nit] I think
andwar added a comment.
Btw, could you also add some negative tests? (e.g. out-of-range immediate)
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andwar added a comment.
Cheers for working on this @kmclaughlin !
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1407
case AArch64ISD::PTRUE: return "AArch64ISD::PTRUE";
+ case AArch64ISD::LD1RQ: return "AArch64ISD::LD1RQ";
case
kmclaughlin created this revision.
kmclaughlin added reviewers: andwar, sdesmalen, efriedma, cameron.mcinally,
dancgr.
Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya,
kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
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