This revision was automatically updated to reflect the committed changes.
Closed by commit rG0df40d6ef8b8: [AArch64][SVE] Add addressing mode for
contiguous loads stores (authored by kmclaughlin).
Changed prior to commit:
https://reviews.llvm.org/D78509?vs=258954=258965#toc
Repository:
rG
kmclaughlin added a comment.
Thanks for taking a look at this, @fpetrogalli!
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78509/new/
https://reviews.llvm.org/D78509
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
kmclaughlin updated this revision to Diff 258954.
kmclaughlin marked 5 inline comments as done.
kmclaughlin added a comment.
- Renamed ld1nf multiclass to ldnf1
- Split out existing reg+imm tests into their own files
- Renamed 'offset' to 'index' in reg+reg tests
CHANGES SINCE LAST ACTION
fpetrogalli accepted this revision.
fpetrogalli added a comment.
This revision is now accepted and ready to land.
I think I made a mess with the Actions for this review! I mean to accept it,
not to enforce the nit comments!
Francesco
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST
fpetrogalli requested changes to this revision.
fpetrogalli added a comment.
This revision now requires changes to proceed.
Hi @kmclaughlin , thank you for working on this!
The patch LGTM, but please consider renaming the multiclass for the non
faulting loads like I suggested. The rest of the
kmclaughlin created this revision.
kmclaughlin added reviewers: sdesmalen, fpetrogalli, efriedma.
Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya,
kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
This patch adds the register + register
