[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14166 + + SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr(), DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl)}; + nit: indentation. Comment at:

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 279362. Conanap marked 5 inline comments as done. Conanap added a comment. Return signature fix, added recognition for ISD:EXTLOAD, some code clean up. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

NeHuang added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156 + + // This transformation is only valid if the we are loading either a byte, + // halfword, word, or doubleword. nit: if we are loading either a byte

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

stefanp added a comment. The title of the patch mentions both zero extend and sign extend. However, it seems that we only have instructions for the zero extend case. Is that right? I see both types of tests in: `test/CodeGen/builtins-ppc-p10vector.c` But I only see codegen tests for the zreo

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 277952. Conanap added a comment. Restored accidentally deleted pattern, removed duplicate tests, moved new tests to another pre-existing file instead. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. I think the patterns for the load instructions may have accidentally been deleted. Please add them back to the patch. Thank you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 277418. Conanap added a comment. Removed duplicate test code found in the instructions and MC Test implementation of VSX Vector store and load with sign extend or zero extend; re-added a test file that was omitted in the last diff update. Repository: rG

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 277415. Conanap marked 2 inline comments as done. Conanap added a comment. Removed unecessary comments and unintended changes. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files:

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. Please update this patch to remove the instruction defs and MC tests. Also, you can update the patch to put your backend llc tests in the file I've introduced in: https://reviews.llvm.org/D82467 Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:14

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 276785. Conanap marked 3 inline comments as done. Conanap added a comment. Now depends on D83364 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap added a comment. Also removed unnecessary brackets and comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13791 + // Ensure that the load from the narrow width is being zero extended to i128. + if ((!ValidLDType) || (LD->getValueType(0) != MVT::i128) || + (LD->getExtensionType() !=

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap marked 2 inline comments as done. Conanap added a comment. Addressed Lei's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 275423. Conanap marked 3 inline comments as done. Conanap added a comment. Moved some code to the top of the file as per Lei's request Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap marked an inline comment as done. Conanap added a comment. fixed a missing comma and ensure that it compiles Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 275159. Conanap added a comment. Fixed a missing comma; ensured it builds. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files: clang/lib/Headers/altivec.h

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:487 +/// Allows utilization of the Load VSX Vector Rightmost Instructions. +LXVRZX + missing `,`? Comment at:

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 275124. Conanap marked 4 inline comments as done. Conanap added a comment. Fixed some formatting stuff. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files:

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap added a comment. Addressed Lei's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap marked 2 inline comments as done. Conanap added a comment. Addressed Anil's comments with regards to the test cases Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:56 + +; CHECK: lxvrdx +; Function Attrs: norecurse nounwind readonly anil9

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added a comment. Please move encoding tests to `ppc64-encoding-ISA31.[txt|s]`. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13792 + if ((LD->getValueType(0) != MVT::i128) || + (LD->getExtensionType() != ISD::ZEXTLOAD) || (!ValidLDType)) +return

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 274097. Conanap marked an inline comment as done. Conanap added a comment. Reordered some declarations in test cases and removed unecessary extra CHECKs. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

anil9 added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:17 +unsigned int uia, *uiap; +signed int *ia; +signed short *sia; nit: It seems that most pull requests follow an ordering like first signed declaration and then unsigned,

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 273421. Conanap marked 9 inline comments as done. Conanap added a comment. Fixed return signature for the open coded functions in altivec.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 273393. Conanap added a comment. Addressed Amy's comments regarding documentation of the changes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files:

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk requested changes to this revision. amyk added a comment. This revision now requires changes to proceed. I have a few comments from the last time we looked at this together. Just also FYI that the backend tests will be apart of the `p10-vsx-builtins.ll` file introduced in

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap created this revision. Conanap added reviewers: power-llvm-team, PowerPC, nemanjai, saghir, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Implemented following functions for Load VSX Vector Sign extend nad zero extend instructions: vector signed __int128 vec_xl_sext (signed