[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-04-09 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai updated this revision to Diff 336320. HsiangKai added a comment. Put element types in the macro and use them to create RecordType directly. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97264/new/ https://reviews.llvm.org/D97264 Files:

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-04-08 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added a comment. In D97264#2663082 , @rogfer01 wrote: > I was under the impression we didn't want to use class-member access syntax > for vector tuples (see > https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) > so

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-04-01 Thread Roger Ferrer Ibanez via Phabricator via cfe-commits
rogfer01 added inline comments. Comment at: clang/lib/AST/ASTContext.cpp:1486 + BuiltinType::Kind K, unsigned NF) { + auto TypeIter = llvm::find_if(Types, [](Type *Ty) { + if (Ty->isBuiltinType()) {

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-04-01 Thread Roger Ferrer Ibanez via Phabricator via cfe-commits
rogfer01 added a comment. I was under the impression we didn't want to use class-member access syntax for vector tuples (see https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) so we don't need a record type, do we? Perhaps it is possible to model them like opaque

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-03-30 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai updated this revision to Diff 334150. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97264/new/ https://reviews.llvm.org/D97264 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/Builtins.def

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai updated this revision to Diff 325987. HsiangKai added a comment. Add comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97264/new/ https://reviews.llvm.org/D97264 Files: clang/include/clang/AST/ASTContext.h

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" HsiangKai wrote: >

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" craig.topper wrote: >

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai marked 3 inline comments as done. HsiangKai added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10672 + if (Ty->isRecordType() && !Ty->getAsRecordDecl()->field_empty() && + Ty->getAsRecordDecl()->field_begin()->getType()->isSizelessType())

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai updated this revision to Diff 325957. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97264/new/ https://reviews.llvm.org/D97264 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/Builtins.def

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" craig.topper wrote: > Why

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" Why is this QualType and

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10672 + if (Ty->isRecordType() && !Ty->getAsRecordDecl()->field_empty() && + Ty->getAsRecordDecl()->field_begin()->getType()->isSizelessType()) Are we able to test this yet?

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:59 #ifndef RVV_VECTOR_TYPE_FLOAT #define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

2021-02-23 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai created this revision. HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01. Herald added subscribers: StephenFan, vkmr, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones,