[clang] [RISCV] Support floating point VCIX (PR #67094)

4vtomat wrote: > The target is support LLVM IR part only, we would like to prevent expose that > on the C intrinsic level if possible, because that's intentionally to expose > vector with unsigned integer only. Sure~ https://github.com/llvm/llvm-project/pull/67094

[clang] [RISCV] Support floating point VCIX (PR #67094)

@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0 ; CHECK-NEXT:ret entry: - tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, %vd, %vs2, half %fs1, iXLen %vl) + tail call void

[clang] [RISCV] Support floating point VCIX (PR #67094)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/67094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support floating point VCIX (PR #67094)

https://github.com/kito-cheng commented: The target is support LLVM IR part only, we would like to prevent expose that on the C intrinsic level if possible, because that's intentionally to expose vector with unsigned integer only. https://github.com/llvm/llvm-project/pull/67094

[clang] [RISCV] Support floating point VCIX (PR #67094)

@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0 ; CHECK-NEXT:ret entry: - tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, %vd, %vs2, half %fs1, iXLen %vl) + tail call void