jrtc27 wrote:
What purpose does this serve if swiftcall doesn't work? Given the tests only
test that you can produce IR from Clang, that suggests that it doesn't actually
do anything useful?.. (And if it does do something useful, *that* should be
being tested)
https://github.com/kubamracek closed
https://github.com/llvm/llvm-project/pull/82152
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/82152
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/kubamracek updated
https://github.com/llvm/llvm-project/pull/82152
>From 97e2f9c1c635310da19f89f44a8085c16c3feb94 Mon Sep 17 00:00:00 2001
From: Kuba Mracek
Date: Sat, 17 Feb 2024 22:26:21 -0800
Subject: [PATCH] [clang] Define SwiftInfo for RISCVTargetCodeGenInfo
---
asb wrote:
Yes, please add a trivial test if at all possible.
https://github.com/llvm/llvm-project/pull/82152
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
jroelofs wrote:
> Can this be tested? I don't know what the affects are.
Might be as simple as adding another `RUN:` line to
`clang/test/CodeGenCXX/arm-swiftcall.{c,cpp}` with a riscv triple.
https://github.com/llvm/llvm-project/pull/82152
___
wangpc-pp wrote:
Can this be tested? I don't know what the affects are.
https://github.com/llvm/llvm-project/pull/82152
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/francisvm approved this pull request.
https://github.com/llvm/llvm-project/pull/82152
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-clang-codegen
Author: Kuba (Brecka) Mracek (kubamracek)
Changes
For Embedded Swift, let's unblock building for RISC-V boards (e.g. ESP32-C6).
This isn't trying to add full RISC-V support to
https://github.com/kubamracek created
https://github.com/llvm/llvm-project/pull/82152
For Embedded Swift, let's unblock building for RISC-V boards (e.g. ESP32-C6).
This isn't trying to add full RISC-V support to Swift / Embedded Swift, it's
just fixing the immediate blocker (not having
10 matches
Mail list logo
