https://github.com/owenca closed https://github.com/llvm/llvm-project/pull/70768
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@@ -3117,9 +3117,16 @@ void UnwrappedLineParser::parseForOrWhileLoop(bool
HasParens) {
FormatTok->setFinalizedType(TT_ConditionLParen);
parseParens();
}
- // Event control.
- if (Style.isVerilog())
+
+ if (Style.isVerilog()) {
+// Event control.
https://github.com/owenca edited https://github.com/llvm/llvm-project/pull/70768
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https://github.com/HazardyKnusperkeks approved this pull request.
https://github.com/llvm/llvm-project/pull/70768
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@@ -3117,9 +3117,16 @@ void UnwrappedLineParser::parseForOrWhileLoop(bool
HasParens) {
FormatTok->setFinalizedType(TT_ConditionLParen);
parseParens();
}
- // Event control.
- if (Style.isVerilog())
+
+ if (Style.isVerilog()) {
+// Event control.
https://github.com/owenca updated
https://github.com/llvm/llvm-project/pull/70768
>From 7e6030532f99b4128807631e993609ce40171043 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Mon, 30 Oct 2023 22:50:27 -0700
Subject: [PATCH 1/2] [clang-format] Treat empty for/while loops as short loops
A
@@ -3117,9 +3117,16 @@ void UnwrappedLineParser::parseForOrWhileLoop(bool
HasParens) {
FormatTok->setFinalizedType(TT_ConditionLParen);
parseParens();
}
- // Event control.
- if (Style.isVerilog())
+
+ if (Style.isVerilog()) {
+// Event control.
@@ -3117,9 +3117,16 @@ void UnwrappedLineParser::parseForOrWhileLoop(bool
HasParens) {
FormatTok->setFinalizedType(TT_ConditionLParen);
parseParens();
}
- // Event control.
- if (Style.isVerilog())
+
+ if (Style.isVerilog()) {
+// Event control.
https://github.com/owenca edited https://github.com/llvm/llvm-project/pull/70768
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@@ -3117,9 +3117,16 @@ void UnwrappedLineParser::parseForOrWhileLoop(bool
HasParens) {
FormatTok->setFinalizedType(TT_ConditionLParen);
parseParens();
}
- // Event control.
- if (Style.isVerilog())
+
+ if (Style.isVerilog()) {
+// Event control.
@@ -3117,9 +3117,16 @@ void UnwrappedLineParser::parseForOrWhileLoop(bool
HasParens) {
FormatTok->setFinalizedType(TT_ConditionLParen);
parseParens();
}
- // Event control.
- if (Style.isVerilog())
+
+ if (Style.isVerilog()) {
+// Event control.
https://github.com/HazardyKnusperkeks edited
https://github.com/llvm/llvm-project/pull/70768
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https://github.com/HazardyKnusperkeks commented:
The code is okay, but I do not share the intention.
https://github.com/llvm/llvm-project/pull/70768
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llvmbot wrote:
@llvm/pr-subscribers-clang-format
Author: Owen Pan (owenca)
Changes
A for/while loop with only a semicolon as its body should be treated as an
empty loop.
Fixes #61708.
---
Full diff: https://github.com/llvm/llvm-project/pull/70768.diff
2 Files Affected:
- (modified)
https://github.com/owenca created
https://github.com/llvm/llvm-project/pull/70768
A for/while loop with only a semicolon as its body should be treated as an
empty loop.
Fixes #61708.
>From 7e6030532f99b4128807631e993609ce40171043 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Mon, 30 Oct
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