https://github.com/Lukacma closed
https://github.com/llvm/llvm-project/pull/88251
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https://github.com/Lukacma updated
https://github.com/llvm/llvm-project/pull/88251
>From fe692284cd248e372302671e094eb9950edb5ee5 Mon Sep 17 00:00:00 2001
From: Marian Lukac
Date: Wed, 10 Apr 2024 10:20:03 +
Subject: [PATCH 1/3] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP
---
https://github.com/Lukacma updated
https://github.com/llvm/llvm-project/pull/88251
>From fe692284cd248e372302671e094eb9950edb5ee5 Mon Sep 17 00:00:00 2001
From: Marian Lukac
Date: Wed, 10 Apr 2024 10:20:03 +
Subject: [PATCH 1/3] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP
---
https://github.com/Lukacma updated
https://github.com/llvm/llvm-project/pull/88251
>From fe692284cd248e372302671e094eb9950edb5ee5 Mon Sep 17 00:00:00 2001
From: Marian Lukac
Date: Wed, 10 Apr 2024 10:20:03 +
Subject: [PATCH 1/3] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP
---
https://github.com/Lukacma updated
https://github.com/llvm/llvm-project/pull/88251
>From fe692284cd248e372302671e094eb9950edb5ee5 Mon Sep 17 00:00:00 2001
From: Marian Lukac
Date: Wed, 10 Apr 2024 10:20:03 +
Subject: [PATCH 1/3] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP
---
https://github.com/CarolineConcatto approved this pull request.
https://github.com/llvm/llvm-project/pull/88251
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@@ -2148,6 +2148,11 @@ let TargetGuard = "sme2" in {
def SVSCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "csil",
MergeNone, "aarch64_sve_sclamp_single_x4", [IsStreaming], []>;
def SVUCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "UcUsUiUl",
https://github.com/Lukacma updated
https://github.com/llvm/llvm-project/pull/88251
>From fe692284cd248e372302671e094eb9950edb5ee5 Mon Sep 17 00:00:00 2001
From: Marian Lukac
Date: Wed, 10 Apr 2024 10:20:03 +
Subject: [PATCH 1/3] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP
---
@@ -2148,6 +2148,11 @@ let TargetGuard = "sme2" in {
def SVSCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "csil",
MergeNone, "aarch64_sve_sclamp_single_x4", [IsStreaming], []>;
def SVUCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "UcUsUiUl",
@@ -2148,6 +2148,11 @@ let TargetGuard = "sme2" in {
def SVSCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "csil",
MergeNone, "aarch64_sve_sclamp_single_x4", [IsStreaming], []>;
def SVUCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "UcUsUiUl",
https://github.com/Lukacma updated
https://github.com/llvm/llvm-project/pull/88251
>From fe692284cd248e372302671e094eb9950edb5ee5 Mon Sep 17 00:00:00 2001
From: Marian Lukac
Date: Wed, 10 Apr 2024 10:20:03 +
Subject: [PATCH 1/2] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP
---
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-clang
Author: None (Lukacma)
Changes
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
```
svbfloat16x2_t svclamp[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zn,
https://github.com/Lukacma created
https://github.com/llvm/llvm-project/pull/88251
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
```
svbfloat16x2_t svclamp[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zn,
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