https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/75596
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@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
momchil-velikov wrote:
Rebased the clear the test run.
https://github.com/llvm/llvm-project/pull/75596
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75596
>From 04a03eae3fcbdd57257ce3867615ec6be9d84e53 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75596
>From fc5c82e61efef3f1cd2f6606b12c358637a687f5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of
@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75596
According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en all of the
affected instruction encodings now require
(FEAT_SVE2 or FEAT_SME2) and
