uweigand wrote:
Fixed merge conflicts, updated as described above, and fixed support for i128
parameters in the z/OS XPLINK ABI.
https://github.com/llvm/llvm-project/pull/74625
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uweigand wrote:
> I have looked through the changes and made some comments inline.
Thanks for the review!
> Commenting:
Fixed, thanks!
> I happened to notice some cases with room for improvement:
Good catch. I've not addressed these right now, this can be done as a
follow-up. (The memory
@@ -1516,48 +1536,206 @@ let Predicates = [FeatureVector] in {
}
}
+//===--===//
+// Support for 128-bit integer values in vector registers
@@ -6481,6 +6737,71 @@ SDValue SystemZTargetLowering::combineLOAD(
SDNode *N, DAGCombinerInfo ) const {
SelectionDAG = DCI.DAG;
EVT LdVT = N->getValueType(0);
+ SDLoc DL(N);
+
+ // Replace an i128 load that is used solely to move its value into GPRs
+ // by
@@ -2918,16 +3049,17 @@ static Comparison getCmp(SelectionDAG , SDValue
CmpOp0, SDValue CmpOp1,
bool IsSignaling = false) {
if (CmpOp1.getOpcode() == ISD::Constant) {
assert(!Chain);
-uint64_t Constant = cast(CmpOp1)->getZExtValue();
@@ -2772,6 +2837,27 @@ static unsigned getTestUnderMaskCond(unsigned BitSize,
unsigned CCMask,
// Update the arguments with the TM version if so.
static void adjustForTestUnderMask(SelectionDAG , const SDLoc ,
Comparison ) {
+ // Use VECTOR
@@ -1466,7 +1509,15 @@ static SDValue convertValVTToLocVT(SelectionDAG ,
const SDLoc ,
static SDValue lowerI128ToGR128(SelectionDAG , SDValue In) {
SDLoc DL(In);
SDValue Lo, Hi;
- std::tie(Lo, Hi) = DAG.SplitScalar(In, DL, MVT::i64, MVT::i64);
+ if
@@ -1183,6 +1187,35 @@ void SystemZDAGToDAGISel::loadVectorConstant(
SelectCode(Op.getNode());
}
+SDNode *SystemZDAGToDAGISel::loadPoolVectorConstant(APInt Val, EVT VT, SDLoc
DL) {
+ SDNode *ResNode;
+ assert (VT.getSizeInBits() == 128);
+
+ SDValue CP =
JonPsson1 wrote:
I have looked through the changes and made some comments inline.
I built this with expensive checks enabled with all checks passing, and SPEC
built successfully.
Commenting:
```
@@ -293,7 +293,7 @@ SystemZTargetLowering::SystemZTargetLowering(const
TargetMachine ,
@@ -6481,6 +6737,71 @@ SDValue SystemZTargetLowering::combineLOAD(
SDNode *N, DAGCombinerInfo ) const {
SelectionDAG = DCI.DAG;
EVT LdVT = N->getValueType(0);
+ SDLoc DL(N);
+
+ // Replace an i128 load that is used solely to move its value into GPRs
+ // by
@@ -2918,16 +3049,17 @@ static Comparison getCmp(SelectionDAG , SDValue
CmpOp0, SDValue CmpOp1,
bool IsSignaling = false) {
if (CmpOp1.getOpcode() == ISD::Constant) {
assert(!Chain);
-uint64_t Constant = cast(CmpOp1)->getZExtValue();
@@ -2772,6 +2837,27 @@ static unsigned getTestUnderMaskCond(unsigned BitSize,
unsigned CCMask,
// Update the arguments with the TM version if so.
static void adjustForTestUnderMask(SelectionDAG , const SDLoc ,
Comparison ) {
+ // Use VECTOR
@@ -1466,7 +1509,15 @@ static SDValue convertValVTToLocVT(SelectionDAG ,
const SDLoc ,
static SDValue lowerI128ToGR128(SelectionDAG , SDValue In) {
SDLoc DL(In);
SDValue Lo, Hi;
- std::tie(Lo, Hi) = DAG.SplitScalar(In, DL, MVT::i64, MVT::i64);
+ if
@@ -1183,6 +1187,35 @@ void SystemZDAGToDAGISel::loadVectorConstant(
SelectCode(Op.getNode());
}
+SDNode *SystemZDAGToDAGISel::loadPoolVectorConstant(APInt Val, EVT VT, SDLoc
DL) {
+ SDNode *ResNode;
+ assert (VT.getSizeInBits() == 128);
+
+ SDValue CP =
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 384f916ea899ea6ac9af4a3fb9d0a5b03937acfe
a3e9b3a923df055c5ebe9ec045ed99c909a16dd2 --
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