Author: Stephen Long Date: 2022-05-23T07:01:11-07:00 New Revision: 3e0be5610ff0e9d5bb15f2872bac8cd17bfcc34a
URL: https://github.com/llvm/llvm-project/commit/3e0be5610ff0e9d5bb15f2872bac8cd17bfcc34a DIFF: https://github.com/llvm/llvm-project/commit/3e0be5610ff0e9d5bb15f2872bac8cd17bfcc34a.diff LOG: [MSVC, ARM64] Add __writex18 intrinsics https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-170 void __writex18byte(unsigned long, unsigned char) void __writex18word(unsigned long, unsigned short) void __writex18dword(unsigned long, unsigned long) void __writex18qword(unsigned long, unsigned __int64) Given the lack of documentation of the intrinsics, we chose to align the offset with just `CharUnits::One()` when calling `IRBuilderBase::CreateAlignedStore()`. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D126023 Added: Modified: clang/include/clang/Basic/BuiltinsAArch64.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/intrin.h clang/test/CodeGen/arm64-microsoft-intrinsics.c Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def index cebd1c07fbcc..a04b48dd128e 100644 --- a/clang/include/clang/Basic/BuiltinsAArch64.def +++ b/clang/include/clang/Basic/BuiltinsAArch64.def @@ -251,6 +251,11 @@ TARGET_HEADER_BUILTIN(__umulh, "ULLiULLiULLi", "nh", "intrin.h", ALL_MS_LANGUAGE TARGET_HEADER_BUILTIN(__break, "vi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(__writex18byte, "vULiUc", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(__writex18word, "vULiUs", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(__writex18dword, "vULiULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(__writex18qword, "vULiULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") + #undef BUILTIN #undef LANGBUILTIN #undef TARGET_HEADER_BUILTIN diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 2ee734550dc1..6168ba938db4 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -9952,6 +9952,31 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, return HigherBits; } + if (BuiltinID == AArch64::BI__writex18byte || + BuiltinID == AArch64::BI__writex18word || + BuiltinID == AArch64::BI__writex18dword || + BuiltinID == AArch64::BI__writex18qword) { + llvm::Type *IntTy = ConvertType(E->getArg(1)->getType()); + + // Read x18 as i8* + LLVMContext &Context = CGM.getLLVMContext(); + llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "x18")}; + llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops); + llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName); + llvm::Function *F = + CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty}); + llvm::Value *X18 = Builder.CreateCall(F, Metadata); + X18 = Builder.CreateIntToPtr(X18, llvm::PointerType::get(Int8Ty, 0)); + + // Store val at x18 + offset + Value *Offset = Builder.CreateZExt(EmitScalarExpr(E->getArg(0)), Int64Ty); + Value *Ptr = Builder.CreateGEP(Int8Ty, X18, Offset); + Ptr = Builder.CreatePointerCast(Ptr, llvm::PointerType::get(IntTy, 0)); + Value *Val = EmitScalarExpr(E->getArg(1)); + StoreInst *Store = Builder.CreateAlignedStore(Val, Ptr, CharUnits::One()); + return Store; + } + // Handle MSVC intrinsics before argument evaluation to prevent double // evaluation. if (Optional<MSVCIntrin> MsvcIntId = translateAarch64ToMsvcIntrin(BuiltinID)) diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h index 07fcae36020d..dbc5159853dd 100644 --- a/clang/lib/Headers/intrin.h +++ b/clang/lib/Headers/intrin.h @@ -562,6 +562,11 @@ __int64 __mulh(__int64 __a, __int64 __b); unsigned __int64 __umulh(unsigned __int64 __a, unsigned __int64 __b); void __break(int); + +void __writex18byte(unsigned long offset, unsigned char data); +void __writex18word(unsigned long offset, unsigned short data); +void __writex18dword(unsigned long offset, unsigned long data); +void __writex18qword(unsigned long offset, unsigned __int64 data); #endif /*----------------------------------------------------------------------------*\ diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c index ecf271bae580..a9b1d444553f 100644 --- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c +++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c @@ -119,5 +119,73 @@ unsigned __int64 check__getReg(void) { // CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]]) // CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]]) + +void check__writex18byte(unsigned long offset, unsigned char data) { + __writex18byte(offset, data); +} + +// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i8, align 1 +// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 +// CHECK-MSVC: store i8 %data, i8* %[[DATA_ADDR]], align 1 +// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) +// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8* +// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 +// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] +// CHECK-MSVC: %[[DATA:.*]] = load i8, i8* %[[DATA_ADDR]], align 1 +// CHECK-MSVC: store i8 %[[DATA]], i8* %[[PTR]], align 1 + +void check__writex18word(unsigned long offset, unsigned short data) { + __writex18word(offset, data); +} + +// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i16, align 2 +// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 +// CHECK-MSVC: store i16 %data, i16* %[[DATA_ADDR]], align 2 +// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) +// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8* +// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 +// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] +// CHECK-MSVC: %[[BITCAST_PTR:.*]] = bitcast i8* %[[PTR]] to i16* +// CHECK-MSVC: %[[DATA:.*]] = load i16, i16* %[[DATA_ADDR]], align 2 +// CHECK-MSVC: store i16 %[[DATA]], i16* %[[BITCAST_PTR]], align 1 + +void check__writex18dword(unsigned long offset, unsigned long data) { + __writex18dword(offset, data); +} + +// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i32, align 4 +// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 +// CHECK-MSVC: store i32 %data, i32* %[[DATA_ADDR]], align 4 +// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) +// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8* +// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 +// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] +// CHECK-MSVC: %[[BITCAST_PTR:.*]] = bitcast i8* %[[PTR]] to i32* +// CHECK-MSVC: %[[DATA:.*]] = load i32, i32* %[[DATA_ADDR]], align 4 +// CHECK-MSVC: store i32 %[[DATA]], i32* %[[BITCAST_PTR]], align 1 + +void check__writex18qword(unsigned long offset, unsigned __int64 data) { + __writex18qword(offset, data); +} + +// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i64, align 8 +// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 +// CHECK-MSVC: store i64 %data, i64* %[[DATA_ADDR]], align 8 +// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) +// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8* +// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4 +// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 +// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] +// CHECK-MSVC: %[[BITCAST_PTR:.*]] = bitcast i8* %[[PTR]] to i64* +// CHECK-MSVC: %[[DATA:.*]] = load i64, i64* %[[DATA_ADDR]], align 8 +// CHECK-MSVC: store i64 %[[DATA]], i64* %[[BITCAST_PTR]], align 1 + // CHECK-MSVC: ![[MD2]] = !{!"x18"} // CHECK-MSVC: ![[MD3]] = !{!"sp"} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
