Author: Kazu Hirata Date: 2023-02-19T23:56:52-08:00 New Revision: a28b252d852c31fb7228e095a213347e6926bb0f
URL: https://github.com/llvm/llvm-project/commit/a28b252d852c31fb7228e095a213347e6926bb0f DIFF: https://github.com/llvm/llvm-project/commit/a28b252d852c31fb7228e095a213347e6926bb0f.diff LOG: Use APInt::getSignificantBits instead of APInt::getMinSignedBits (NFC) Note that getMinSignedBits has been soft-deprecated in favor of getSignificantBits. Added: Modified: clang-tools-extra/clangd/Hover.cpp clang/lib/AST/ExprConstant.cpp clang/lib/Sema/SemaChecking.cpp clang/lib/Sema/SemaDecl.cpp clang/lib/Sema/SemaExpr.cpp clang/lib/Sema/SemaTemplate.cpp clang/lib/StaticAnalyzer/Core/APSIntType.cpp llvm/include/llvm/Analysis/TargetTransformInfoImpl.h llvm/include/llvm/CodeGen/SelectionDAG.h llvm/lib/Analysis/ConstantFolding.cpp llvm/lib/CodeGen/CodeGenPrepare.cpp llvm/lib/CodeGen/MIRParser/MIParser.cpp llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/IR/ConstantFold.cpp llvm/lib/IR/ConstantRange.cpp llvm/lib/IR/Value.cpp llvm/lib/Support/APSInt.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp llvm/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp llvm/lib/Transforms/Scalar/Float2Int.cpp llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp llvm/lib/Transforms/Utils/BypassSlowDivision.cpp llvm/lib/Transforms/Utils/SimplifyCFG.cpp llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp polly/lib/Support/GICHelper.cpp Removed: ################################################################################ diff --git a/clang-tools-extra/clangd/Hover.cpp b/clang-tools-extra/clangd/Hover.cpp index 1a51614bb9d45..c5436141adbf7 100644 --- a/clang-tools-extra/clangd/Hover.cpp +++ b/clang-tools-extra/clangd/Hover.cpp @@ -396,7 +396,7 @@ void fillFunctionTypeAndParams(HoverInfo &HI, const Decl *D, // -2^32 => 0xfffffffeffffffff static llvm::FormattedNumber printHex(const llvm::APSInt &V) { uint64_t Bits = V.getExtValue(); - if (V.isNegative() && V.getMinSignedBits() <= 32) + if (V.isNegative() && V.getSignificantBits() <= 32) return llvm::format_hex(uint32_t(Bits), 0); return llvm::format_hex(Bits, 0); } @@ -430,7 +430,7 @@ std::optional<std::string> printExprValue(const Expr *E, // Show enums symbolically, not numerically like APValue::printPretty(). if (T->isEnumeralType() && Constant.Val.isInt() && - Constant.Val.getInt().getMinSignedBits() <= 64) { + Constant.Val.getInt().getSignificantBits() <= 64) { // Compare to int64_t to avoid bit-width match requirements. int64_t Val = Constant.Val.getInt().getExtValue(); for (const EnumConstantDecl *ECD : @@ -442,7 +442,7 @@ std::optional<std::string> printExprValue(const Expr *E, } // Show hex value of integers if they're at least 10 (or negative!) if (T->isIntegralOrEnumerationType() && Constant.Val.isInt() && - Constant.Val.getInt().getMinSignedBits() <= 64 && + Constant.Val.getInt().getSignificantBits() <= 64 && Constant.Val.getInt().uge(10)) return llvm::formatv("{0} ({1})", Constant.Val.getAsString(Ctx, T), printHex(Constant.Val.getInt())) diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 9d43ad1cfc528..9e67f862ae634 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -12008,7 +12008,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, if (!EvaluateInteger(E->getArg(0), Val, Info)) return false; - return Success(Val.getBitWidth() - Val.getMinSignedBits(), E); + return Success(Val.getBitWidth() - Val.getSignificantBits(), E); } case Builtin::BI__builtin_clz: diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 54f7d041a857a..9d5490a99310f 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -12456,7 +12456,7 @@ struct IntRange { static IntRange GetValueRange(ASTContext &C, llvm::APSInt &value, unsigned MaxWidth) { if (value.isSigned() && value.isNegative()) - return IntRange(value.getMinSignedBits(), false); + return IntRange(value.getSignificantBits(), false); if (value.getBitWidth() > MaxWidth) value = value.trunc(MaxWidth); @@ -13373,7 +13373,7 @@ static bool AnalyzeBitFieldAssignment(Sema &S, FieldDecl *Bitfield, Expr *Init, if (!Value.isSigned() || Value.isNegative()) if (UnaryOperator *UO = dyn_cast<UnaryOperator>(OriginalInit)) if (UO->getOpcode() == UO_Minus || UO->getOpcode() == UO_Not) - OriginalWidth = Value.getMinSignedBits(); + OriginalWidth = Value.getSignificantBits(); if (OriginalWidth <= FieldWidth) return false; diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index ba5b2f67beca6..09540e52892d1 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -19060,7 +19060,7 @@ static bool isRepresentableIntegerValue(ASTContext &Context, --BitWidth; return Value.getActiveBits() <= BitWidth; } - return Value.getMinSignedBits() <= BitWidth; + return Value.getSignificantBits() <= BitWidth; } // Given an integral type, return the next larger integral type @@ -19595,8 +19595,8 @@ void Sema::ActOnEnumBody(SourceLocation EnumLoc, SourceRange BraceRange, unsigned ActiveBits = InitVal.getActiveBits(); NumPositiveBits = std::max({NumPositiveBits, ActiveBits, 1u}); } else { - NumNegativeBits = std::max(NumNegativeBits, - (unsigned)InitVal.getMinSignedBits()); + NumNegativeBits = + std::max(NumNegativeBits, (unsigned)InitVal.getSignificantBits()); } } diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index ab34fd87b6775..12c02e531da3e 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -10502,7 +10502,7 @@ static bool canConvertIntToOtherIntTy(Sema &S, ExprResult *Int, // bits that the vector element type, reject it. llvm::APSInt Result = EVResult.Val.getInt(); unsigned NumBits = IntSigned - ? (Result.isNegative() ? Result.getMinSignedBits() + ? (Result.isNegative() ? Result.getSignificantBits() : Result.getActiveBits()) : Result.getActiveBits(); if (Order < 0 && S.Context.getIntWidth(OtherIntTy) < NumBits) @@ -11745,7 +11745,7 @@ static void DiagnoseBadShiftValues(Sema& S, ExprResult &LHS, ExprResult &RHS, } llvm::APInt ResultBits = - static_cast<llvm::APInt&>(Right) + Left.getMinSignedBits(); + static_cast<llvm::APInt &>(Right) + Left.getSignificantBits(); if (LeftBits.uge(ResultBits)) return; llvm::APSInt Result = Left.extend(ResultBits.getLimitedValue()); @@ -11768,9 +11768,9 @@ static void DiagnoseBadShiftValues(Sema& S, ExprResult &LHS, ExprResult &RHS, } S.Diag(Loc, diag::warn_shift_result_gt_typewidth) - << HexResult.str() << Result.getMinSignedBits() << LHSType - << Left.getBitWidth() << LHS.get()->getSourceRange() - << RHS.get()->getSourceRange(); + << HexResult.str() << Result.getSignificantBits() << LHSType + << Left.getBitWidth() << LHS.get()->getSourceRange() + << RHS.get()->getSourceRange(); } /// Return the resulting type when a vector is shifted diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 3a56c26f36407..8df8eadad3fef 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -7521,7 +7521,7 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param, else if (OldValue.isUnsigned()) RequiredBits = OldValue.getActiveBits() + 1; else - RequiredBits = OldValue.getMinSignedBits(); + RequiredBits = OldValue.getSignificantBits(); if (RequiredBits > AllowedBits) { Diag(Arg->getBeginLoc(), diag::warn_template_arg_too_large) << toString(OldValue, 10) << toString(Value, 10) << Param->getType() diff --git a/clang/lib/StaticAnalyzer/Core/APSIntType.cpp b/clang/lib/StaticAnalyzer/Core/APSIntType.cpp index a1de10c89ed91..1185cdaa044a5 100644 --- a/clang/lib/StaticAnalyzer/Core/APSIntType.cpp +++ b/clang/lib/StaticAnalyzer/Core/APSIntType.cpp @@ -23,7 +23,7 @@ APSIntType::testInRange(const llvm::APSInt &Value, unsigned MinBits; if (AllowSignConversions) { if (Value.isSigned() && !IsUnsigned) - MinBits = Value.getMinSignedBits(); + MinBits = Value.getSignificantBits(); else MinBits = Value.getActiveBits(); @@ -33,7 +33,7 @@ APSIntType::testInRange(const llvm::APSInt &Value, // Unsigned integers can be converted to unsigned integers of the same width // or signed integers with one more bit. if (Value.isSigned()) - MinBits = Value.getMinSignedBits() - IsUnsigned; + MinBits = Value.getSignificantBits() - IsUnsigned; else MinBits = Value.getActiveBits() + !IsUnsigned; } diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index cc57defb063de..9b19f3a506a05 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -887,7 +887,7 @@ class TargetTransformInfoImplBase { bool signedElement = IntElement->getValue().isNegative(); // Get the element min required size. unsigned ElementMinRequiredSize = - IntElement->getValue().getMinSignedBits() - 1; + IntElement->getValue().getSignificantBits() - 1; // In case one element is signed then all the vector is signed. isSigned |= signedElement; // Save the max required bit size between all the elements. @@ -902,7 +902,7 @@ class TargetTransformInfoImplBase { if (const auto *CI = dyn_cast<ConstantInt>(Val)) { isSigned = CI->getValue().isNegative(); - return CI->getValue().getMinSignedBits() - 1; + return CI->getValue().getSignificantBits() - 1; } if (const auto *Cast = dyn_cast<SExtInst>(Val)) { diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index aa1936c2757e7..1377feaa270d9 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1060,7 +1060,7 @@ class SelectionDAG { /// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm) { - assert(MulImm.getMinSignedBits() <= VT.getSizeInBits() && + assert(MulImm.getSignificantBits() <= VT.getSizeInBits() && "Immediate does not fit VT"); return getNode(ISD::VSCALE, DL, VT, getConstant(MulImm.sextOrTrunc(VT.getSizeInBits()), DL, VT)); diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp index 8fe0799128c2e..585a987c1049a 100644 --- a/llvm/lib/Analysis/ConstantFolding.cpp +++ b/llvm/lib/Analysis/ConstantFolding.cpp @@ -713,7 +713,7 @@ Constant *llvm::ConstantFoldLoadFromConst(Constant *C, Type *Ty, return Result; // Try hard to fold loads from bitcasted strange and non-type-safe things. - if (Offset.getMinSignedBits() <= 64) + if (Offset.getSignificantBits() <= 64) if (Constant *Result = FoldReinterpretLoadFromConst(C, Ty, Offset.getSExtValue(), DL)) return Result; diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index dd431cc6f4f5f..f028381793d3f 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -4698,7 +4698,7 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode, if (ConstantInt *CI = dyn_cast<ConstantInt>(AddrInst->getOperand(i))) { const APInt &CVal = CI->getValue(); - if (CVal.getMinSignedBits() <= 64) { + if (CVal.getSignificantBits() <= 64) { ConstantOffset += CVal.getSExtValue() * TypeSize; continue; } diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 525f49347fc46..d38e0ba365802 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -2414,7 +2414,7 @@ bool MIParser::parseMetadataOperand(MachineOperand &Dest) { bool MIParser::parseCFIOffset(int &Offset) { if (Token.isNot(MIToken::IntegerLiteral)) return error("expected a cfi offset"); - if (Token.integerValue().getMinSignedBits() > 32) + if (Token.integerValue().getSignificantBits() > 32) return error("expected a 32 bit integer (the cfi offset is too large)"); Offset = (int)Token.integerValue().getExtValue(); lex(); @@ -3001,7 +3001,7 @@ bool MIParser::parseOffset(int64_t &Offset) { lex(); if (Token.isNot(MIToken::IntegerLiteral)) return error("expected an integer literal after '" + Sign + "'"); - if (Token.integerValue().getMinSignedBits() > 64) + if (Token.integerValue().getSignificantBits() > 64) return error("expected 64-bit integer (too large)"); Offset = Token.integerValue().getExtValue(); if (IsNegative) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ba037998aaf1b..503b3c9e92e1d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5988,8 +5988,7 @@ SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) { // in a register. APInt ADDC = ADDI->getAPIntValue(); APInt SRLC = SRLI->getAPIntValue(); - if (ADDC.getMinSignedBits() <= 64 && - SRLC.ult(VT.getSizeInBits()) && + if (ADDC.getSignificantBits() <= 64 && SRLC.ult(VT.getSizeInBits()) && !TLI.isLegalAddImmediate(ADDC.getSExtValue())) { APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), SRLC.getZExtValue()); @@ -9816,7 +9815,7 @@ static SDValue combineShiftToMULH(SDNode *N, SelectionDAG &DAG, SDValue MulhRightOp; if (ConstantSDNode *Constant = isConstOrConstSplat(RightOp)) { unsigned ActiveBits = IsSignExt - ? Constant->getAPIntValue().getMinSignedBits() + ? Constant->getAPIntValue().getSignificantBits() : Constant->getAPIntValue().getActiveBits(); if (ActiveBits > NarrowVTSize) return SDValue(); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 6d972f402b6c2..4096a95cc45b0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -4333,7 +4333,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, } // Figure out how many bits we need to preserve this constant. - unsigned ReqdBits = Signed ? C1.getMinSignedBits() : C1.getActiveBits(); + unsigned ReqdBits = Signed ? C1.getSignificantBits() : C1.getActiveBits(); // Make sure we're not losing bits from the constant. if (MinBits > 0 && @@ -4507,7 +4507,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, // If the constant doesn't fit into the number of bits for the source of // the sign extension, it is impossible for both sides to be equal. - if (C1.getMinSignedBits() > ExtSrcTyBits) + if (C1.getSignificantBits() > ExtSrcTyBits) return DAG.getBoolConstant(Cond == ISD::SETNE, dl, VT, OpVT); assert(ExtDstTy == N0.getOperand(0).getValueType() && @@ -4863,7 +4863,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, } } - if (C1.getMinSignedBits() <= 64 && + if (C1.getSignificantBits() <= 64 && !isLegalICmpImmediate(C1.getSExtValue())) { EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); // (X & -256) == 256 -> (X >> 8) == 1 @@ -4900,7 +4900,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ShiftBits = C1.countr_zero(); } NewC.lshrInPlace(ShiftBits); - if (ShiftBits && NewC.getMinSignedBits() <= 64 && + if (ShiftBits && NewC.getSignificantBits() <= 64 && isLegalICmpImmediate(NewC.getSExtValue()) && !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0, diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp index 9a48f346419e1..553bc1e277e3b 100644 --- a/llvm/lib/IR/ConstantFold.cpp +++ b/llvm/lib/IR/ConstantFold.cpp @@ -1941,7 +1941,7 @@ static bool isInBoundsIndices(ArrayRef<IndexTy> Idxs) { static bool isIndexInRangeOfArrayType(uint64_t NumElements, const ConstantInt *CI) { // We cannot bounds check the index if it doesn't fit in an int64_t. - if (CI->getValue().getMinSignedBits() > 64) + if (CI->getValue().getSignificantBits() > 64) return false; // A negative index or an index past the end of our sequential type is diff --git a/llvm/lib/IR/ConstantRange.cpp b/llvm/lib/IR/ConstantRange.cpp index af70bfe1ec12a..74cc09705f883 100644 --- a/llvm/lib/IR/ConstantRange.cpp +++ b/llvm/lib/IR/ConstantRange.cpp @@ -481,8 +481,8 @@ unsigned ConstantRange::getMinSignedBits() const { if (isEmptySet()) return 0; - return std::max(getSignedMin().getMinSignedBits(), - getSignedMax().getMinSignedBits()); + return std::max(getSignedMin().getSignificantBits(), + getSignedMax().getSignificantBits()); } ConstantRange ConstantRange::subtract(const APInt &Val) const { diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp index 1a7ee3169da03..281594d735e0f 100644 --- a/llvm/lib/IR/Value.cpp +++ b/llvm/lib/IR/Value.cpp @@ -737,7 +737,7 @@ const Value *Value::stripAndAccumulateConstantOffsets( // Stop traversal if the pointer offset wouldn't fit in the bit-width // provided by the Offset argument. This can happen due to AddrSpaceCast // stripping. - if (GEPOffset.getMinSignedBits() > BitWidth) + if (GEPOffset.getSignificantBits() > BitWidth) return V; // External Analysis can return a result higher/lower than the value diff --git a/llvm/lib/Support/APSInt.cpp b/llvm/lib/Support/APSInt.cpp index b65b6824eaf8e..5a9f44f304a27 100644 --- a/llvm/lib/Support/APSInt.cpp +++ b/llvm/lib/Support/APSInt.cpp @@ -25,7 +25,7 @@ APSInt::APSInt(StringRef Str) { unsigned NumBits = ((Str.size() * 64) / 19) + 2; APInt Tmp(NumBits, Str, /*radix=*/10); if (Str[0] == '-') { - unsigned MinBits = Tmp.getMinSignedBits(); + unsigned MinBits = Tmp.getSignificantBits(); if (MinBits < NumBits) Tmp = Tmp.trunc(std::max<unsigned>(1, MinBits)); *this = APSInt(Tmp, /*isUnsigned=*/false); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ee163caaf53c1..cbe180c597cb6 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -10749,13 +10749,13 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift( // We can materialise `c1 << c2` into an add immediate, so it's "free", // and the combine should happen, to potentially allow further combines // later. - if (ShiftedC1Int.getMinSignedBits() <= 64 && + if (ShiftedC1Int.getSignificantBits() <= 64 && isLegalAddImmediate(ShiftedC1Int.getSExtValue())) return true; // We can materialise `c1` in an add immediate, so it's "free", and the // combine should be prevented. - if (C1Int.getMinSignedBits() <= 64 && + if (C1Int.getSignificantBits() <= 64 && isLegalAddImmediate(C1Int.getSExtValue())) return false; @@ -10845,7 +10845,7 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant( return false; // What is the fewest number of bits we need to represent the negative number. - unsigned MinSignedBits = ExpandedMask.getMinSignedBits(); + unsigned MinSignedBits = ExpandedMask.getSignificantBits(); // Try to make a 12 bit negative immediate. If that fails try to make a 32 // bit negative immediate unless the shrunk immediate already fits in 32 bits. diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index fcc88d6d4682c..130cc218f3047 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -164,7 +164,7 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, // Check immediate is the correct argument... if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) { // ... and fits into the 12-bit immediate. - if (Imm.getMinSignedBits() <= 64 && + if (Imm.getSignificantBits() <= 64 && getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { return TTI::TCC_Free; } diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 250edf64cb6c5..1e9e2917a3aa6 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -1391,7 +1391,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) { auto OperandV = OperandC->getAPIntValue(); if (NegateOperand) OperandV = -OperandV; - if (OperandV.getMinSignedBits() > 8) + if (OperandV.getSignificantBits() > 8) return false; Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT); diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index f47cc27124517..4c6e51b796556 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -4468,8 +4468,8 @@ bool X86DAGToDAGISel::shrinkAndImmediate(SDNode *And) { // If a negative constant would not allow a smaller encoding, there's no need // to continue. Only change the constant when we know it's a win. - unsigned MinWidth = NegMaskVal.getMinSignedBits(); - if (MinWidth > 32 || (MinWidth > 8 && MaskVal.getMinSignedBits() <= 32)) + unsigned MinWidth = NegMaskVal.getSignificantBits(); + if (MinWidth > 32 || (MinWidth > 8 && MaskVal.getSignificantBits() <= 32)) return false; // Extend masks if we truncated above. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 33db66c1bba94..03736ac0234d0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -48062,8 +48062,8 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG, } APInt NewMaskVal = MaskVal.lshr(ShiftC->getAPIntValue()); - unsigned OldMaskSize = MaskVal.getMinSignedBits(); - unsigned NewMaskSize = NewMaskVal.getMinSignedBits(); + unsigned OldMaskSize = MaskVal.getSignificantBits(); + unsigned NewMaskSize = NewMaskVal.getSignificantBits(); if ((OldMaskSize > 8 && NewMaskSize <= 8) || (OldMaskSize > 32 && NewMaskSize <= 32)) { // srl (and X, AndC), ShiftC --> and (srl X, ShiftC), (AndC >> ShiftC) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index c95bde43be093..e0d7bd4d84c4a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1359,7 +1359,8 @@ Instruction *InstCombinerImpl::visitSDiv(BinaryOperator &I) { // (sext X) sdiv C --> sext (X sdiv C) Value *Op0Src; if (match(Op0, m_OneUse(m_SExt(m_Value(Op0Src)))) && - Op0Src->getType()->getScalarSizeInBits() >= Op1C->getMinSignedBits()) { + Op0Src->getType()->getScalarSizeInBits() >= + Op1C->getSignificantBits()) { // In the general case, we need to make sure that the dividend is not the // minimum signed value because dividing that by -1 is UB. But here, we diff --git a/llvm/lib/Transforms/Scalar/Float2Int.cpp b/llvm/lib/Transforms/Scalar/Float2Int.cpp index f66d1b914b0b9..7d27b783f1372 100644 --- a/llvm/lib/Transforms/Scalar/Float2Int.cpp +++ b/llvm/lib/Transforms/Scalar/Float2Int.cpp @@ -391,8 +391,9 @@ bool Float2IntPass::validateAndTransform() { // The number of bits required is the maximum of the upper and // lower limits, plus one so it can be signed. - unsigned MinBW = std::max(R.getLower().getMinSignedBits(), - R.getUpper().getMinSignedBits()) + 1; + unsigned MinBW = std::max(R.getLower().getSignificantBits(), + R.getUpper().getSignificantBits()) + + 1; LLVM_DEBUG(dbgs() << "F2I: MinBitwidth=" << MinBW << ", R: " << R << "\n"); // If we've run off the realms of the exactly representable integers, diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp index c2b64c0e41a42..3045bd935f49e 100644 --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -799,7 +799,7 @@ static const SCEV *getExactSDiv(const SCEV *LHS, const SCEV *RHS, /// value, and mutate S to point to a new SCEV with that value excluded. static int64_t ExtractImmediate(const SCEV *&S, ScalarEvolution &SE) { if (const SCEVConstant *C = dyn_cast<SCEVConstant>(S)) { - if (C->getAPInt().getMinSignedBits() <= 64) { + if (C->getAPInt().getSignificantBits() <= 64) { S = SE.getConstant(C->getType(), 0); return C->getValue()->getSExtValue(); } @@ -1414,7 +1414,7 @@ void Cost::RateFormula(const Formula &F, C.ImmCost += 64; // Handle symbolic values conservatively. // TODO: This should probably be the pointer size. else if (Offset != 0) - C.ImmCost += APInt(64, Offset, true).getMinSignedBits(); + C.ImmCost += APInt(64, Offset, true).getSignificantBits(); // Check with target if this offset with this instruction is // specifically not supported. @@ -2498,7 +2498,7 @@ LSRInstance::OptimizeLoopTermCond() { if (C->isOne() || C->isMinusOne()) goto decline_post_inc; // Avoid weird situations. - if (C->getValue().getMinSignedBits() >= 64 || + if (C->getValue().getSignificantBits() >= 64 || C->getValue().isMinSignedValue()) goto decline_post_inc; // Check for possible scaled-address reuse. @@ -2740,13 +2740,13 @@ void LSRInstance::CollectInterestingTypesAndFactors() { if (const SCEVConstant *Factor = dyn_cast_or_null<SCEVConstant>(getExactSDiv(NewStride, OldStride, SE, true))) { - if (Factor->getAPInt().getMinSignedBits() <= 64 && !Factor->isZero()) + if (Factor->getAPInt().getSignificantBits() <= 64 && !Factor->isZero()) Factors.insert(Factor->getAPInt().getSExtValue()); } else if (const SCEVConstant *Factor = dyn_cast_or_null<SCEVConstant>(getExactSDiv(OldStride, NewStride, SE, true))) { - if (Factor->getAPInt().getMinSignedBits() <= 64 && !Factor->isZero()) + if (Factor->getAPInt().getSignificantBits() <= 64 && !Factor->isZero()) Factors.insert(Factor->getAPInt().getSExtValue()); } } @@ -3175,7 +3175,7 @@ static bool canFoldIVIncExpr(const SCEV *IncExpr, Instruction *UserInst, if (!IncConst || !isAddressUse(TTI, UserInst, Operand)) return false; - if (IncConst->getAPInt().getMinSignedBits() > 64) + if (IncConst->getAPInt().getSignificantBits() > 64) return false; MemAccessTy AccessTy = getAccessType(TTI, UserInst, Operand); @@ -6063,7 +6063,7 @@ struct SCEVDbgValueBuilder { } bool pushConst(const SCEVConstant *C) { - if (C->getAPInt().getMinSignedBits() > 64) + if (C->getAPInt().getSignificantBits() > 64) return false; Expr.push_back(llvm::dwarf::DW_OP_consts); Expr.push_back(C->getAPInt().getSExtValue()); @@ -6152,7 +6152,7 @@ struct SCEVDbgValueBuilder { /// SCEV constant value is an identity function. bool isIdentityFunction(uint64_t Op, const SCEV *S) { if (const SCEVConstant *C = dyn_cast<SCEVConstant>(S)) { - if (C->getAPInt().getMinSignedBits() > 64) + if (C->getAPInt().getSignificantBits() > 64) return false; int64_t I = C->getAPInt().getSExtValue(); switch (Op) { @@ -6500,7 +6500,7 @@ static bool SalvageDVI(llvm::Loop *L, ScalarEvolution &SE, // less DWARF ops than an iteration count-based expression. if (std::optional<APInt> Offset = SE.computeConstantDifference(DVIRec.SCEVs[i], SCEVInductionVar)) { - if (Offset->getMinSignedBits() <= 64) + if (Offset->getSignificantBits() <= 64) SalvageExpr->createOffsetExpr(Offset->getSExtValue(), LSRInductionVar); } else if (!SalvageExpr->createIterCountExpr(DVIRec.SCEVs[i], IterCountExpr, SE)) diff --git a/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp b/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp index 930a0bcbfac57..73a50b793e6d2 100644 --- a/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp +++ b/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp @@ -202,7 +202,7 @@ bool FastDivInsertionTask::isHashLikeValue(Value *V, VisitedSetTy &Visited) { ConstantInt *C = dyn_cast<ConstantInt>(Op1); if (!C && isa<BitCastInst>(Op1)) C = dyn_cast<ConstantInt>(cast<BitCastInst>(Op1)->getOperand(0)); - return C && C->getValue().getMinSignedBits() > BypassType->getBitWidth(); + return C && C->getValue().getSignificantBits() > BypassType->getBitWidth(); } case Instruction::PHI: // Stop IR traversal in case of a crazy input code. This limits recursion diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 73b3bb3f454ee..769c095e29fea 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -5453,7 +5453,7 @@ static bool eliminateDeadSwitchCases(SwitchInst *SI, DomTreeUpdater *DTU, } const APInt &CaseVal = Case.getCaseValue()->getValue(); if (Known.Zero.intersects(CaseVal) || !Known.One.isSubsetOf(CaseVal) || - (CaseVal.getMinSignedBits() > MaxSignificantBitsInCond)) { + (CaseVal.getSignificantBits() > MaxSignificantBitsInCond)) { DeadCases.push_back(Case.getCaseValue()); if (DTU) --NumPerSuccessorCases[Successor]; diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp index 0b7fc853dc1b0..601d0ab82e4d4 100644 --- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp @@ -346,8 +346,8 @@ bool Vectorizer::areConsecutivePointers(Value *PtrA, Value *PtrB, // stripAndAccumulateInBoundsConstantOffsets should properly handle a // possible overflow and the value should fit into a smallest data type // used in the cast/gep chain. - assert(OffsetA.getMinSignedBits() <= NewPtrBitWidth && - OffsetB.getMinSignedBits() <= NewPtrBitWidth); + assert(OffsetA.getSignificantBits() <= NewPtrBitWidth && + OffsetB.getSignificantBits() <= NewPtrBitWidth); OffsetA = OffsetA.sextOrTrunc(NewPtrBitWidth); OffsetB = OffsetB.sextOrTrunc(NewPtrBitWidth); diff --git a/polly/lib/Support/GICHelper.cpp b/polly/lib/Support/GICHelper.cpp index 638289c86becf..0e491944c162e 100644 --- a/polly/lib/Support/GICHelper.cpp +++ b/polly/lib/Support/GICHelper.cpp @@ -74,8 +74,8 @@ APInt polly::APIntFromVal(__isl_take isl_val *Val) { // isl may represent small numbers with more than the minimal number of bits. // We truncate the APInt to the minimal number of bits needed to represent the // signed value it contains, to ensure that the bitwidth is always minimal. - if (A.getMinSignedBits() < A.getBitWidth()) - A = A.trunc(A.getMinSignedBits()); + if (A.getSignificantBits() < A.getBitWidth()) + A = A.trunc(A.getSignificantBits()); free(Data); isl_val_free(Val); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits