https://github.com/uweigand closed
https://github.com/llvm/llvm-project/pull/74625
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JonPsson1 wrote:
Thanks for explanations.
Updates to my comments LGTM.
https://github.com/llvm/llvm-project/pull/74625
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@@ -1516,48 +1536,206 @@ let Predicates = [FeatureVector] in {
}
}
+//===--===//
+// Support for 128-bit integer values in vector registers
+//===-
uweigand wrote:
@JonPsson1 - please have a look at the effects of i128 support in particular on
atomics
@redstar - can you check impact on the z/OS ABI? we may need to handle legal
i128 there too, but there doesn't appear to be any in-tree test case for
passing i128 on z/OS
Any other comment
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-llvm-selectiondag
Author: Ulrich Weigand (uweigand)
Changes
On processors supporting vector registers and SIMD instructions, enable i128 as
legal type in VRs. This allows many operations to be implemented via native
in
