@@ -188,3 +188,8 @@ addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid
operand for instruction
# fence.tso accepts no operands
fence.tso rw, rw # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
+.Ltlsdesc_hi0:
+jalr x5, 0(a1), %tlsdesc_hi(.Ltlsdesc_hi0)
@@ -6843,6 +6845,24 @@ SDValue
RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
return LowerCallTo(CLI).first;
}
+SDValue
+RISCVTargetLowering::getGeneralDynamicTLSDescAddr(GlobalAddressSDNode *N,
ilovepi wrote:
done.
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/66915
>From ce9772dd519a62025cf545ded306bf40c75f2924 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Tue, 19 Sep 2023 20:53:54 +
Subject: [PATCH 1/7] [RISCV] Support Global Dynamic TLSDESC in the RISC-V
backend
@@ -6843,6 +6845,24 @@ SDValue
RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
return LowerCallTo(CLI).first;
}
+SDValue
+RISCVTargetLowering::getGeneralDynamicTLSDescAddr(GlobalAddressSDNode *N,
MaskRay wrote:
getTLSDescAddr sounds good.
@@ -6843,6 +6845,24 @@ SDValue
RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
return LowerCallTo(CLI).first;
}
+SDValue
+RISCVTargetLowering::getGeneralDynamicTLSDescAddr(GlobalAddressSDNode *N,
ilovepi wrote:
Well, AArch64 handles