Author: tra Date: Thu May 19 13:44:45 2016 New Revision: 270094 URL: http://llvm.org/viewvc/llvm-project?rev=270094&view=rev Log: [CUDA] Enable fusing FP ops (-ffp-contract=fast) for CUDA by default.
This matches default nvcc behavior and gives substantial performance boost on GPU where fmad is much cheaper compared to add+mul. Differential Revision: http://reviews.llvm.org/D20341 Added: cfe/trunk/test/CodeGenCUDA/fp-contract.cu Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/CompilerInvocation.cpp?rev=270094&r1=270093&r2=270094&view=diff ============================================================================== --- cfe/trunk/lib/Frontend/CompilerInvocation.cpp (original) +++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp Thu May 19 13:44:45 2016 @@ -2255,10 +2255,15 @@ bool CompilerInvocation::CreateFromArgs( LangOpts.ObjCExceptions = 1; } - // During CUDA device-side compilation, the aux triple is the triple used for - // host compilation. - if (LangOpts.CUDA && LangOpts.CUDAIsDevice) { - Res.getTargetOpts().HostTriple = Res.getFrontendOpts().AuxTriple; + if (LangOpts.CUDA) { + // During CUDA device-side compilation, the aux triple is the + // triple used for host compilation. + if (LangOpts.CUDAIsDevice) + Res.getTargetOpts().HostTriple = Res.getFrontendOpts().AuxTriple; + + // Set default FP_CONTRACT to FAST. + if (!Args.hasArg(OPT_ffp_contract)) + Res.getCodeGenOpts().setFPContractMode(CodeGenOptions::FPC_Fast); } // FIXME: Override value name discarding when asan or msan is used because the Added: cfe/trunk/test/CodeGenCUDA/fp-contract.cu URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCUDA/fp-contract.cu?rev=270094&view=auto ============================================================================== --- cfe/trunk/test/CodeGenCUDA/fp-contract.cu (added) +++ cfe/trunk/test/CodeGenCUDA/fp-contract.cu Thu May 19 13:44:45 2016 @@ -0,0 +1,32 @@ +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target + +// By default we should fuse multiply/add into fma instruction. +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -disable-llvm-passes -o - %s | FileCheck -check-prefix ENABLED %s + +// Explicit -ffp-contract=fast +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -ffp-contract=fast -disable-llvm-passes -o - %s \ +// RUN: | FileCheck -check-prefix ENABLED %s + +// Explicit -ffp-contract=on -- fusing by front-end (disabled). +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -ffp-contract=on -disable-llvm-passes -o - %s \ +// RUN: | FileCheck -check-prefix DISABLED %s + +// Explicit -ffp-contract=off should disable instruction fusing. +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -ffp-contract=off -disable-llvm-passes -o - %s \ +// RUN: | FileCheck -check-prefix DISABLED %s + + +#include "Inputs/cuda.h" + +__host__ __device__ float func(float a, float b, float c) { return a + b * c; } +// ENABLED: fma.rn.f32 +// ENABLED-NEXT: st.param.f32 + +// DISABLED: mul.rn.f32 +// DISABLED-NEXT: add.rn.f32 +// DISABLED-NEXT: st.param.f32 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits