Author: dnsampaio Date: Wed Jul 10 01:16:49 2019 New Revision: 365598 URL: http://llvm.org/viewvc/llvm-project?rev=365598&view=rev Log: [NFC][AArch64] Fix vector vqtb[lx][1-4]_s8 operand
Summary: Change the vqtb[lx][1-4]_s8 instrinsics to have the last argument as vector of unsigned valuse, not signed, accordingly to https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics Reviewers: LukeCheeseman, DavidSpickett Reviewed By: DavidSpickett Subscribers: DavidSpickett, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64243 Modified: cfe/trunk/include/clang/Basic/arm_neon.td cfe/trunk/test/CodeGen/aarch64-neon-tbl.c Modified: cfe/trunk/include/clang/Basic/arm_neon.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=365598&r1=365597&r2=365598&view=diff ============================================================================== --- cfe/trunk/include/clang/Basic/arm_neon.td (original) +++ cfe/trunk/include/clang/Basic/arm_neon.td Wed Jul 10 01:16:49 2019 @@ -1070,16 +1070,16 @@ def VUZP2 : SOpInst<"vuzp2", "ddd", //////////////////////////////////////////////////////////////////////////////// // Table lookup let InstName = "vtbl" in { -def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">; -def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">; -def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">; -def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">; +def VQTBL1_A64 : WInst<"vqtbl1", "dju", "UccPcQUcQcQPc">; +def VQTBL2_A64 : WInst<"vqtbl2", "dBu", "UccPcQUcQcQPc">; +def VQTBL3_A64 : WInst<"vqtbl3", "dCu", "UccPcQUcQcQPc">; +def VQTBL4_A64 : WInst<"vqtbl4", "dDu", "UccPcQUcQcQPc">; } let InstName = "vtbx" in { -def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">; -def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">; -def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">; -def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">; +def VQTBX1_A64 : WInst<"vqtbx1", "ddju", "UccPcQUcQcQPc">; +def VQTBX2_A64 : WInst<"vqtbx2", "ddBu", "UccPcQUcQcQPc">; +def VQTBX3_A64 : WInst<"vqtbx3", "ddCu", "UccPcQUcQcQPc">; +def VQTBX4_A64 : WInst<"vqtbx4", "ddDu", "UccPcQUcQcQPc">; } //////////////////////////////////////////////////////////////////////////////// Modified: cfe/trunk/test/CodeGen/aarch64-neon-tbl.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-tbl.c?rev=365598&r1=365597&r2=365598&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/aarch64-neon-tbl.c (original) +++ cfe/trunk/test/CodeGen/aarch64-neon-tbl.c Wed Jul 10 01:16:49 2019 @@ -16,7 +16,7 @@ int8x8_t test_vtbl1_s8(int8x8_t a, int8x // CHECK-LABEL: define <8 x i8> @test_vqtbl1_s8(<16 x i8> %a, <8 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL1_I]] -int8x8_t test_vqtbl1_s8(int8x16_t a, int8x8_t b) { +int8x8_t test_vqtbl1_s8(int8x16_t a, uint8x8_t b) { return vqtbl1_s8(a, b); } @@ -59,7 +59,7 @@ int8x8_t test_vtbl2_s8(int8x8x2_t a, int // CHECK: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX2_I]], align 16 // CHECK: [[VTBL2_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]], <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL2_I]] -int8x8_t test_vqtbl2_s8(int8x16x2_t a, int8x8_t b) { +int8x8_t test_vqtbl2_s8(int8x16x2_t a, uint8x8_t b) { return vqtbl2_s8(a, b); } @@ -109,7 +109,7 @@ int8x8_t test_vtbl3_s8(int8x8x3_t a, int // CHECK: [[TMP3:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX4_I]], align 16 // CHECK: [[VTBL3_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL3_I]] -int8x8_t test_vqtbl3_s8(int8x16x3_t a, int8x8_t b) { +int8x8_t test_vqtbl3_s8(int8x16x3_t a, uint8x8_t b) { return vqtbl3_s8(a, b); } @@ -165,7 +165,7 @@ int8x8_t test_vtbl4_s8(int8x8x4_t a, int // CHECK: [[TMP4:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX6_I]], align 16 // CHECK: [[VTBL4_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl4.v8i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <16 x i8> [[TMP4]], <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL4_I]] -int8x8_t test_vqtbl4_s8(int8x16x4_t a, int8x8_t b) { +int8x8_t test_vqtbl4_s8(int8x16x4_t a, uint8x8_t b) { return vqtbl4_s8(a, b); } @@ -348,7 +348,7 @@ int8x8_t test_vtbx4_s8(int8x8_t a, int8x // CHECK-LABEL: define <8 x i8> @test_vqtbx1_s8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX1_I]] -int8x8_t test_vqtbx1_s8(int8x8_t a, int8x16_t b, int8x8_t c) { +int8x8_t test_vqtbx1_s8(int8x8_t a, int8x16_t b, uint8x8_t c) { return vqtbx1_s8(a, b, c); } @@ -369,7 +369,7 @@ int8x8_t test_vqtbx1_s8(int8x8_t a, int8 // CHECK: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX2_I]], align 16 // CHECK: [[VTBX2_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx2.v8i8(<8 x i8> %a, <16 x i8> [[TMP1]], <16 x i8> [[TMP2]], <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX2_I]] -int8x8_t test_vqtbx2_s8(int8x8_t a, int8x16x2_t b, int8x8_t c) { +int8x8_t test_vqtbx2_s8(int8x8_t a, int8x16x2_t b, uint8x8_t c) { return vqtbx2_s8(a, b, c); } @@ -393,7 +393,7 @@ int8x8_t test_vqtbx2_s8(int8x8_t a, int8 // CHECK: [[TMP3:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX4_I]], align 16 // CHECK: [[VTBX3_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx3.v8i8(<8 x i8> %a, <16 x i8> [[TMP1]], <16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX3_I]] -int8x8_t test_vqtbx3_s8(int8x8_t a, int8x16x3_t b, int8x8_t c) { +int8x8_t test_vqtbx3_s8(int8x8_t a, int8x16x3_t b, uint8x8_t c) { return vqtbx3_s8(a, b, c); } @@ -420,14 +420,14 @@ int8x8_t test_vqtbx3_s8(int8x8_t a, int8 // CHECK: [[TMP4:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX6_I]], align 16 // CHECK: [[VTBX4_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx4.v8i8(<8 x i8> %a, <16 x i8> [[TMP1]], <16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <16 x i8> [[TMP4]], <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX4_I]] -int8x8_t test_vqtbx4_s8(int8x8_t a, int8x16x4_t b, int8x8_t c) { +int8x8_t test_vqtbx4_s8(int8x8_t a, int8x16x4_t b, uint8x8_t c) { return vqtbx4_s8(a, b, c); } // CHECK-LABEL: define <16 x i8> @test_vqtbx1q_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3 // CHECK: ret <16 x i8> [[VTBX1_I]] -int8x16_t test_vqtbx1q_s8(int8x16_t a, int8x16_t b, int8x16_t c) { +int8x16_t test_vqtbx1q_s8(int8x16_t a, int8x16_t b, uint8x16_t c) { return vqtbx1q_s8(a, b, c); } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits