date:20240116

[llvm] [libcxx] [compiler-rt] [clang-tools-extra] [flang] [lld] [mlir] [libc] [clang] [lldb] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

2024-01-16 Thread Fangrui Song via cfe-commits


https://github.com/MaskRay edited 
https://github.com/llvm/llvm-project/pull/77886
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[llvm] [libcxx] [compiler-rt] [clang-tools-extra] [flang] [lld] [mlir] [libc] [clang] [lldb] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

2024-01-16 Thread Fangrui Song via cfe-commits


https://github.com/MaskRay closed 
https://github.com/llvm/llvm-project/pull/77886
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[clang] d4cb5d9 - [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (#77886)

2024-01-16 Thread via cfe-commits


Author: Fangrui Song
Date: 2024-01-16T23:57:42-08:00
New Revision: d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7

URL: 
https://github.com/llvm/llvm-project/commit/d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7
DIFF: 
https://github.com/llvm/llvm-project/commit/d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7.diff

LOG: [X86] Add "Ws" constraint and "p" modifier for symbolic address/label 
reference (#77886)

Printing the raw symbol is useful in inline asm (e.g. getting the C++
mangled name, referencing a symbol in a custom way while ensuring it is
not optimized out even if internal). Similar constraints are available
in other targets (e.g. "S" for aarch64/riscv, "Cs" for m68k).

```
namespace ns { extern int var, a[4]; }
void foo() {
  asm(".pushsection .xxx,\"aw\"; .dc.a %p0; .popsection" :: "Ws"(::var));
  asm(".reloc ., BFD_RELOC_NONE, %p0" :: "Ws"(::a[3]));
}
```

Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105576

Added: 
llvm/test/CodeGen/X86/inline-asm-Ws-constraint-error.ll
llvm/test/CodeGen/X86/inline-asm-Ws-constraint.ll

Modified: 
clang/lib/Basic/Targets/X86.cpp
clang/test/CodeGen/X86/inline-asm-constraints.c
clang/test/Sema/inline-asm-validate-x86.c
llvm/docs/LangRef.rst
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 64e281b888a95f..a68b662d9401aa 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -1418,6 +1418,14 @@ bool X86TargetInfo::validateAsmConstraint(
   case 'O':
 Info.setRequiresImmediate(0, 127);
 return true;
+  case 'W':
+switch (*++Name) {
+default:
+  return false;
+case 's':
+  Info.setAllowsRegister();
+  return true;
+}
   // Register constraints.
   case 'Y': // 'Y' is the first character for several 2-character constraints.
 // Shift the pointer to the second character of the constraint.
@@ -1715,6 +1723,9 @@ std::string X86TargetInfo::convertConstraint(const char 
*) const {
 return std::string("{st}");
   case 'u':// second from top of floating point stack.
 return std::string("{st(1)}"); // second from top of floating point stack.
+  case 'W':
+assert(Constraint[1] == 's');
+return '^' + std::string(Constraint++, 2);
   case 'Y':
 switch (Constraint[1]) {
 default:

diff  --git a/clang/test/CodeGen/X86/inline-asm-constraints.c 
b/clang/test/CodeGen/X86/inline-asm-constraints.c
index b75a84d7a7bcbf..c89d94cab946b3 100644
--- a/clang/test/CodeGen/X86/inline-asm-constraints.c
+++ b/clang/test/CodeGen/X86/inline-asm-constraints.c
@@ -53,3 +53,14 @@ __m512 testZMM0(void) {
 #endif
   return zmm0;
 }
+
+extern int var, arr[4];
+struct Pair { int a, b; } pair;
+
+// CHECK-LABEL: test_Ws(
+// CHECK: call void asm sideeffect "// ${0:p} ${1:p} ${2:p}", 
"^Ws,^Ws,^Ws,~{dirflag},~{fpsr},~{flags}"(ptr @var, ptr getelementptr inbounds 
([4 x i32], ptr @arr, i64 0, i64 3), ptr @test_Ws)
+// CHECK: call void asm sideeffect "// $0", 
"^Ws,~{dirflag},~{fpsr},~{flags}"(ptr getelementptr inbounds (%struct.Pair, ptr 
@pair, i32 0, i32 1))
+void test_Ws(void) {
+  asm("// %p0 %p1 %p2" :: "Ws"(), "Ws"([3]), "Ws"(test_Ws));
+  asm("// %0" :: "Ws"());
+}

diff  --git a/clang/test/Sema/inline-asm-validate-x86.c 
b/clang/test/Sema/inline-asm-validate-x86.c
index 87b60a0955301a..d4c10c36f5fbea 100644
--- a/clang/test/Sema/inline-asm-validate-x86.c
+++ b/clang/test/Sema/inline-asm-validate-x86.c
@@ -130,3 +130,11 @@ void pr40890(void) {
   __asm__ __volatile__("\n#define BEEF abcd%0\n" : : 
"n"((int*)0xdeadbeef));
 #endif
 }
+
+void test_W(int i) {
+  __asm__("" : : "Wd"(test_W)); // expected-error{{invalid input constraint 
'Wd' in asm}}
+
+  __asm__("" : : "Ws"(test_W(0))); // expected-error{{invalid type 'void' in 
asm input for constraint 'Ws'}}
+  // Codegen error
+  __asm__("" : : "Ws"(i));
+}

diff  --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index d881deb30049a2..27429ad1f43c99 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5336,6 +5336,8 @@ X86:
   operand in a SSE register. If AVX is also enabled, can also be a 256-bit
   vector operand in an AVX register. If AVX-512 is also enabled, can also be a
   512-bit vector operand in an AVX512 register. Otherwise, an error.
+- ``Ws``: A symbolic reference with an optional constant addend or a label
+  reference.
 - ``x``: The same as ``v``, except that when AVX-512 is enabled, the ``x`` code
   only allocates into the first 16 AVX-512 registers, while the ``v`` code
   allocates into any of the 32 AVX-512 registers.
@@ -5518,6 +5520,7 @@ X86:
   the operand. (The behavior for relocatable symbol expressions is a
   target-specific behavior for this typically target-independent modifier)
 - ``H``: Print a memory reference with additional offset

[clang] [clang] Fix parenthesized list initialization of arrays not working with `new` (PR #76976)

2024-01-16 Thread via cfe-commits


cor3ntin wrote:

@MitalAshok You want to review this?

https://github.com/llvm/llvm-project/pull/76976
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[clang] [Clang][Sema] fix crash of attribute transform (PR #78088)

2024-01-16 Thread via cfe-commits



@@ -7081,10 +7085,10 @@ QualType 
TreeTransform::TransformAttributedType(
   // FIXME: dependent operand expressions?
   if (getDerived().AlwaysRebuild() ||
   modifiedType != oldType->getModifiedType()) {
-// TODO: this is really lame; we should really be rebuilding the
-// equivalent type from first principles.
-QualType equivalentType
-  = getDerived().TransformType(oldType->getEquivalentType());
+TypeLocBuilder AuxiliaryTLB;
+AuxiliaryTLB.reserve(TL.getFullDataSize());

cor3ntin wrote:

an alternative might be to call 
`TLB.TypeWasModifiedSafely(result)` (after the call to `getAttributedType` 
below).
I wonder if @AaronBallman  has a better alternative

https://github.com/llvm/llvm-project/pull/78088
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[clang-tools-extra] [clang] [llvm] [CLANG] Fix : More Detailed "No expected directives found" (PR #78338)

2024-01-16 Thread Anton Korobeynikov via cfe-commits



@@ -9,7 +9,7 @@
 /// \file
 /// Defines the Diagnostic-related interfaces.
 //
-//===--===//
+//===--===//]

asl wrote:

still unrelated change. I would suggest you to carefully check all the code in 
the PR

https://github.com/llvm/llvm-project/pull/78338
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[clang] [Clang] fix static operator()/[] call not evaluating object (PR #78356)

2024-01-16 Thread A. Jiang via cfe-commits



@@ -598,3 +600,27 @@ namespace B {
 }
 void g(B::X x) { A::f(x); }
 }
+
+namespace static_operator {
+#if __cplusplus >= 201703L

frederick-vs-ja wrote:

Why C++17?

https://github.com/llvm/llvm-project/pull/78356
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[clang-tools-extra] [clang] [llvm] [CLANG] Fix : More Detailed "No expected directives found" (PR #78338)

2024-01-16 Thread Anton Korobeynikov via cfe-commits



@@ -635,16 +635,16 @@ def execute_command(self) -> bool:
 """
 This function reads lines from STDIN and executes the first command
 that it finds.  The 2 supported commands are:
-/cherry-pick commit0   <...>

asl wrote:

You certainly could submit multiple PRs for separate changes.

https://github.com/llvm/llvm-project/pull/78338
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[clang] [Clang] fix static operator()/[] call not evaluating object (PR #78356)

2024-01-16 Thread A. Jiang via cfe-commits


https://github.com/frederick-vs-ja edited 
https://github.com/llvm/llvm-project/pull/78356
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[clang] [Clang] fix static operator()/[] call not evaluating object (PR #78356)

2024-01-16 Thread A. Jiang via cfe-commits


https://github.com/frederick-vs-ja commented:

It seems that more things are being done #68485. Have you double checked that 
PR?

https://github.com/llvm/llvm-project/pull/78356
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[clang] [llvm] [AMDGPU] Add GFX12 WMMA and SWMMAC instructions (PR #77795)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -423,6 +423,67 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi", 
"n", "gfx12-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts")
 
+//===--===//
+// WMMA builtins.
+// Postfix w32 indicates the builtin requires wavefront size of 32.
+// Postfix w64 indicates the builtin requires wavefront size of 64.
+//
+// Some of these are very similar to their GFX11 counterparts, but they don't
+// require replication of the A,B matrices, so they use fewer vector elements.
+// Therefore, we add an "_gfx12" suffix to distinguish them from the existing
+// builtins.
+//===--===//
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_f16_w32_gfx12, 
"V8fV8hV8hV8f", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_bf16_w32_gfx12, 
"V8fV8sV8sV8f", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f16_16x16x16_f16_w32_gfx12, 
"V8hV8hV8hV8h", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w32_gfx12, 
"V8sV8sV8sV8s", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_i32_16x16x16_iu8_w32_gfx12, 
"V8iIbV2iIbV2iV8iIb", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_i32_16x16x16_iu4_w32_gfx12, 
"V8iIbiIbiV8iIb", "nc", "gfx12-insts,wavefrontsize32")
+// These are gfx12-only, but for consistency with the other WMMA variants we're
+// keeping the "_gfx12" suffix.
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_fp8_fp8_w32_gfx12, 
"V8fV2iV2iV8f", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_fp8_bf8_w32_gfx12, 
"V8fV2iV2iV8f", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_bf8_fp8_w32_gfx12, 
"V8fV2iV2iV8f", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_bf8_bf8_w32_gfx12, 
"V8fV2iV2iV8f", "nc", "gfx12-insts,wavefrontsize32")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_i32_16x16x32_iu4_w32_gfx12, 
"V8iIbV2iIbV2iV8iIb", "nc", "gfx12-insts,wavefrontsize32")
+
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_f16_w64_gfx12, 
"V4fV4hV4hV4f", "nc", "gfx12-insts,wavefrontsize64")
+TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_bf16_w64_gfx12, 
"V4fV4sV4sV4f", "nc", "gfx12-insts,wavefrontsize64")

arsenm wrote:

Can we switch new bf16 types to use the natural __bf16?

https://github.com/llvm/llvm-project/pull/77795
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[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

2024-01-16 Thread Mariusz Sikora via cfe-commits


https://github.com/mariusz-sikora-at-amd updated 
https://github.com/llvm/llvm-project/pull/76224

>From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001
From: Vang Thao 
Date: Thu, 21 Dec 2023 11:58:47 +0100
Subject: [PATCH 1/6] [AMDGPU][GFX12] Add Atomic cond_sub_u32

---
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |  19 +-
 llvm/lib/Target/AMDGPU/AMDGPUGISel.td |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h   |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUInstructions.td  |   4 +
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |   3 +
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   3 +
 .../Target/AMDGPU/AMDGPUSearchableTables.td   |   7 +
 llvm/lib/Target/AMDGPU/BUFInstructions.td |  14 +
 llvm/lib/Target/AMDGPU/DSInstructions.td  |  27 +-
 llvm/lib/Target/AMDGPU/FLATInstructions.td|  31 +++
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp |  10 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.td |   1 +
 llvm/lib/Target/AMDGPU/SIInstructions.td  |   1 +
 llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll  | 254 ++
 .../AMDGPU/llvm.amdgcn.atomic.cond.sub.ll | 171 
 llvm/test/MC/AMDGPU/gfx11_unsupported.s   |  12 +
 llvm/test/MC/AMDGPU/gfx12_asm_ds.s|  18 ++
 llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s |  66 +
 llvm/test/MC/AMDGPU/gfx12_asm_vflat.s |  36 +++
 .../MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt  |  81 ++
 .../AMDGPU/gfx12_dasm_vbuffer_mubuf.txt   |  42 +++
 .../Disassembler/AMDGPU/gfx12_dasm_vflat.txt  |  18 ++
 23 files changed, 812 insertions(+), 9 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index cb48f54b13a6cd..2d066350ee9f84 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -10,6 +10,10 @@
 //
 
//===--===//
 
+def flat_ptr_ty : LLVMQualPointerType<0>;
+def global_ptr_ty : LLVMQualPointerType<1>;
+def local_ptr_ty : LLVMQualPointerType<3>;
+
 class AMDGPUReadPreloadRegisterIntrinsic
   : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
 
@@ -1243,6 +1247,7 @@ def int_amdgcn_raw_buffer_atomic_or : 
AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic;
+def int_amdgcn_raw_buffer_atomic_cond_sub_u32 : AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -1279,6 +1284,7 @@ def int_amdgcn_raw_ptr_buffer_atomic_or : 
AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_xor : AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_inc : AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_dec : AMDGPURawPtrBufferAtomic;
+def int_amdgcn_raw_ptr_buffer_atomic_cond_sub_u32 : AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -1317,6 +1323,7 @@ def int_amdgcn_struct_buffer_atomic_or : 
AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic;
+def int_amdgcn_struct_buffer_atomic_cond_sub_u32 : AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -1352,6 +1359,7 @@ def int_amdgcn_struct_ptr_buffer_atomic_or : 
AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_xor : AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_inc : AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_dec : AMDGPUStructPtrBufferAtomic;
+def int_amdgcn_struct_ptr_buffer_atomic_cond_sub_u32 : 
AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -2353,10 +2361,10 @@ def int_amdgcn_s_get_waveid_in_workgroup :
   Intrinsic<[llvm_i32_ty], [],
 [IntrNoMem, IntrHasSideEffects, IntrWillReturn, IntrNoCallback, 
IntrNoFree]>;
 
-class AMDGPUAtomicRtn : Intrinsic <
+class AMDGPUAtomicRtn : Intrinsic <
   [vt],
-  [llvm_anyptr_ty,// vaddr
-   vt],   // vdata(VGPR)
+  [pt,  // vaddr
+   vt], // vdata(VGPR)
   [IntrArgMemOnly, IntrWillReturn, NoCapture>, IntrNoCallback, 
IntrNoFree], "",
   [SDNPMemOperand]>;
 
@@ -2491,6 +2499,11 @@ def int_amdgcn_flat_atomic_fmax_num   : 
AMDGPUAtomicRtn;
 def int_amdgcn_global_atomic_fmin_num : AMDGPUAtomicRtn;

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

2024-01-16 Thread Mariusz Sikora via cfe-commits



@@ -1182,6 +1182,11 @@ The AMDGPU backend implements the following LLVM IR 
intrinsics.
 
The iglp_opt strategy 
implementations are subject to change.
 
+  llvm.atomic.cond.sub.u32 Provides direct access to 
flat_atomic_cond_sub_u32, global_atomic_cond_sub_u32

mariusz-sikora-at-amd wrote:

ah, thanks !

https://github.com/llvm/llvm-project/pull/76224
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[clang] [llvm] [GitHub] Add python 3.7 to libclang python test (PR #77219)

2024-01-16 Thread Vlad Serebrennikov via cfe-commits


https://github.com/Endilll approved this pull request.

LGTM. I believe we can go ahead with this even if discussion about raising 
minimum Python version is not going anywhere. Better test 3.7 and 3.11 than 
just 3.11 anyway.

https://github.com/llvm/llvm-project/pull/77219
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[clang-tools-extra] [clang] [llvm] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -1182,6 +1182,11 @@ The AMDGPU backend implements the following LLVM IR 
intrinsics.
 
The iglp_opt strategy 
implementations are subject to change.
 
+  llvm.atomic.cond.sub.u32 Provides direct access to 
flat_atomic_cond_sub_u32, global_atomic_cond_sub_u32

arsenm wrote:

missed the amdgcn part 

https://github.com/llvm/llvm-project/pull/76224
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[clang-tools-extra] [clang] [llvm] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

2024-01-16 Thread Mariusz Sikora via cfe-commits


https://github.com/mariusz-sikora-at-amd updated 
https://github.com/llvm/llvm-project/pull/76224

>From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001
From: Vang Thao 
Date: Thu, 21 Dec 2023 11:58:47 +0100
Subject: [PATCH 1/5] [AMDGPU][GFX12] Add Atomic cond_sub_u32

---
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |  19 +-
 llvm/lib/Target/AMDGPU/AMDGPUGISel.td |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h   |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUInstructions.td  |   4 +
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |   3 +
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   3 +
 .../Target/AMDGPU/AMDGPUSearchableTables.td   |   7 +
 llvm/lib/Target/AMDGPU/BUFInstructions.td |  14 +
 llvm/lib/Target/AMDGPU/DSInstructions.td  |  27 +-
 llvm/lib/Target/AMDGPU/FLATInstructions.td|  31 +++
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp |  10 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.td |   1 +
 llvm/lib/Target/AMDGPU/SIInstructions.td  |   1 +
 llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll  | 254 ++
 .../AMDGPU/llvm.amdgcn.atomic.cond.sub.ll | 171 
 llvm/test/MC/AMDGPU/gfx11_unsupported.s   |  12 +
 llvm/test/MC/AMDGPU/gfx12_asm_ds.s|  18 ++
 llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s |  66 +
 llvm/test/MC/AMDGPU/gfx12_asm_vflat.s |  36 +++
 .../MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt  |  81 ++
 .../AMDGPU/gfx12_dasm_vbuffer_mubuf.txt   |  42 +++
 .../Disassembler/AMDGPU/gfx12_dasm_vflat.txt  |  18 ++
 23 files changed, 812 insertions(+), 9 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index cb48f54b13a6cda..2d066350ee9f84e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -10,6 +10,10 @@
 //
 
//===--===//
 
+def flat_ptr_ty : LLVMQualPointerType<0>;
+def global_ptr_ty : LLVMQualPointerType<1>;
+def local_ptr_ty : LLVMQualPointerType<3>;
+
 class AMDGPUReadPreloadRegisterIntrinsic
   : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
 
@@ -1243,6 +1247,7 @@ def int_amdgcn_raw_buffer_atomic_or : 
AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic;
+def int_amdgcn_raw_buffer_atomic_cond_sub_u32 : AMDGPURawBufferAtomic;
 def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -1279,6 +1284,7 @@ def int_amdgcn_raw_ptr_buffer_atomic_or : 
AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_xor : AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_inc : AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_dec : AMDGPURawPtrBufferAtomic;
+def int_amdgcn_raw_ptr_buffer_atomic_cond_sub_u32 : AMDGPURawPtrBufferAtomic;
 def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -1317,6 +1323,7 @@ def int_amdgcn_struct_buffer_atomic_or : 
AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic;
+def int_amdgcn_struct_buffer_atomic_cond_sub_u32 : AMDGPUStructBufferAtomic;
 def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -1352,6 +1359,7 @@ def int_amdgcn_struct_ptr_buffer_atomic_or : 
AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_xor : AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_inc : AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_dec : AMDGPUStructPtrBufferAtomic;
+def int_amdgcn_struct_ptr_buffer_atomic_cond_sub_u32 : 
AMDGPUStructPtrBufferAtomic;
 def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic<
   [llvm_anyint_ty],
   [LLVMMatchType<0>,  // src(VGPR)
@@ -2353,10 +2361,10 @@ def int_amdgcn_s_get_waveid_in_workgroup :
   Intrinsic<[llvm_i32_ty], [],
 [IntrNoMem, IntrHasSideEffects, IntrWillReturn, IntrNoCallback, 
IntrNoFree]>;
 
-class AMDGPUAtomicRtn : Intrinsic <
+class AMDGPUAtomicRtn : Intrinsic <
   [vt],
-  [llvm_anyptr_ty,// vaddr
-   vt],   // vdata(VGPR)
+  [pt,  // vaddr
+   vt], // vdata(VGPR)
   [IntrArgMemOnly, IntrWillReturn, NoCapture>, IntrNoCallback, 
IntrNoFree], "",
   [SDNPMemOperand]>;
 
@@ -2491,6 +2499,11 @@ def int_amdgcn_flat_atomic_fmax_num   : 
AMDGPUAtomicRtn;
 def int_amdgcn_global_atomic_fmin_num :

[clang] [clang][modules] Print library module manifest path. (PR #76451)

2024-01-16 Thread Mark de Wever via cfe-commits


mordante wrote:

> LGTM.
> 
> We need to delete 
> `clang/test/Driver/Inputs/cxx23_modules/usr/lib/x86_64-linux-gnu/libc++.so` 
> and 
> `clang/test/Driver/Inputs/cxx23_modules/usr/lib/x86_64-linux-gnu/modules.json`,
>  we should generate them with `split-file`

Are you sure that is the proper way? Should these tests not use a complete 
installation to make sure it works on installations?

https://github.com/llvm/llvm-project/pull/76451
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[clang] [llvm] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -1847,30 +1850,18 @@ struct CounterCoverageMappingBuilder
 // Extract the Parent Region Counter.
 Counter ParentCnt = getRegion().getCounter();
 
-// Extract the MCDC condition IDs (returns 0 if not needed).
-MCDCConditionID NextOrID = MCDCBuilder.getNextLOrCondID();
-MCDCConditionID NextAndID = MCDCBuilder.getNextLAndCondID();
 MCDCConditionID LHSid = MCDCBuilder.getCondID(E->getLHS());
 MCDCConditionID RHSid = MCDCBuilder.getCondID(E->getRHS());

chapuni wrote:

They may be moved to `createBranchRegion()` since `CondID` is available as 
`CondIDMap`.

https://github.com/llvm/llvm-project/pull/78202
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[clang] [llvm] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -1822,20 +1817,28 @@ struct CounterCoverageMappingBuilder
   }
 
   void VisitBinLAnd(const BinaryOperator *E) {
-// Keep track of Binary Operator and assign MCDC condition IDs
+bool IsRootNode = MCDCBuilder.isIdle();
+
+// Keep track of Binary Operator and assign MCDC condition IDs.
 MCDCBuilder.pushAndAssignIDs(E);
 
 extendRegion(E->getLHS());
 propagateCounts(getRegion().getCounter(), E->getLHS());
 handleFileExit(getEnd(E->getLHS()));
 
+// Track LHS True/False Decision.
+auto DecisionLHS = MCDCBuilder.pop();
+
 // Counter tracks the right hand side of a logical and operator.
 extendRegion(E->getRHS());
 propagateCounts(getRegionCounter(E), E->getRHS());
 
-// Process Binary Operator and create MCDC Decision Region if top-level
+// Track RHS True/False Decision.
+const auto  = MCDCBuilder.back();

chapuni wrote:

This might crash if it would be moved before `propagateCounts(getRHS)`, since 
the stack might be reallocated in children.
Could it be rewritten with passing by value (instead of by ref) for safety in 
the future?

https://github.com/llvm/llvm-project/pull/78202
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[clang] [llvm] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -663,9 +663,12 @@ struct MCDCCoverageBuilder {
 private:
   CodeGenModule 
 
-  llvm::SmallVector AndRHS;
-  llvm::SmallVector OrRHS;
-  llvm::SmallVector NestLevel;
+  struct DecisionIDPair {
+MCDCConditionID TrueID = 0;
+MCDCConditionID FalseID = 0;
+  };
+
+  llvm::SmallVector DecisionStack;

chapuni wrote:

The background why the number of inline elements is 1:
`DecisionStack`  is initialized with one `[0,0]` value as the sentinel 
(immutable, readonly). I thought most conditions will not grow up the stack 
since they don't meet logical ops. The stack may be reallocated when at least 
one logical op was found.

In contrast, possibly the maximum number of stack depth might be at most 6, I 
guess. The default number of inline elements is 6 on 
`llvm::SmallVector` in this case. The size is `16 + 8 * n` in 
general.

Which is better with `default(n=6)`: 64 bytes or `n=1`, 24 bytes?

https://github.com/llvm/llvm-project/pull/78202
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[llvm] [clang] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
 return E->getOpcode() == BO_LAnd;
   }
 
-  /// Push an ID onto the corresponding RHS stack.
-  void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[CodeGenFunction::stripCond(E->getRHS())]);
-  }
-
-  /// Pop an ID from the corresponding RHS stack.
-  void popRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-if (!rhs.empty())
-  rhs.pop_back();
-  }
-
-  /// If the expected ID is on top, pop it off the corresponding RHS stack.
-  void popRHSifTop(const BinaryOperator *E) {
-if (!OrRHS.empty() && CondIDs[E] == OrRHS.back())
-  OrRHS.pop_back();
-else if (!AndRHS.empty() && CondIDs[E] == AndRHS.back())
-  AndRHS.pop_back();
-  }
-
 public:
   MCDCCoverageBuilder(CodeGenModule ,
   llvm::DenseMap ,
   llvm::DenseMap )
-  : CGM(CGM), CondIDs(CondIDMap), MCDCBitmapMap(MCDCBitmapMap) {}
+  : CGM(CGM), DecisionStack(1), CondIDs(CondIDMap),

chapuni wrote:

It's better to write the concept of the stack onto `struct DecisionIDPair`.

https://github.com/llvm/llvm-project/pull/78202
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[clang] [llvm] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -730,68 +723,70 @@ struct MCDCCoverageBuilder {
   return;
 
 // If binary expression is disqualified, don't do mapping.
-if (NestLevel.empty() &&
-!MCDCBitmapMap.contains(CodeGenFunction::stripCond(E)))
+if (!isBuilding() && 
!MCDCBitmapMap.contains(CodeGenFunction::stripCond(E)))
   NotMapped = true;
 
-// Push Stmt on 'NestLevel' stack to keep track of nest location.
-NestLevel.push_back(E);
-
 // Don't go any further if we don't need to map condition IDs.
 if (NotMapped)
   return;
 
+assert(DecisionStack.size() >= 1);
+const DecisionIDPair  = DecisionStack.back();
+
 // If the operator itself has an assigned ID, this means it represents a
-// larger subtree.  In this case, pop its ID out of the RHS stack and
-// assign that ID to its LHS node.  Its RHS will receive a new ID.
-if (CondIDs.contains(CodeGenFunction::stripCond(E))) {
-  // If Stmt has an ID, assign its ID to LHS
-  CondIDs[CodeGenFunction::stripCond(E->getLHS())] = CondIDs[E];
-
-  // Since the operator's LHS assumes the operator's same ID, pop the
-  // operator from the RHS stack so that if LHS short-circuits, it won't be
-  // incorrectly re-used as the node executed next.
-  popRHSifTop(E);
-} else {
-  // Otherwise, assign ID+1 to LHS.
-  CondIDs[CodeGenFunction::stripCond(E->getLHS())] = NextID++;
-}
+// larger subtree.  In this case, assign that ID to its LHS node.  Its RHS
+// will receive a new ID below. Otherwise, assign ID+1 to LHS.
+if (CondIDs.contains(CodeGenFunction::stripCond(E)))
+  setCondID(E->getLHS(), getCondID(E));
+else
+  setCondID(E->getLHS(), NextID++);
+
+// Assign a ID+1 for the RHS.
+MCDCConditionID RHSid = NextID++;
+setCondID(E->getRHS(), RHSid);
+
+// Push the LHS decision IDs onto the DecisionStack.
+if (isLAnd(E))
+  DecisionStack.push_back({RHSid, ParentDecision.FalseID});
+else
+  DecisionStack.push_back({ParentDecision.TrueID, RHSid});
+  }
 
-// Assign ID+1 to RHS.
-CondIDs[CodeGenFunction::stripCond(E->getRHS())] = NextID++;
+  /// Pop and return the LHS Decision ({0,0} if not set).
+  DecisionIDPair pop() {
+assert(DecisionStack.size() >= 1);
 
-// Push ID of Stmt's RHS so that LHS nodes know about it
-pushRHS(E);
+if (!CGM.getCodeGenOpts().MCDCCoverage || NotMapped)
+  return DecisionStack.front();
+
+assert(DecisionStack.size() > 1);

chapuni wrote:

I found another place to hold the assertion. Overall I suggest holding two 
place (including this).

https://github.com/llvm/llvm-project/pull/78202
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[clang] [llvm] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -1847,30 +1850,18 @@ struct CounterCoverageMappingBuilder
 // Extract the Parent Region Counter.
 Counter ParentCnt = getRegion().getCounter();
 
-// Extract the MCDC condition IDs (returns 0 if not needed).
-MCDCConditionID NextOrID = MCDCBuilder.getNextLOrCondID();
-MCDCConditionID NextAndID = MCDCBuilder.getNextLAndCondID();
 MCDCConditionID LHSid = MCDCBuilder.getCondID(E->getLHS());
 MCDCConditionID RHSid = MCDCBuilder.getCondID(E->getRHS());
 
 // Create Branch Region around LHS condition.
-// MC/DC: For "LHS && RHS"
-// - If LHS is TRUE, execution goes to the RHS.
-// - If LHS is FALSE, execution goes to the LHS of the next logical-OR.
-//   If that does not exist, execution exits (ID == 0).
 createBranchRegion(E->getLHS(), RHSExecCnt,
-   subtractCounters(ParentCnt, RHSExecCnt), LHSid, RHSid,
-   NextOrID);
+   subtractCounters(ParentCnt, RHSExecCnt), LHSid,
+   DecisionLHS.TrueID, DecisionLHS.FalseID);

chapuni wrote:

They may be reduced to `const DecisionIDPair&` if its struct definition is move 
out of `MCDCCoverageBuilder`.

https://github.com/llvm/llvm-project/pull/78202
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[llvm] [clang] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread NAKAMURA Takumi via cfe-commits



@@ -730,68 +723,70 @@ struct MCDCCoverageBuilder {
   return;
 
 // If binary expression is disqualified, don't do mapping.
-if (NestLevel.empty() &&
-!MCDCBitmapMap.contains(CodeGenFunction::stripCond(E)))
+if (!isBuilding() && 
!MCDCBitmapMap.contains(CodeGenFunction::stripCond(E)))
   NotMapped = true;
 
-// Push Stmt on 'NestLevel' stack to keep track of nest location.
-NestLevel.push_back(E);
-
 // Don't go any further if we don't need to map condition IDs.
 if (NotMapped)
   return;
 
+assert(DecisionStack.size() >= 1);
+const DecisionIDPair  = DecisionStack.back();
+
 // If the operator itself has an assigned ID, this means it represents a
-// larger subtree.  In this case, pop its ID out of the RHS stack and
-// assign that ID to its LHS node.  Its RHS will receive a new ID.
-if (CondIDs.contains(CodeGenFunction::stripCond(E))) {
-  // If Stmt has an ID, assign its ID to LHS
-  CondIDs[CodeGenFunction::stripCond(E->getLHS())] = CondIDs[E];
-
-  // Since the operator's LHS assumes the operator's same ID, pop the
-  // operator from the RHS stack so that if LHS short-circuits, it won't be
-  // incorrectly re-used as the node executed next.
-  popRHSifTop(E);
-} else {
-  // Otherwise, assign ID+1 to LHS.
-  CondIDs[CodeGenFunction::stripCond(E->getLHS())] = NextID++;
-}
+// larger subtree.  In this case, assign that ID to its LHS node.  Its RHS
+// will receive a new ID below. Otherwise, assign ID+1 to LHS.
+if (CondIDs.contains(CodeGenFunction::stripCond(E)))
+  setCondID(E->getLHS(), getCondID(E));
+else
+  setCondID(E->getLHS(), NextID++);
+
+// Assign a ID+1 for the RHS.
+MCDCConditionID RHSid = NextID++;
+setCondID(E->getRHS(), RHSid);
+
+// Push the LHS decision IDs onto the DecisionStack.
+if (isLAnd(E))
+  DecisionStack.push_back({RHSid, ParentDecision.FalseID});
+else
+  DecisionStack.push_back({ParentDecision.TrueID, RHSid});
+  }
 
-// Assign ID+1 to RHS.
-CondIDs[CodeGenFunction::stripCond(E->getRHS())] = NextID++;
+  /// Pop and return the LHS Decision ({0,0} if not set).
+  DecisionIDPair pop() {
+assert(DecisionStack.size() >= 1);
 
-// Push ID of Stmt's RHS so that LHS nodes know about it
-pushRHS(E);
+if (!CGM.getCodeGenOpts().MCDCCoverage || NotMapped)
+  return DecisionStack.front();
+
+assert(DecisionStack.size() > 1);
+DecisionIDPair D = DecisionStack.back();
+DecisionStack.pop_back();
+return D;
   }
 
-  /// Pop the binary operator from the next level. If the walk is at the top of
-  /// the next, assign the total number of conditions.
-  unsigned popAndReturnCondCount(const BinaryOperator *E) {
+  /// Return the total number of conditions and reset the state. The number of
+  /// conditions is zero if the expression isn't mapped.
+  unsigned getTotalConditionsAndReset(const BinaryOperator *E) {
 if (!CGM.getCodeGenOpts().MCDCCoverage)
   return 0;
 
-unsigned TotalConds = 0;
-
-// Pop Stmt from 'NestLevel' stack.
-assert(NestLevel.back() == E);
-NestLevel.pop_back();
+assert(!isIdle());
+assert(DecisionStack.size() == 1);

chapuni wrote:

This is also better to hold, I think.

https://github.com/llvm/llvm-project/pull/78202
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[compiler-rt] [clang] [llvm] [X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (PR #78384)

2024-01-16 Thread Freddy Ye via cfe-commits



@@ -229,9 +230,9 @@ X86_FEATURE   (XSAVE,   "xsave")
 X86_FEATURE   (XSAVEC,  "xsavec")
 X86_FEATURE   (XSAVEOPT,"xsaveopt")
 X86_FEATURE   (XSAVES,  "xsaves")
+X86_FEATURE_COMPAT(AVX512FP16,  "avx512fp16",39)

FreddyLeaf wrote:

Sorry, I misunderstood before. c50fb21 updated. With this update, 
cpu_specific/dispatch can clarify sapphirerapids and cooperlake now.

https://github.com/llvm/llvm-project/pull/78384
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[clang] [clang][ExprConst] allow single element access of vector object to be constant expression (PR #72607)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -437,6 +442,16 @@ namespace {
   MostDerivedArraySize = 2;
   MostDerivedPathLength = Entries.size();
 }
+void addVectorUnchecked(QualType EltTy, uint64_t Size, uint64_t Idx) {
+  Entries.push_back(PathEntry::ArrayIndex(Idx));
+
+  // This is technically a most-derived object, though in practice this
+  // is unlikely to matter.
+  MostDerivedType = EltTy;
+  MostDerivedIsArrayElement = true;
+  MostDerivedArraySize = Size;

arsenm wrote:

I think accessing individual fields should be OK. Taking the address of a 
vector element feels wrong, but I haven't thought too deeply about it 

https://github.com/llvm/llvm-project/pull/72607
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[compiler-rt] [clang] [llvm] [X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (PR #78384)

2024-01-16 Thread Freddy Ye via cfe-commits


https://github.com/FreddyLeaf updated 
https://github.com/llvm/llvm-project/pull/78384

>From 04bbfad594054c2dab033b977c7dfa178fee8568 Mon Sep 17 00:00:00 2001
From: Freddy Ye 
Date: Thu, 4 Jan 2024 21:00:23 +0800
Subject: [PATCH 1/4] [X86] Support "f16c" and "avx512fp16" for
 __builtin_cpu_supports

This resolves issue #65320.
---
 compiler-rt/lib/builtins/cpu_model/x86.c   | 5 -
 llvm/include/llvm/TargetParser/X86TargetParser.def | 5 +++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c 
b/compiler-rt/lib/builtins/cpu_model/x86.c
index 9d9a5d3f1542cd..0750e29f989a8d 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -148,7 +148,8 @@ enum ProcessorFeatures {
   FEATURE_LZCNT,
   FEATURE_MOVBE,
 
-  FEATURE_X86_64_BASELINE = 95,
+  FEATURE_AVX512FP16 = 94,
+  FEATURE_X86_64_BASELINE,
   FEATURE_X86_64_V2,
   FEATURE_X86_64_V3,
   FEATURE_X86_64_V4,
@@ -812,6 +813,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned 
EDX, unsigned MaxLeaf,
 setFeature(FEATURE_AVX5124FMAPS);
   if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
 setFeature(FEATURE_AVX512VP2INTERSECT);
+  if (HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save)
+setFeature(FEATURE_AVX512FP16);
 
   // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
   // return all 0s for invalid subleaves so check the limit.
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def 
b/llvm/include/llvm/TargetParser/X86TargetParser.def
index b58feafe4e8c24..43162f2b52ebab 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -122,6 +122,7 @@ X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "gracemont")
 //
 // We cannot just re-sort the list though because its order is dictated by the
 // order of bits in CodeGenFunction::GetX86CpuSupportsMask.
+// We cannot re-adjust the position of X86_FEATURE_COMPAT at the whole list.
 #ifndef X86_FEATURE_COMPAT
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) X86_FEATURE(ENUM, STR)
 #endif
@@ -184,12 +185,12 @@ X86_FEATURE   (AMX_TILE,"amx-tile")
 X86_FEATURE   (CLDEMOTE,"cldemote")
 X86_FEATURE   (CLFLUSHOPT,  "clflushopt")
 X86_FEATURE   (CLWB,"clwb")
+X86_FEATURE_COMPAT(F16C,"f16c",  38)
 X86_FEATURE   (CLZERO,  "clzero")
 X86_FEATURE   (CMPXCHG16B,  "cx16")
 X86_FEATURE   (CMPXCHG8B,   "cx8")
 X86_FEATURE   (CRC32,   "crc32")
 X86_FEATURE   (ENQCMD,  "enqcmd")
-X86_FEATURE   (F16C,"f16c")
 X86_FEATURE   (FSGSBASE,"fsgsbase")
 X86_FEATURE   (FXSR,"fxsr")
 X86_FEATURE   (INVPCID, "invpcid")
@@ -229,9 +230,9 @@ X86_FEATURE   (XSAVE,   "xsave")
 X86_FEATURE   (XSAVEC,  "xsavec")
 X86_FEATURE   (XSAVEOPT,"xsaveopt")
 X86_FEATURE   (XSAVES,  "xsaves")
+X86_FEATURE_COMPAT(AVX512FP16,  "avx512fp16",39)
 X86_FEATURE   (HRESET,  "hreset")
 X86_FEATURE   (RAOINT,  "raoint")
-X86_FEATURE   (AVX512FP16,  "avx512fp16")
 X86_FEATURE   (AMX_FP16,"amx-fp16")
 X86_FEATURE   (CMPCCXADD,   "cmpccxadd")
 X86_FEATURE   (AVXNECONVERT,"avxneconvert")

>From 79bf68d976ef53d5a404cd9b7a0bd485c9937ba0 Mon Sep 17 00:00:00 2001
From: Freddy Ye 
Date: Wed, 17 Jan 2024 12:06:38 +0800
Subject: [PATCH 2/4] add test

---
 clang/test/CodeGen/target-builtin-noerror.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/clang/test/CodeGen/target-builtin-noerror.c 
b/clang/test/CodeGen/target-builtin-noerror.c
index 505f4a3e94565d..06bb40a2b71ea9 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -82,6 +82,8 @@ void verifyfeaturestrings(void) {
   (void)__builtin_cpu_supports("avx512bitalg");
   (void)__builtin_cpu_supports("avx512bf16");
   (void)__builtin_cpu_supports("avx512vp2intersect");
+  (void)__builtin_cpu_supports("f16c");
+  (void)__builtin_cpu_supports("avx512fp16");
 }
 
 void verifycpustrings(void) {

>From 400b00d4aaf4a11978dc5ddd58acc2a2cb36ed1f Mon Sep 17 00:00:00 2001
From: Freddy Ye 
Date: Wed, 17 Jan 2024 13:40:27 +0800
Subject: [PATCH 3/4] update lit test

---
 clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp 
b/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
index ef2498bd7e14ce..183eb4fb6ac61e 100644
--- a/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
+++ b/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
@@ -80,8 +80,8 @@ OutOfLineDefs::foo(int, int, int) {
 // LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEiii.S
 // LINUX: define dso_local noundef i32

[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

2024-01-16 Thread Craig Topper via cfe-commits



@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
 #endif /* __x86_64__ */
 
 #ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile 
+///
+/// This intrinsic corresponds to the \c PUSHFQ + \c POP instruction sequence.

topperc wrote:

I wrote that comment before I checked and meant to remove it before I approved. 
Sorry.

https://github.com/llvm/llvm-project/pull/77686
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[clang] [clang][docs] Improve "Obtaining Clang" section (PR #71313)

2024-01-16 Thread Robin Caloudis via cfe-commits


robincaloudis wrote:

@jrtc27, I do not have write access. All checks passed. Can you merge the PR? 
Thanks. 

https://github.com/llvm/llvm-project/pull/71313
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[clang] [X86_64] fix empty structure vaarg in c++ (PR #77907)

2024-01-16 Thread Phoebe Wang via cfe-commits


phoebewang wrote:

> I've revised it. Can you check it again? @phoebewang

I'm not sure the usage of the `isEmptyRecord`. Tagging @asb who modified the 
interface recently.

https://github.com/llvm/llvm-project/pull/77907
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[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Craig Topper via cfe-commits


https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/77426
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[clang] [lldb] [clang-tools-extra] [llvm] [flang] [lld] [compiler-rt] [libcxx] [libc] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -130,6 +130,8 @@
 ; GCN-O0-NEXT:MachineDominator Tree Construction
 ; GCN-O0-NEXT:Machine Natural Loop Construction
 ; GCN-O0-NEXT:MachinePostDominator Tree Construction
+; GCN-O0-NEXT:Basic Alias Analysis (stateless AA impl)
+; GCN-O0-NEXT:Function Alias Analysis Results

arsenm wrote:

You can check the opt level in getAnalysisUsage too, from the TargetMachine 

https://github.com/llvm/llvm-project/pull/74537
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[clang] [compiler-rt] [lld] [libc] [libcxx] [llvm] [clang-tools-extra] [lldb] [flang] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

2024-01-16 Thread Matt Arsenault via cfe-commits


https://github.com/arsenm approved this pull request.

lgtm, but can still fix the -O0 thing 

https://github.com/llvm/llvm-project/pull/74537
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[lldb] [llvm] [libcxx] [clang-tools-extra] [compiler-rt] [clang] [lld] [libc] [flang] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -707,7 +723,40 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
 (TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) {
   // MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS
   // written can be accessed. A load from LDS to VMEM does not need a wait.
-  setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, CurrScore);
+  unsigned Slot = 0;
+  for (const auto *MemOp : Inst.memoperands()) {
+if (!MemOp->isStore() ||
+MemOp->getAddrSpace() != AMDGPUAS::LOCAL_ADDRESS)
+  continue;
+// Comparing just AA info does not guarantee memoperands are equal
+// in general, but this is so for LDS DMA in practice.
+auto AAI = MemOp->getAAInfo();
+// Alias scope information gives a way to definitely identify an
+// original memory object and practically produced in the module LDS
+// lowering pass. If there is no scope available we will not be able
+// to disambiguate LDS aliasing as after the module lowering all LDS
+// is squashed into a single big object. Do not attemt to use one of

arsenm wrote:

Typo 'attemt'

https://github.com/llvm/llvm-project/pull/74537
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[libc] [clang] [compiler-rt] [clang-tools-extra] [lld] [lldb] [flang] [llvm] [libcxx] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

2024-01-16 Thread Matt Arsenault via cfe-commits


https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/74537
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[clang] [clang] Upstream XROS support in Clang (PR #78392)

2024-01-16 Thread Cyndy Ishida via cfe-commits


https://github.com/cyndyishida approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/78392
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[libc] [clang] [compiler-rt] [clang-tools-extra] [libcxxabi] [libunwind] [lldb] [mlir] [flang] [llvm] [libcxx] [ASan][AMDGPU] Fix Assertion Failure. (PR #78242)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -0,0 +1,48 @@
+;RUN: opt < %s -passes=asan -S | FileCheck %s
+
+target datalayout = 
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
+target triple = "amdgcn-amd-amdhsa"
+
+@__const.__assert_fail.fmt = private unnamed_addr addrspace(4) constant [47 x 
i8] c"%s:%u: %s: Device-side assertion `%s' failed.\0A\00", align 16
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: 
readwrite)
+declare void @llvm.memcpy.p0.p4.i64(ptr noalias nocapture writeonly, ptr 
addrspace(4) noalias nocapture readonly, i64, i1 immarg) #1
+
+; Function Attrs: convergent mustprogress noinline nounwind optnone
+define weak hidden void @test_mem_intrinsic() sanitize_address #0 {
+; CHECK: define weak hidden void @test_mem_intrinsic() #1 {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[FMT:%.*]] = alloca [47 x i8], align 16, addrspace(5)
+; CHECK-NEXT: [[FADDRC:%.*]] = addrspacecast ptr addrspace(5) [[FMT]] to ptr
+; CHECK-NEXT: [[ITMP:%.*]] = call ptr @__asan_memcpy(ptr [[FADDRC]], ptr 
addrspacecast (ptr addrspace(4) @__const.__assert_fail.fmt to ptr), i64 47)
+; CHECK-NEXT: ret
+entry:
+%fmt = alloca [47 x i8], align 16, addrspace(5)
+%fmt.ascast = addrspacecast ptr addrspace(5) %fmt to ptr
+call void @llvm.memcpy.p0.p4.i64(ptr align 16 %fmt.ascast, ptr addrspace(4) 
align 16 @__const.__assert_fail.fmt, i64 47, i1 false)
+ret void
+}
+
+
+
+attributes #0 = { convergent mustprogress noinline nounwind optnone 
"frame-pointer"="all" "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" "target-cpu"="gfx906" 
"target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64,+xnack"
 }
+attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: 
readwrite) }
+attributes #2 = { convergent nounwind "frame-pointer"="all" 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-cpu"="gfx906" 
"target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64,+xnack"
 }
+attributes #3 = { cold noreturn nounwind memory(inaccessiblemem: write) }
+attributes #4 = { convergent mustprogress noinline norecurse nounwind optnone 
"amdgpu-flat-work-group-size"="1,1024" "frame-pointer"="all" 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-cpu"="gfx906" 
"target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64,+xnack"
 "uniform-work-group-size"="true" }
+attributes #5 = { convergent nounwind }
+
+!llvm.module.flags = !{!0, !1, !2, !3, !4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 400}

arsenm wrote:

Don't need most of this metadata or most of the attributes 

https://github.com/llvm/llvm-project/pull/78242
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[libc] [clang] [compiler-rt] [clang-tools-extra] [libcxxabi] [libunwind] [lldb] [mlir] [flang] [llvm] [libcxx] [ASan][AMDGPU] Fix Assertion Failure. (PR #78242)

2024-01-16 Thread via cfe-commits


https://github.com/ampandey-1995 updated 
https://github.com/llvm/llvm-project/pull/78242

>From fe6d4abebb12e063e10b2266f76ff1a604783c0c Mon Sep 17 00:00:00 2001
From: Amit Pandey 
Date: Mon, 11 Dec 2023 14:23:44 +0530
Subject: [PATCH] [ASan][AMDGPU] Fix Assertion Failure.

Assertion failure `(i >= FTy->getNumParams() || FTy->getParamType(i) ==
Args[i]->getType()) && "Calling a function with a bad signature!"'.  The
'llvm.memcpy' intercepted by ASan instrumentation pass is implemented by it's
own __asan_memcpy implementation. The second argument of llvm.memcpy accepts ptr
to addrspace(4), __asan_memcpy also has to follow ptr to addrspace(4)
convention.
---
 .../Instrumentation/AddressSanitizer.cpp  |  8 ++--
 .../AMDGPU/asan_instrument_mem_intrinsics.ll  | 48 +++
 2 files changed, 53 insertions(+), 3 deletions(-)
 create mode 100644 
llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll

diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index fb5838bb7941ad..32e7f1b6fc3374 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -1254,9 +1254,11 @@ Value *AddressSanitizer::memToShadow(Value *Shadow, 
IRBuilder<> ) {
 void AddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) {
   InstrumentationIRBuilder IRB(MI);
   if (isa(MI)) {
-IRB.CreateCall(isa(MI) ? AsanMemmove : AsanMemcpy,
-   {MI->getOperand(0), MI->getOperand(1),
-IRB.CreateIntCast(MI->getOperand(2), IntptrTy, false)});
+IRB.CreateCall(
+isa(MI) ? AsanMemmove : AsanMemcpy,
+{MI->getOperand(0),
+ IRB.CreatePointerBitCastOrAddrSpaceCast(MI->getOperand(1), PtrTy),
+ IRB.CreateIntCast(MI->getOperand(2), IntptrTy, false)});
   } else if (isa(MI)) {
 IRB.CreateCall(
 AsanMemset,
diff --git 
a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
 
b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
new file mode 100644
index 00..26258ef384795d
--- /dev/null
+++ 
b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
@@ -0,0 +1,48 @@
+;RUN: opt < %s -passes=asan -S | FileCheck %s
+
+target datalayout = 
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
+target triple = "amdgcn-amd-amdhsa"
+
+@__const.__assert_fail.fmt = private unnamed_addr addrspace(4) constant [47 x 
i8] c"%s:%u: %s: Device-side assertion `%s' failed.\0A\00", align 16
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: 
readwrite)
+declare void @llvm.memcpy.p0.p4.i64(ptr noalias nocapture writeonly, ptr 
addrspace(4) noalias nocapture readonly, i64, i1 immarg) #1
+
+; Function Attrs: convergent mustprogress noinline nounwind optnone
+define weak hidden void @test_mem_intrinsic() sanitize_address #0 {
+; CHECK: define weak hidden void @test_mem_intrinsic() #1 {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[FMT:%.*]] = alloca [47 x i8], align 16, addrspace(5)
+; CHECK-NEXT: [[FADDRC:%.*]] = addrspacecast ptr addrspace(5) [[FMT]] to ptr
+; CHECK-NEXT: [[ITMP:%.*]] = call ptr @__asan_memcpy(ptr [[FADDRC]], ptr 
addrspacecast (ptr addrspace(4) @__const.__assert_fail.fmt to ptr), i64 47)
+; CHECK-NEXT: ret
+entry:
+%fmt = alloca [47 x i8], align 16, addrspace(5)
+%fmt.ascast = addrspacecast ptr addrspace(5) %fmt to ptr
+call void @llvm.memcpy.p0.p4.i64(ptr align 16 %fmt.ascast, ptr addrspace(4) 
align 16 @__const.__assert_fail.fmt, i64 47, i1 false)
+ret void
+}
+
+
+
+attributes #0 = { convergent mustprogress noinline nounwind optnone 
"frame-pointer"="all" "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" "target-cpu"="gfx906" 
"target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64,+xnack"
 }
+attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: 
readwrite) }
+attributes #2 = { convergent nounwind "frame-pointer"="all" 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-cpu"="gfx906" 
"target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64,+xnack"
 }
+attributes #3 = { cold noreturn nounwind memory(inaccessiblemem: write) }
+attributes #4 = { convergent mustprogress noinline norecurse nounwind optnone 
"amdgpu-flat-work-group-size"="1,1024" "frame-pointer"="all" 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-cpu"="gfx906"

[clang-tools-extra] Add clang-tidy check to suggest replacement of conditional statement with std::min/std::max (PR #77816)

2024-01-16 Thread Félix-Antoine Constantin via cfe-commits

felix642 wrote:

@11happy what are you trying to achieve exactly and what is not working ? 
Is this related to the example that you provided above? 

>``` 
>auto lhsVar1Str = Lexer::getSourceText( 
>>CharSourceRange::getTokenRange(Source.getSpellingLoc(lhsVar1->getBeginLoc()),Source.getSpellingLoc(lhsVar1->getEn>dLoc())),
>  Context.getSourceManager(), Context.getLangOpts());
>```
>it outputs this :
>```
 >//
>-  if (MY_MIN(value1, value2) < value3)
>-value3 = MY_MIN(value1, value2); //
>+  value3 = std::min((a) < (b) ? (a) : (b), value3); //
> }
>```

If that's the case I'm guessing that you simply forgot to update the begin and 
end location of the if/then stmt with the spelling loc ?  

Regarding the request for a test case with macros, my intention was to 
understand how your check handles them. I believe updating a macro is risk 
free, but there might be use cases that I'm overlooking.
 One potential issue could arise if someone is using the macro in another 
translation unit without directly importing it. In that case, updating the 
macro without the necessary include might cause compilation failures. However, 
I'm unsure if this is a use case that needs consideration.

It might be worth to look if other checks are currently updating macros. This 
might be a decent indicator of the risk of doing so (If a few checks are 
already doing it then I might be overthinking it). Also, @PiotrZSL might be 
able to give us some insight on this since he has more experience with 
clang-tidy.

https://github.com/llvm/llvm-project/pull/77816
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[clang] 4e64159 - [Clang] Implement CWG2598: Union of non-literal types (#78195)

2024-01-16 Thread via cfe-commits


Author: cor3ntin
Date: 2024-01-17T06:16:12+01:00
New Revision: 4e64159c866446ed7f5783649f8f5699f84bb1a6

URL: 
https://github.com/llvm/llvm-project/commit/4e64159c866446ed7f5783649f8f5699f84bb1a6
DIFF: 
https://github.com/llvm/llvm-project/commit/4e64159c866446ed7f5783649f8f5699f84bb1a6.diff

LOG: [Clang] Implement CWG2598: Union of non-literal types (#78195)

A union is considered a literal type unless it has no non-literal
member.

This resolves CWG2096 (which makes unions with literal members literal)
and CWG2598 (empty unions are literal types).

Fixes #77924

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
clang/include/clang/AST/DeclCXX.h
clang/lib/AST/DeclCXX.cpp
clang/test/CXX/drs/dr20xx.cpp
clang/test/CXX/drs/dr25xx.cpp
clang/test/SemaCXX/literal-type.cpp
clang/www/cxx_dr_status.html

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1eba8ab5590c52..e45e016b3d66bd 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -227,6 +227,11 @@ C++2c Feature Support
 Resolutions to C++ Defect Reports
 ^
 
+- Implemented `CWG2598 `_ and `CWG2096 
`_,
+  making unions (that have either no members or at least one literal member) 
literal types.
+  (`#77924: `_).
+
+
 C Language Changes
 --
 - ``structs``, ``unions``, and ``arrays`` that are const may now be used as

diff  --git a/clang/include/clang/AST/DeclCXX.h 
b/clang/include/clang/AST/DeclCXX.h
index 648f5f94640870..75b73700c44d67 100644
--- a/clang/include/clang/AST/DeclCXX.h
+++ b/clang/include/clang/AST/DeclCXX.h
@@ -1439,31 +1439,20 @@ class CXXRecordDecl : public RecordDecl {
 
   /// Determine whether this class is a literal type.
   ///
-  /// C++11 [basic.types]p10:
+  /// C++20 [basic.types]p10:
   ///   A class type that has all the following properties:
-  /// - it has a trivial destructor
-  /// - every constructor call and full-expression in the
-  ///   brace-or-equal-intializers for non-static data members (if any) is
-  ///   a constant expression.
-  /// - it is an aggregate type or has at least one constexpr constructor
-  ///   or constructor template that is not a copy or move constructor, and
-  /// - all of its non-static data members and base classes are of literal
-  ///   types
-  ///
-  /// We resolve DR1361 by ignoring the second bullet. We resolve DR1452 by
-  /// treating types with trivial default constructors as literal types.
-  ///
-  /// Only in C++17 and beyond, are lambdas literal types.
-  bool isLiteral() const {
-const LangOptions  = getLangOpts();
-return (LangOpts.CPlusPlus20 ? hasConstexprDestructor()
-  : hasTrivialDestructor()) &&
-   (!isLambda() || LangOpts.CPlusPlus17) &&
-   !hasNonLiteralTypeFieldsOrBases() &&
-   (isAggregate() || isLambda() ||
-hasConstexprNonCopyMoveConstructor() ||
-hasTrivialDefaultConstructor());
-  }
+  /// - it has a constexpr destructor
+  /// - all of its non-static non-variant data members and base classes
+  ///   are of non-volatile literal types, and it:
+  ///- is a closure type
+  ///- is an aggregate union type that has either no variant members
+  ///  or at least one variant member of non-volatile literal type
+  ///- is a non-union aggregate type for which each of its anonymous
+  ///  union members satisfies the above requirements for an aggregate
+  ///  union type, or
+  ///- has at least one constexpr constructor or constructor template
+  ///  that is not a copy or move constructor.
+  bool isLiteral() const;
 
   /// Determine whether this is a structural type.
   bool isStructural() const {

diff  --git a/clang/lib/AST/DeclCXX.cpp b/clang/lib/AST/DeclCXX.cpp
index 98b0a6dc28ea2f..c11f6458c07dde 100644
--- a/clang/lib/AST/DeclCXX.cpp
+++ b/clang/lib/AST/DeclCXX.cpp
@@ -1383,6 +1383,31 @@ void CXXRecordDecl::addedMember(Decl *D) {
   }
 }
 
+bool CXXRecordDecl::isLiteral() const {
+  const LangOptions  = getLangOpts();
+  if (!(LangOpts.CPlusPlus20 ? hasConstexprDestructor()
+ : hasTrivialDestructor()))
+return false;
+
+  if (hasNonLiteralTypeFieldsOrBases()) {
+// CWG2598
+// is an aggregate union type that has either no variant
+// members or at least one variant member of non-volatile literal type,
+if (!isUnion())
+  return false;
+bool HasAtLeastOneLiteralMember =
+fields().empty() || any_of(fields(), [this](const FieldDecl *D) {
+  return !D->getType().isVolatileQualified() &&
+ D->getType()->isLiteralType(getASTContext());
+});
+

[clang] [Clang] Implement CWG2598: Union of non-literal types (PR #78195)

2024-01-16 Thread via cfe-commits


https://github.com/cor3ntin closed 
https://github.com/llvm/llvm-project/pull/78195
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[clang] [Clang][Sema] improve sema check of clang::musttail attribute (PR #77727)

2024-01-16 Thread Qizhi Hu via cfe-commits


https://github.com/jcsxky updated 
https://github.com/llvm/llvm-project/pull/77727

>From 67396b51f45f36391bbcf47d1d4cae9274d18526 Mon Sep 17 00:00:00 2001
From: huqizhi 
Date: Thu, 11 Jan 2024 13:02:21 +0800
Subject: [PATCH] [Clang][SemaCXX] improve sema check of clang::musttail
 attribute

---
 clang/docs/ReleaseNotes.rst  | 3 +++
 clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 ++
 clang/lib/Sema/SemaStmt.cpp  | 6 ++
 clang/test/SemaCXX/PR76631.cpp   | 9 +
 4 files changed, 20 insertions(+)
 create mode 100644 clang/test/SemaCXX/PR76631.cpp

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1eba8ab5590c52..db7a14eda0808c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -760,6 +760,9 @@ Bug Fixes in This Version
   Fixes (`#77583 `_)
 - Fix an issue where CTAD fails for function-type/array-type arguments.
   Fixes (`#51710 `_)
+- Fix assertion failure when call noreturn-attribute function with musttail
+  attribute.
+  Fixes (`#76631 `_)
 
 Bug Fixes to Compiler Builtins
 ^^
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 991c72cad33cad..03b0122d1c08f7 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -3113,6 +3113,8 @@ def err_musttail_scope : Error<
   "cannot perform a tail call from this return statement">;
 def err_musttail_no_variadic : Error<
   "%0 attribute may not be used with variadic functions">;
+def err_musttail_no_return : Error<
+  "%0 attribute may not be used with no-return-attribute functions">;
 
 def err_nsobject_attribute : Error<
   "'NSObject' attribute is for pointer types only">;
diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp
index 21efe25ed84a3d..9e7c8c7e4e8c12 100644
--- a/clang/lib/Sema/SemaStmt.cpp
+++ b/clang/lib/Sema/SemaStmt.cpp
@@ -786,6 +786,12 @@ bool Sema::checkMustTailAttr(const Stmt *St, const Attr 
) {
 return false;
   }
 
+  const auto *CalleeDecl = CE->getCalleeDecl();
+  if (CalleeDecl && CalleeDecl->hasAttr()) {
+Diag(St->getBeginLoc(), diag::err_musttail_no_return) << 
+return false;
+  }
+
   // Caller and callee must match in whether they have a "this" parameter.
   if (CallerType.This.isNull() != CalleeType.This.isNull()) {
 if (const auto *ND = dyn_cast_or_null(CE->getCalleeDecl())) {
diff --git a/clang/test/SemaCXX/PR76631.cpp b/clang/test/SemaCXX/PR76631.cpp
new file mode 100644
index 00..947fa3fc2635e6
--- /dev/null
+++ b/clang/test/SemaCXX/PR76631.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -verify -std=c++11 -fsyntax-only %s
+
+[[noreturn]] void throw_int() {
+  throw int(); // expected-error {{cannot use 'throw' with exceptions 
disabled}}
+}
+
+void throw_int_wrapper() {
+  [[clang::musttail]] return throw_int(); // expected-error {{'musttail' 
attribute may not be used with no-return-attribute functions}}
+}

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[llvm] [clang] [LinkerWrapper] Handle AMDGPU Target-IDs correctly when linking (PR #78359)

2024-01-16 Thread Matt Arsenault via cfe-commits



@@ -162,6 +162,19 @@ class OffloadFile : public OwningBinary {
   std::unique_ptr Buffer)
   : OwningBinary(std::move(Binary), std::move(Buffer)) {}
 
+  /// Make a deep copy of this offloading file.
+  OffloadFile copy() const {
+std::unique_ptr Buffer = MemoryBuffer::getMemBufferCopy(
+getBinary()->getMemoryBufferRef().getBuffer());
+
+// This parsing should never fail because it has already been parsed.
+auto NewBinaryOrErr = OffloadBinary::create(*Buffer);
+assert(NewBinaryOrErr && "Failed to parse a copy of the binary?");
+if (!NewBinaryOrErr)

arsenm wrote:

Assert + error handling = ???

https://github.com/llvm/llvm-project/pull/78359
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[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

2024-01-16 Thread Kishan Parmar via cfe-commits


https://github.com/Long5hot updated 
https://github.com/llvm/llvm-project/pull/77732

>From ec05087b89af829247879c2e860f9d93f548c7a1 Mon Sep 17 00:00:00 2001
From: Kishan Parmar 
Date: Wed, 17 Jan 2024 10:29:34 +0530
Subject: [PATCH] [clang][PowerPC] Add flag to enable compatibility with GNU
 for complex arguments

Fixes : https://github.com/llvm/llvm-project/issues/56023

https://godbolt.org/z/1bsW1sKMs

newFlag : -fcomplex-ppc-gnu-abi

GNU uses GPRs for complex parameters and return values storing for 
PowerPC-32bit,
which can be enabled which above flag.
Intent of this patch is to make clang compatible with GNU libraries of complex.
---
 clang/include/clang/Basic/CodeGenOptions.def  |   2 +
 clang/include/clang/Basic/CodeGenOptions.h|   7 +
 clang/include/clang/Driver/Options.td |   4 +
 clang/lib/CodeGen/CodeGenModule.cpp   |   6 +-
 clang/lib/CodeGen/TargetInfo.h|   3 +-
 clang/lib/CodeGen/Targets/PPC.cpp | 110 +--
 clang/lib/Driver/ToolChains/Clang.cpp |   9 ++
 clang/lib/Frontend/CompilerInvocation.cpp |   8 ++
 .../CodeGen/PowerPC/ppc32-complex-gnu-abi.c   | 132 ++
 9 files changed, 266 insertions(+), 15 deletions(-)
 create mode 100644 clang/test/CodeGen/PowerPC/ppc32-complex-gnu-abi.c

diff --git a/clang/include/clang/Basic/CodeGenOptions.def 
b/clang/include/clang/Basic/CodeGenOptions.def
index 2c4fb6745bc172f..beeefae15c63f82 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -213,6 +213,8 @@ CODEGENOPT(MCDCCoverage , 1, 0) ///< Enable MC/DC code 
coverage criteria.
 
   /// If -fpcc-struct-return or -freg-struct-return is specified.
 ENUM_CODEGENOPT(StructReturnConvention, StructReturnConventionKind, 2, 
SRCK_Default)
+  /// If -fcomplex-ppc-gnu-abi for ppc32
+ENUM_CODEGENOPT(ComplexInRegABI, ComplexArgumentConventionKind, 2, 
CMPLX_Default)
 
 CODEGENOPT(RelaxAll  , 1, 0) ///< Relax all machine code instructions.
 CODEGENOPT(RelaxedAliasing   , 1, 0) ///< Set when -fno-strict-aliasing is 
enabled.
diff --git a/clang/include/clang/Basic/CodeGenOptions.h 
b/clang/include/clang/Basic/CodeGenOptions.h
index 6952b48e898a819..8abca0e3dda3343 100644
--- a/clang/include/clang/Basic/CodeGenOptions.h
+++ b/clang/include/clang/Basic/CodeGenOptions.h
@@ -78,6 +78,13 @@ class CodeGenOptions : public CodeGenOptionsBase {
 SRCK_InRegs// Small structs in registers (-freg-struct-return).
   };
 
+  enum ComplexArgumentConventionKind {
+CMPLX_Default,
+CMPLX_OnStack,
+CMPLX_OnGPR, // if ppc32 -fcomplex-ppc-gnu-abi
+CMPLX_OnFPR
+  };
+
   enum ProfileInstrKind {
 ProfileNone,   // Profile instrumentation is turned off.
 ProfileClangInstr, // Clang instrumentation to generate execution counts
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index a4a988c71ec412c..10166757b1352ed 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2540,6 +2540,10 @@ def ffp_contract : Joined<["-"], "ffp-contract=">, 
Group,
   HelpText<"Form fused FP ops (e.g. FMAs)">,
   Values<"fast,on,off,fast-honor-pragmas">;
 
+def fcomplex_ppc_gnu_abi : Flag<["-"], "fcomplex-ppc-gnu-abi">, 
Group, Visibility<[ClangOption, CC1Option]>,
+  DocBrief<"Follow the GNU ABI, store Complex values in GPR instead of stack 
for PowerPC-32">,
+  HelpText<"Store Complex values in GPR instead of stack for PowerPC-32">;
+
 defm strict_float_cast_overflow : BoolFOption<"strict-float-cast-overflow",
   CodeGenOpts<"StrictFloatCastOverflow">, DefaultTrue,
   NegFlag
 createAIXTargetCodeGenInfo(CodeGenModule , bool Is64Bit);
 
 std::unique_ptr
-createPPC32TargetCodeGenInfo(CodeGenModule , bool SoftFloatABI);
+createPPC32TargetCodeGenInfo(CodeGenModule , bool SoftFloatABI,
+ unsigned RLen);
 
 std::unique_ptr
 createPPC64TargetCodeGenInfo(CodeGenModule );
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp 
b/clang/lib/CodeGen/Targets/PPC.cpp
index 40e508c1772..f514f2e25a48f92 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -271,22 +271,33 @@ namespace {
 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
   bool IsSoftFloatABI;
   bool IsRetSmallStructInRegABI;
+  bool isComplexInRegABI;
+  // Size of GPR in bits
+  unsigned RLen;
+  static const int NumArgGPRs = 8;
 
   CharUnits getParamTypeAlignment(QualType Ty) const;
+  ABIArgInfo handleComplex(QualType Ty, uint64_t ) const;
 
 public:
   PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes , bool SoftFloatABI,
- bool RetSmallStructInRegABI)
+ bool RetSmallStructInRegABI, unsigned RLen,
+ bool ComplexInRegABI)
   : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
-IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
+IsRetSmallStructInRegABI(RetSmallStructInRegABI),
+

[libc] [clang] [compiler-rt] [clang-tools-extra] [libcxxabi] [flang] [lldb] [lld] [llvm] [libcxx] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2024-01-16 Thread Fangrui Song via cfe-commits


https://github.com/MaskRay edited 
https://github.com/llvm/llvm-project/pull/66915
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[clang] [Clang][Sema] fix crash of attribute transform (PR #78088)

2024-01-16 Thread Qizhi Hu via cfe-commits



@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+template
+struct Bar {
+int* data;
+
+auto operator[](const int index) const [[clang::lifetimebound]] -> 
decltype(data[index]) {
+return data[index];
+}
+};
+
+int main() {
+Bar b;
+(void)b[2];
+}

jcsxky wrote:

Done

https://github.com/llvm/llvm-project/pull/78088
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[libcxx] [clang-tools-extra] [libcxxabi] [compiler-rt] [clang] [lldb] [lld] [flang] [llvm] [libc] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2024-01-16 Thread Fangrui Song via cfe-commits


https://github.com/MaskRay approved this pull request.

LGTM once the TLSDESC option is moved to use llvm/lib/CodeGen/CommandFlags.cpp

It's worth giving others some time to respond.

https://github.com/llvm/llvm-project/pull/66915
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[clang] [Clang][Sema] fix crash of attribute transform (PR #78088)

2024-01-16 Thread Qizhi Hu via cfe-commits


https://github.com/jcsxky updated 
https://github.com/llvm/llvm-project/pull/78088

>From 55b433e5bad38b2ce359c480066b1b8c2917ebbf Mon Sep 17 00:00:00 2001
From: huqizhi 
Date: Sun, 14 Jan 2024 15:07:26 +0800
Subject: [PATCH] [Clang][Sema] fix crash of attribute transform

---
 clang/include/clang/AST/TypeLoc.h   |  4 
 clang/lib/Sema/TreeTransform.h  | 14 +-
 clang/test/Sema/attr-lifetimebound-no-crash.cpp | 17 +
 3 files changed, 30 insertions(+), 5 deletions(-)
 create mode 100644 clang/test/Sema/attr-lifetimebound-no-crash.cpp

diff --git a/clang/include/clang/AST/TypeLoc.h 
b/clang/include/clang/AST/TypeLoc.h
index 471deb14aba51f..04780fdeae3bc1 100644
--- a/clang/include/clang/AST/TypeLoc.h
+++ b/clang/include/clang/AST/TypeLoc.h
@@ -884,6 +884,10 @@ class AttributedTypeLoc : public 
ConcreteTypeLocgetEquivalentType(), getNonLocalData());
+  }
+
   /// The type attribute.
   const Attr *getAttr() const {
 return getLocalData()->TypeAttr;
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 1a1bc87d2b3203..c8653017a034e7 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -6124,7 +6124,11 @@ QualType 
TreeTransform::TransformFunctionProtoType(
   //   "pointer to cv-qualifier-seq X" between the optional cv-qualifer-seq
   //   and the end of the function-definition, member-declarator, or
   //   declarator.
-  Sema::CXXThisScopeRAII ThisScope(SemaRef, ThisContext, ThisTypeQuals);
+  auto *RD =
+  dyn_cast_or_null(SemaRef.getCurLexicalContext());
+  Sema::CXXThisScopeRAII ThisScope(
+  SemaRef, ThisContext == nullptr && nullptr != RD ? RD : ThisContext,
+  ThisTypeQuals);
 
   ResultType = getDerived().TransformType(TLB, TL.getReturnLoc());
   if (ResultType.isNull())
@@ -7081,10 +7085,10 @@ QualType 
TreeTransform::TransformAttributedType(
   // FIXME: dependent operand expressions?
   if (getDerived().AlwaysRebuild() ||
   modifiedType != oldType->getModifiedType()) {
-// TODO: this is really lame; we should really be rebuilding the
-// equivalent type from first principles.
-QualType equivalentType
-  = getDerived().TransformType(oldType->getEquivalentType());
+TypeLocBuilder AuxiliaryTLB;
+AuxiliaryTLB.reserve(TL.getFullDataSize());
+QualType equivalentType =
+getDerived().TransformType(AuxiliaryTLB, TL.getEquivalentTypeLoc());
 if (equivalentType.isNull())
   return QualType();
 
diff --git a/clang/test/Sema/attr-lifetimebound-no-crash.cpp 
b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
new file mode 100644
index 00..e668a78790defd
--- /dev/null
+++ b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+template
+struct Bar {
+int* data;
+
+auto operator[](const int index) const [[clang::lifetimebound]] -> 
decltype(data[index]) {
+return data[index];
+}
+};
+
+int main() {
+Bar b;
+(void)b[2];
+}

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[libc] [clang] [compiler-rt] [clang-tools-extra] [libcxxabi] [flang] [lldb] [lld] [llvm] [libcxx] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2024-01-16 Thread Fangrui Song via cfe-commits



@@ -80,6 +80,11 @@ static cl::opt EnableRISCVDeadRegisterElimination(
  " them with stores to x0"),
 cl::init(true));
 
+// TODO: This should be controlled by -mtls-dialect=
+cl::opt EnableRISCVTLSDESC("riscv-enable-tlsdesc",

MaskRay wrote:

We should add an option to `codegen::InitTargetOptionsFromCodeGenFlags`, then 
reference it using something like `DAG.getTarget().useTLSDESC()`. aarch64 ELF 
only implements TLSDESC for dynamic TLS models, it is fine for it to ignore 
`useTLSDESC`.

https://github.com/llvm/llvm-project/pull/66915
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[clang] [clang][Interp] IndirectMember initializers (PR #69900)

2024-01-16 Thread Timm Baeder via cfe-commits

Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= ,
Timm =?utf-8?q?Bäder?= 
Message-ID:
In-Reply-To: 


https://github.com/tbaederr updated 
https://github.com/llvm/llvm-project/pull/69900

>From 58ff884a20816526ea1b3e4035a65ab435e2396d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timm=20B=C3=A4der?= 
Date: Sun, 22 Oct 2023 19:47:33 +0200
Subject: [PATCH 1/5] [clang][Interp] IndirectMember initializers

---
 clang/lib/AST/Interp/ByteCodeStmtGen.cpp | 67 
 clang/lib/AST/Interp/Interp.h|  7 ++-
 clang/lib/AST/Interp/Opcodes.td  |  6 ++-
 clang/test/AST/Interp/records.cpp| 60 +
 4 files changed, 114 insertions(+), 26 deletions(-)

diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp 
b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp
index b1ab5fcf9cb64c..7dca7c902b1c79 100644
--- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp
+++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp
@@ -142,6 +142,27 @@ bool ByteCodeStmtGen::visitFunc(const 
FunctionDecl *F) {
   // Classify the return type.
   ReturnType = this->classify(F->getReturnType());
 
+  auto emitFieldInitializer = [&](const Record::Field *F, unsigned FieldOffset,
+  const Expr *InitExpr) -> bool {
+if (std::optional T = this->classify(InitExpr)) {
+  if (!this->visit(InitExpr))
+return false;
+
+  if (F->isBitField())
+return this->emitInitThisBitField(*T, F, FieldOffset, InitExpr);
+  return this->emitInitThisField(*T, FieldOffset, InitExpr);
+}
+// Non-primitive case. Get a pointer to the field-to-initialize
+// on the stack and call visitInitialzer() for it.
+if (!this->emitGetPtrThisField(FieldOffset, InitExpr))
+  return false;
+
+if (!this->visitInitializer(InitExpr))
+  return false;
+
+return this->emitPopPtr(InitExpr);
+  };
+
   // Emit custom code if this is a lambda static invoker.
   if (const auto *MD = dyn_cast(F);
   MD && MD->isLambdaStaticInvoker())
@@ -162,29 +183,8 @@ bool ByteCodeStmtGen::visitFunc(const 
FunctionDecl *F) {
   if (const FieldDecl *Member = Init->getMember()) {
 const Record::Field *F = R->getField(Member);
 
-if (std::optional T = this->classify(InitExpr)) {
-  if (!this->visit(InitExpr))
-return false;
-
-  if (F->isBitField()) {
-if (!this->emitInitThisBitField(*T, F, InitExpr))
-  return false;
-  } else {
-if (!this->emitInitThisField(*T, F->Offset, InitExpr))
-  return false;
-  }
-} else {
-  // Non-primitive case. Get a pointer to the field-to-initialize
-  // on the stack and call visitInitialzer() for it.
-  if (!this->emitGetPtrThisField(F->Offset, InitExpr))
-return false;
-
-  if (!this->visitInitializer(InitExpr))
-return false;
-
-  if (!this->emitPopPtr(InitExpr))
-return false;
-}
+if (!emitFieldInitializer(F, F->Offset, InitExpr))
+  return false;
   } else if (const Type *Base = Init->getBaseClass()) {
 // Base class initializer.
 // Get This Base and call initializer on it.
@@ -198,6 +198,27 @@ bool ByteCodeStmtGen::visitFunc(const 
FunctionDecl *F) {
   return false;
 if (!this->emitInitPtrPop(InitExpr))
   return false;
+  } else if (const IndirectFieldDecl *IFD = Init->getIndirectMember()) {
+assert(IFD->getChainingSize() >= 2);
+
+unsigned NestedFieldOffset = 0;
+const Record::Field *NestedField = nullptr;
+for (const NamedDecl *ND : IFD->chain()) {
+  // FIXME: Can this *not* be a FieldDecl?
+  const FieldDecl *FD = cast(ND);
+  const Record *FieldRecord =
+  this->P.getOrCreateRecord(FD->getParent());
+  assert(FieldRecord);
+
+  NestedField = FieldRecord->getField(FD);
+  assert(NestedField);
+
+  NestedFieldOffset += NestedField->Offset;
+}
+assert(NestedField);
+
+if (!emitFieldInitializer(NestedField, NestedFieldOffset, InitExpr))
+  return false;
   } else {
 assert(Init->isDelegatingInitializer());
 if (!this->emitThis(InitExpr))
diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h
index dbbc4c09ce42a1..5321f9617feff2 100644
--- a/clang/lib/AST/Interp/Interp.h
+++ b/clang/lib/AST/Interp/Interp.h
@@ -1078,15 +1078,18 @@ bool InitThisField(InterpState , CodePtr OpPC, 
uint32_t I) {
   return true;
 }
 
+// FIXME: The Field pointer here is too much IMO and we could instead just
+// pass an Offset + BitWidth pair.
 template ::T>
-bool InitThisBitField(InterpState , CodePtr OpPC, const Record::Field *F) {
+bool InitThisBitField(InterpState , CodePtr OpPC, const Record::Field *F,
+  uint32_t FieldOffset) {
   assert(F->isBitField());
   if

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Luke Lau via cfe-commits


https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77426

>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/4] [RISCV] Overwrite cpu target features for full arch
 string in target attribute

This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)

When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.

In initFeatureMap, there are now two code paths:

1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.

Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.

2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
---
 clang/lib/Basic/Targets/RISCV.cpp | 78 +++
 .../CodeGen/RISCV/riscv-func-attr-target.c|  8 +-
 2 files changed, 30 insertions(+), 56 deletions(-)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..b56c1d465ad77a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,39 +235,6 @@ ArrayRef 
RISCVTargetInfo::getTargetBuiltins() const {
 clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
 }
 
-static std::vector
-collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
-  std::vector NonISAExtFeatureVec;
-
-  auto IsNonISAExtFeature = [](const std::string ) {
-assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
-StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
-return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
-  };
-  llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-IsNonISAExtFeature);
-
-  return NonISAExtFeatureVec;
-}
-
-static std::vector
-resolveTargetAttrOverride(const std::vector ,
-  int XLen) {
-  auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
-  if (I == FeaturesVec.end())
-return FeaturesVec;
-
-  ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
-  std::vector NonISAExtFeature =
-  collectNonISAExtFeature(FeaturesNeedOverride, XLen);
-
-  std::vector ResolvedFeature(++I, FeaturesVec.end());
-  ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
- NonISAExtFeature.end());
-
-  return ResolvedFeature;
-}
-
 bool RISCVTargetInfo::initFeatureMap(
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures = std::vector(std::next(I), 
FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string ) {
+  assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+  std::string Ext = Feature.substr(1); // drop the +/-
+  return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+  std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
 
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+  }
+
+  // Otherwise, parse the features and add any implied extensions.
+  std::vector AllFeatures = FeaturesVec;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
   if (!ParseResult) {
 std::string Buffer;
 llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -295,21 +279,9 @@ bool RISCVTargetInfo::initFeatureMap(
 return false;
   }
 
-  // RISCVISAInfo makes implications for ISA features
-  std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
-
-  // parseFeatures normalizes the feature set by dropping any explicit
-  // negatives, and non-extension features.  We need to preserve the later
-  // for correctness and want

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Luke Lau via cfe-commits



@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](StringRef Feature) {
+  assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+  StringRef Ext = Feature.substr(1); // drop the +/-
+  return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+  std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
 
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+  }
+
+  // Otherwise, parse the features and add any implied extensions.
+  std::vector AllFeatures = FeaturesVec;

lukel97 wrote:

FeaturesVec is a const reference argument so we can't mutate it unfortunately. 
Is there another way to avoid the copy here?

https://github.com/llvm/llvm-project/pull/77426
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[clang] [clang] Upstream XROS support in Clang (PR #78392)

2024-01-16 Thread via cfe-commits


llvmbot wrote:



@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-clang-codegen

Author: Jonas Devlieghere (JDevlieghere)


Changes

Upstream XROS support in the clang frontend and driver.

---
Full diff: https://github.com/llvm/llvm-project/pull/78392.diff


10 Files Affected:

- (modified) clang/lib/Basic/Targets/OSTargets.h (+5-1) 
- (modified) clang/lib/CodeGen/CGObjC.cpp (+5) 
- (modified) clang/lib/Driver/Driver.cpp (+1) 
- (modified) clang/lib/Driver/ToolChains/Arch/AArch64.cpp (+5) 
- (modified) clang/lib/Driver/ToolChains/Arch/ARM.cpp (+3-2) 
- (modified) clang/lib/Driver/ToolChains/Darwin.cpp (+46-3) 
- (modified) clang/lib/Driver/ToolChains/Darwin.h (+13-1) 
- (modified) clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp (+2) 
- (added) clang/test/Driver/xros-driver.c (+41) 
- (added) clang/test/Frontend/xros-version.c (+3) 


``diff
diff --git a/clang/lib/Basic/Targets/OSTargets.h 
b/clang/lib/Basic/Targets/OSTargets.h
index 342af4bbc42b7b..4366c1149e4053 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -74,7 +74,8 @@ class LLVM_LIBRARY_VISIBILITY DarwinTargetInfo : public 
OSTargetInfo {
 this->TLSSupported = !Triple.isOSVersionLT(3);
 } else if (Triple.isDriverKit()) {
   // No TLS on DriverKit.
-}
+} else if (Triple.isXROS())
+  this->TLSSupported = true;
 
 this->MCountName = "\01mcount";
   }
@@ -109,6 +110,9 @@ class LLVM_LIBRARY_VISIBILITY DarwinTargetInfo : public 
OSTargetInfo {
 case llvm::Triple::WatchOS: // Earliest supporting version is 5.0.0.
   MinVersion = llvm::VersionTuple(5U);
   break;
+case llvm::Triple::XROS:
+  MinVersion = llvm::VersionTuple(0);
+  break;
 default:
   // Conservatively return 8 bytes if OS is unknown.
   return 64;
diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp
index acc85165a470be..03fc0ec7ff54e1 100644
--- a/clang/lib/CodeGen/CGObjC.cpp
+++ b/clang/lib/CodeGen/CGObjC.cpp
@@ -3941,6 +3941,8 @@ static unsigned getBaseMachOPlatformID(const llvm::Triple 
) {
 return llvm::MachO::PLATFORM_TVOS;
   case llvm::Triple::WatchOS:
 return llvm::MachO::PLATFORM_WATCHOS;
+  case llvm::Triple::XROS:
+return llvm::MachO::PLATFORM_XROS;
   case llvm::Triple::DriverKit:
 return llvm::MachO::PLATFORM_DRIVERKIT;
   default:
@@ -4024,6 +4026,9 @@ static bool isFoundationNeededForDarwinAvailabilityCheck(
   case llvm::Triple::MacOSX:
 FoundationDroppedInVersion = VersionTuple(/*Major=*/10, /*Minor=*/15);
 break;
+  case llvm::Triple::XROS:
+// XROS doesn't need Foundation.
+return false;
   case llvm::Triple::DriverKit:
 // DriverKit doesn't need Foundation.
 return false;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 1889ea28079df1..35d563b9a87fac 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -6213,6 +6213,7 @@ const ToolChain ::getToolChain(const ArgList ,
 case llvm::Triple::IOS:
 case llvm::Triple::TvOS:
 case llvm::Triple::WatchOS:
+case llvm::Triple::XROS:
 case llvm::Triple::DriverKit:
   TC = std::make_unique(*this, Target, Args);
   break;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 912df79417ae21..e73ffcfa4e343a 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -53,6 +53,11 @@ std::string aarch64::getAArch64TargetCPU(const ArgList ,
 return "apple-m1";
   }
 
+  if (Triple.isXROS()) {
+// The xrOS simulator runs on M1 as well, it should have been covered 
above.
+assert(!Triple.isSimulatorEnvironment() && "xrossim should be mac-like");
+return "apple-a12";
+  }
   // arm64e requires v8.3a and only runs on apple-a12 and later CPUs.
   if (Triple.isArm64e())
 return "apple-a12";
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp 
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 25470db2b6cebd..e6ee2f88a84edf 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -367,6 +367,7 @@ arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple 
) {
   case llvm::Triple::IOS:
   case llvm::Triple::TvOS:
   case llvm::Triple::DriverKit:
+  case llvm::Triple::XROS:
 // Darwin defaults to "softfp" for v6 and v7.
 if (Triple.isWatchABI())
   return FloatABI::Hard;
@@ -836,8 +837,8 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver 
,
 if (A->getOption().matches(options::OPT_mlong_calls))
   Features.push_back("+long-calls");
   } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
- !Triple.isWatchOS()) {
-  Features.push_back("+long-calls");
+ !Triple.isWatchOS() && !Triple.isXROS()) {
+Features.push_back("+long-calls");
   }
 
   // Generate execute-only output (no data access to code sections).
diff

[clang] [clang] Upstream XROS support in Clang (PR #78392)

2024-01-16 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Jonas Devlieghere (JDevlieghere)


Changes

Upstream XROS support in the clang frontend and driver.

---
Full diff: https://github.com/llvm/llvm-project/pull/78392.diff


10 Files Affected:

- (modified) clang/lib/Basic/Targets/OSTargets.h (+5-1) 
- (modified) clang/lib/CodeGen/CGObjC.cpp (+5) 
- (modified) clang/lib/Driver/Driver.cpp (+1) 
- (modified) clang/lib/Driver/ToolChains/Arch/AArch64.cpp (+5) 
- (modified) clang/lib/Driver/ToolChains/Arch/ARM.cpp (+3-2) 
- (modified) clang/lib/Driver/ToolChains/Darwin.cpp (+46-3) 
- (modified) clang/lib/Driver/ToolChains/Darwin.h (+13-1) 
- (modified) clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp (+2) 
- (added) clang/test/Driver/xros-driver.c (+41) 
- (added) clang/test/Frontend/xros-version.c (+3) 


``diff
diff --git a/clang/lib/Basic/Targets/OSTargets.h 
b/clang/lib/Basic/Targets/OSTargets.h
index 342af4bbc42b7bc..4366c1149e40530 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -74,7 +74,8 @@ class LLVM_LIBRARY_VISIBILITY DarwinTargetInfo : public 
OSTargetInfo {
 this->TLSSupported = !Triple.isOSVersionLT(3);
 } else if (Triple.isDriverKit()) {
   // No TLS on DriverKit.
-}
+} else if (Triple.isXROS())
+  this->TLSSupported = true;
 
 this->MCountName = "\01mcount";
   }
@@ -109,6 +110,9 @@ class LLVM_LIBRARY_VISIBILITY DarwinTargetInfo : public 
OSTargetInfo {
 case llvm::Triple::WatchOS: // Earliest supporting version is 5.0.0.
   MinVersion = llvm::VersionTuple(5U);
   break;
+case llvm::Triple::XROS:
+  MinVersion = llvm::VersionTuple(0);
+  break;
 default:
   // Conservatively return 8 bytes if OS is unknown.
   return 64;
diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp
index acc85165a470be7..03fc0ec7ff54e1c 100644
--- a/clang/lib/CodeGen/CGObjC.cpp
+++ b/clang/lib/CodeGen/CGObjC.cpp
@@ -3941,6 +3941,8 @@ static unsigned getBaseMachOPlatformID(const llvm::Triple 
) {
 return llvm::MachO::PLATFORM_TVOS;
   case llvm::Triple::WatchOS:
 return llvm::MachO::PLATFORM_WATCHOS;
+  case llvm::Triple::XROS:
+return llvm::MachO::PLATFORM_XROS;
   case llvm::Triple::DriverKit:
 return llvm::MachO::PLATFORM_DRIVERKIT;
   default:
@@ -4024,6 +4026,9 @@ static bool isFoundationNeededForDarwinAvailabilityCheck(
   case llvm::Triple::MacOSX:
 FoundationDroppedInVersion = VersionTuple(/*Major=*/10, /*Minor=*/15);
 break;
+  case llvm::Triple::XROS:
+// XROS doesn't need Foundation.
+return false;
   case llvm::Triple::DriverKit:
 // DriverKit doesn't need Foundation.
 return false;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 1889ea28079df10..35d563b9a87fac4 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -6213,6 +6213,7 @@ const ToolChain ::getToolChain(const ArgList ,
 case llvm::Triple::IOS:
 case llvm::Triple::TvOS:
 case llvm::Triple::WatchOS:
+case llvm::Triple::XROS:
 case llvm::Triple::DriverKit:
   TC = std::make_unique(*this, Target, Args);
   break;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 912df79417ae21e..e73ffcfa4e343af 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -53,6 +53,11 @@ std::string aarch64::getAArch64TargetCPU(const ArgList ,
 return "apple-m1";
   }
 
+  if (Triple.isXROS()) {
+// The xrOS simulator runs on M1 as well, it should have been covered 
above.
+assert(!Triple.isSimulatorEnvironment() && "xrossim should be mac-like");
+return "apple-a12";
+  }
   // arm64e requires v8.3a and only runs on apple-a12 and later CPUs.
   if (Triple.isArm64e())
 return "apple-a12";
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp 
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 25470db2b6cebd7..e6ee2f88a84edf2 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -367,6 +367,7 @@ arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple 
) {
   case llvm::Triple::IOS:
   case llvm::Triple::TvOS:
   case llvm::Triple::DriverKit:
+  case llvm::Triple::XROS:
 // Darwin defaults to "softfp" for v6 and v7.
 if (Triple.isWatchABI())
   return FloatABI::Hard;
@@ -836,8 +837,8 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver 
,
 if (A->getOption().matches(options::OPT_mlong_calls))
   Features.push_back("+long-calls");
   } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
- !Triple.isWatchOS()) {
-  Features.push_back("+long-calls");
+ !Triple.isWatchOS() && !Triple.isXROS()) {
+Features.push_back("+long-calls");
   }
 
   // Generate execute-only output (no data access to code sections).
diff --git

[clang] [clang] Upstream XROS support in Clang (PR #78392)

2024-01-16 Thread Jonas Devlieghere via cfe-commits


https://github.com/JDevlieghere created 
https://github.com/llvm/llvm-project/pull/78392

Upstream XROS support in the clang frontend and driver.

>From 1e65420f87eed1f7f4380496f96eef2560a15cb0 Mon Sep 17 00:00:00 2001
From: Jonas Devlieghere 
Date: Tue, 16 Jan 2024 20:36:47 -0800
Subject: [PATCH] [clang] Upstream XROS support in Clang

Upstream XROS support in the clang frontend and driver.
---
 clang/lib/Basic/Targets/OSTargets.h   |  6 ++-
 clang/lib/CodeGen/CGObjC.cpp  |  5 ++
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp  |  5 ++
 clang/lib/Driver/ToolChains/Arch/ARM.cpp  |  5 +-
 clang/lib/Driver/ToolChains/Darwin.cpp| 49 +--
 clang/lib/Driver/ToolChains/Darwin.h  | 14 +-
 .../Checkers/CheckSecuritySyntaxOnly.cpp  |  2 +
 clang/test/Driver/xros-driver.c   | 41 
 clang/test/Frontend/xros-version.c|  3 ++
 10 files changed, 124 insertions(+), 7 deletions(-)
 create mode 100644 clang/test/Driver/xros-driver.c
 create mode 100644 clang/test/Frontend/xros-version.c

diff --git a/clang/lib/Basic/Targets/OSTargets.h 
b/clang/lib/Basic/Targets/OSTargets.h
index 342af4bbc42b7bc..4366c1149e40530 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -74,7 +74,8 @@ class LLVM_LIBRARY_VISIBILITY DarwinTargetInfo : public 
OSTargetInfo {
 this->TLSSupported = !Triple.isOSVersionLT(3);
 } else if (Triple.isDriverKit()) {
   // No TLS on DriverKit.
-}
+} else if (Triple.isXROS())
+  this->TLSSupported = true;
 
 this->MCountName = "\01mcount";
   }
@@ -109,6 +110,9 @@ class LLVM_LIBRARY_VISIBILITY DarwinTargetInfo : public 
OSTargetInfo {
 case llvm::Triple::WatchOS: // Earliest supporting version is 5.0.0.
   MinVersion = llvm::VersionTuple(5U);
   break;
+case llvm::Triple::XROS:
+  MinVersion = llvm::VersionTuple(0);
+  break;
 default:
   // Conservatively return 8 bytes if OS is unknown.
   return 64;
diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp
index acc85165a470be7..03fc0ec7ff54e1c 100644
--- a/clang/lib/CodeGen/CGObjC.cpp
+++ b/clang/lib/CodeGen/CGObjC.cpp
@@ -3941,6 +3941,8 @@ static unsigned getBaseMachOPlatformID(const llvm::Triple 
) {
 return llvm::MachO::PLATFORM_TVOS;
   case llvm::Triple::WatchOS:
 return llvm::MachO::PLATFORM_WATCHOS;
+  case llvm::Triple::XROS:
+return llvm::MachO::PLATFORM_XROS;
   case llvm::Triple::DriverKit:
 return llvm::MachO::PLATFORM_DRIVERKIT;
   default:
@@ -4024,6 +4026,9 @@ static bool isFoundationNeededForDarwinAvailabilityCheck(
   case llvm::Triple::MacOSX:
 FoundationDroppedInVersion = VersionTuple(/*Major=*/10, /*Minor=*/15);
 break;
+  case llvm::Triple::XROS:
+// XROS doesn't need Foundation.
+return false;
   case llvm::Triple::DriverKit:
 // DriverKit doesn't need Foundation.
 return false;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 1889ea28079df10..35d563b9a87fac4 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -6213,6 +6213,7 @@ const ToolChain ::getToolChain(const ArgList ,
 case llvm::Triple::IOS:
 case llvm::Triple::TvOS:
 case llvm::Triple::WatchOS:
+case llvm::Triple::XROS:
 case llvm::Triple::DriverKit:
   TC = std::make_unique(*this, Target, Args);
   break;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 912df79417ae21e..e73ffcfa4e343af 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -53,6 +53,11 @@ std::string aarch64::getAArch64TargetCPU(const ArgList ,
 return "apple-m1";
   }
 
+  if (Triple.isXROS()) {
+// The xrOS simulator runs on M1 as well, it should have been covered 
above.
+assert(!Triple.isSimulatorEnvironment() && "xrossim should be mac-like");
+return "apple-a12";
+  }
   // arm64e requires v8.3a and only runs on apple-a12 and later CPUs.
   if (Triple.isArm64e())
 return "apple-a12";
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp 
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 25470db2b6cebd7..e6ee2f88a84edf2 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -367,6 +367,7 @@ arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple 
) {
   case llvm::Triple::IOS:
   case llvm::Triple::TvOS:
   case llvm::Triple::DriverKit:
+  case llvm::Triple::XROS:
 // Darwin defaults to "softfp" for v6 and v7.
 if (Triple.isWatchABI())
   return FloatABI::Hard;
@@ -836,8 +837,8 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver 
,
 if (A->getOption().matches(options::OPT_mlong_calls))
   Features.push_back("+long-calls");
   } else if (KernelOrKext && (!Triple.isiOS() ||

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Craig Topper via cfe-commits



@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](StringRef Feature) {
+  assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+  StringRef Ext = Feature.substr(1); // drop the +/-
+  return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+  std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
 
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+  }
+
+  // Otherwise, parse the features and add any implied extensions.
+  std::vector AllFeatures = FeaturesVec;

topperc wrote:

This might need to be `std::vector` Also I'm not we should copy 
the vector here just to rename it?

https://github.com/llvm/llvm-project/pull/77426
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[clang] [clang-cl] document correct defaults for `-fms-compatibility-version` / `-fmsc-version` (PR #76418)

2024-01-16 Thread Saleem Abdulrasool via cfe-commits


https://github.com/compnerd closed 
https://github.com/llvm/llvm-project/pull/76418
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[clang] 3e0d71c - [clang-cl] document correct defaults for `-fms-compatibility-version` / `-fmsc-version` (#76418)

2024-01-16 Thread via cfe-commits


Author: h-vetinari
Date: 2024-01-16T20:28:29-08:00
New Revision: 3e0d71cdf4a406c6a1de825cf69d889d97ede46b

URL: 
https://github.com/llvm/llvm-project/commit/3e0d71cdf4a406c6a1de825cf69d889d97ede46b
DIFF: 
https://github.com/llvm/llvm-project/commit/3e0d71cdf4a406c6a1de825cf69d889d97ede46b.diff

LOG: [clang-cl] document correct defaults for `-fms-compatibility-version` / 
`-fmsc-version` (#76418)

The UserManual states wrongly (AFAICT) that these default are not being
defined for clang-cl, whereas further up the opposite is stated:


https://github.com/llvm/llvm-project/blob/c86fe3ee0b92934f5d18394d9a0cdc1d3f0eef64/clang/docs/UsersManual.rst#L3375-L3382

I've chosen to follow that wording, as it's the latest related update.

CC @RIscRIpt who recently touched this in
b3e6ff331925dde24a4707452d657da0fdf7f588
CC @AaronBallman who cared about this, c.f.
8fc0dcf036bf199b2af2e10a4f81215dbd706daf

Added: 


Modified: 
clang/docs/CommandGuide/clang.rst
clang/docs/UsersManual.rst

Removed: 




diff  --git a/clang/docs/CommandGuide/clang.rst 
b/clang/docs/CommandGuide/clang.rst
index e1c872cdc55396..643365215f8759 100644
--- a/clang/docs/CommandGuide/clang.rst
+++ b/clang/docs/CommandGuide/clang.rst
@@ -302,7 +302,7 @@ Language Selection and Mode Options
 .. option:: -fmsc-version=
 
  Set ``_MSC_VER``. When on Windows, this defaults to either the same value as
- the currently installed version of cl.exe, or ``1920``. Not set otherwise.
+ the currently installed version of cl.exe, or ``1933``. Not set otherwise.
 
 .. option:: -fborland-extensions
 

diff  --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst
index c6a6b06fc04be7..881d903d91a7ea 100644
--- a/clang/docs/UsersManual.rst
+++ b/clang/docs/UsersManual.rst
@@ -4436,11 +4436,11 @@ Execute ``clang-cl /?`` to see a list of supported 
options:
   -fmerge-all-constants   Allow merging of constants
   -fms-compatibility-version=
   Dot-separated value representing the Microsoft 
compiler version
-  number to report in _MSC_VER (0 = don't define 
it (default))
+  number to report in _MSC_VER (0 = don't define 
it; default is same value as installed cl.exe, or 1933)
   -fms-compatibility  Enable full Microsoft Visual C++ compatibility
   -fms-extensions Accept some non-standard constructs supported by 
the Microsoft compiler
   -fmsc-version=   Microsoft compiler version number to report in 
_MSC_VER
-  (0 = don't define it (default))
+  (0 = don't define it; default is same value as 
installed cl.exe, or 1933)
   -fno-addrsigDon't emit an address-significance table
   -fno-builtin-Disable implicit builtin knowledge of a specific 
function
   -fno-builtinDisable implicit builtin knowledge of functions



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[clang] [clang-cl] document correct defaults for `-fms-compatibility-version` / `-fmsc-version` (PR #76418)

2024-01-16 Thread Saleem Abdulrasool via cfe-commits


compnerd wrote:

Thank you for fixing the documentation!

https://github.com/llvm/llvm-project/pull/76418
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[clang] [llvm] [SPARC] Support reserving arbitrary general purpose registers (PR #74927)

2024-01-16 Thread Brad Smith via cfe-commits


brad0 wrote:

There is a conflict at the moment. Also 18 is coming up.

https://github.com/llvm/llvm-project/pull/74927
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[clang] [X86_64] fix empty structure vaarg in c++ (PR #77907)

2024-01-16 Thread Longsheng Mou via cfe-commits


CoTinker wrote:

I've revised it. Can you check it again? @phoebewang 

https://github.com/llvm/llvm-project/pull/77907
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[clang] [compiler-rt] [llvm] [X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (PR #78384)

2024-01-16 Thread Freddy Ye via cfe-commits


https://github.com/FreddyLeaf deleted 
https://github.com/llvm/llvm-project/pull/78384
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[clang] [compiler-rt] [llvm] [X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (PR #78384)

2024-01-16 Thread Freddy Ye via cfe-commits



@@ -184,12 +185,12 @@ X86_FEATURE   (AMX_TILE,"amx-tile")
 X86_FEATURE   (CLDEMOTE,"cldemote")
 X86_FEATURE   (CLFLUSHOPT,  "clflushopt")
 X86_FEATURE   (CLWB,"clwb")
+X86_FEATURE_COMPAT(F16C,"f16c",  38)

FreddyLeaf wrote:

79bf68d

https://github.com/llvm/llvm-project/pull/78384
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[clang] [compiler-rt] [llvm] [X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (PR #78384)

2024-01-16 Thread Freddy Ye via cfe-commits


https://github.com/FreddyLeaf updated 
https://github.com/llvm/llvm-project/pull/78384

>From 04bbfad594054c2dab033b977c7dfa178fee8568 Mon Sep 17 00:00:00 2001
From: Freddy Ye 
Date: Thu, 4 Jan 2024 21:00:23 +0800
Subject: [PATCH 1/2] [X86] Support "f16c" and "avx512fp16" for
 __builtin_cpu_supports

This resolves issue #65320.
---
 compiler-rt/lib/builtins/cpu_model/x86.c   | 5 -
 llvm/include/llvm/TargetParser/X86TargetParser.def | 5 +++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c 
b/compiler-rt/lib/builtins/cpu_model/x86.c
index 9d9a5d3f1542cd..0750e29f989a8d 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -148,7 +148,8 @@ enum ProcessorFeatures {
   FEATURE_LZCNT,
   FEATURE_MOVBE,
 
-  FEATURE_X86_64_BASELINE = 95,
+  FEATURE_AVX512FP16 = 94,
+  FEATURE_X86_64_BASELINE,
   FEATURE_X86_64_V2,
   FEATURE_X86_64_V3,
   FEATURE_X86_64_V4,
@@ -812,6 +813,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned 
EDX, unsigned MaxLeaf,
 setFeature(FEATURE_AVX5124FMAPS);
   if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
 setFeature(FEATURE_AVX512VP2INTERSECT);
+  if (HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save)
+setFeature(FEATURE_AVX512FP16);
 
   // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
   // return all 0s for invalid subleaves so check the limit.
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def 
b/llvm/include/llvm/TargetParser/X86TargetParser.def
index b58feafe4e8c24..43162f2b52ebab 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -122,6 +122,7 @@ X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "gracemont")
 //
 // We cannot just re-sort the list though because its order is dictated by the
 // order of bits in CodeGenFunction::GetX86CpuSupportsMask.
+// We cannot re-adjust the position of X86_FEATURE_COMPAT at the whole list.
 #ifndef X86_FEATURE_COMPAT
 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) X86_FEATURE(ENUM, STR)
 #endif
@@ -184,12 +185,12 @@ X86_FEATURE   (AMX_TILE,"amx-tile")
 X86_FEATURE   (CLDEMOTE,"cldemote")
 X86_FEATURE   (CLFLUSHOPT,  "clflushopt")
 X86_FEATURE   (CLWB,"clwb")
+X86_FEATURE_COMPAT(F16C,"f16c",  38)
 X86_FEATURE   (CLZERO,  "clzero")
 X86_FEATURE   (CMPXCHG16B,  "cx16")
 X86_FEATURE   (CMPXCHG8B,   "cx8")
 X86_FEATURE   (CRC32,   "crc32")
 X86_FEATURE   (ENQCMD,  "enqcmd")
-X86_FEATURE   (F16C,"f16c")
 X86_FEATURE   (FSGSBASE,"fsgsbase")
 X86_FEATURE   (FXSR,"fxsr")
 X86_FEATURE   (INVPCID, "invpcid")
@@ -229,9 +230,9 @@ X86_FEATURE   (XSAVE,   "xsave")
 X86_FEATURE   (XSAVEC,  "xsavec")
 X86_FEATURE   (XSAVEOPT,"xsaveopt")
 X86_FEATURE   (XSAVES,  "xsaves")
+X86_FEATURE_COMPAT(AVX512FP16,  "avx512fp16",39)
 X86_FEATURE   (HRESET,  "hreset")
 X86_FEATURE   (RAOINT,  "raoint")
-X86_FEATURE   (AVX512FP16,  "avx512fp16")
 X86_FEATURE   (AMX_FP16,"amx-fp16")
 X86_FEATURE   (CMPCCXADD,   "cmpccxadd")
 X86_FEATURE   (AVXNECONVERT,"avxneconvert")

>From 79bf68d976ef53d5a404cd9b7a0bd485c9937ba0 Mon Sep 17 00:00:00 2001
From: Freddy Ye 
Date: Wed, 17 Jan 2024 12:06:38 +0800
Subject: [PATCH 2/2] add test

---
 clang/test/CodeGen/target-builtin-noerror.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/clang/test/CodeGen/target-builtin-noerror.c 
b/clang/test/CodeGen/target-builtin-noerror.c
index 505f4a3e94565d..06bb40a2b71ea9 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -82,6 +82,8 @@ void verifyfeaturestrings(void) {
   (void)__builtin_cpu_supports("avx512bitalg");
   (void)__builtin_cpu_supports("avx512bf16");
   (void)__builtin_cpu_supports("avx512vp2intersect");
+  (void)__builtin_cpu_supports("f16c");
+  (void)__builtin_cpu_supports("avx512fp16");
 }
 
 void verifycpustrings(void) {

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[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Luke Lau via cfe-commits


https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77426

>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/3] [RISCV] Overwrite cpu target features for full arch
 string in target attribute

This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)

When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.

In initFeatureMap, there are now two code paths:

1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.

Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.

2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
---
 clang/lib/Basic/Targets/RISCV.cpp | 78 +++
 .../CodeGen/RISCV/riscv-func-attr-target.c|  8 +-
 2 files changed, 30 insertions(+), 56 deletions(-)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..b56c1d465ad77a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,39 +235,6 @@ ArrayRef 
RISCVTargetInfo::getTargetBuiltins() const {
 clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
 }
 
-static std::vector
-collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
-  std::vector NonISAExtFeatureVec;
-
-  auto IsNonISAExtFeature = [](const std::string ) {
-assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
-StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
-return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
-  };
-  llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-IsNonISAExtFeature);
-
-  return NonISAExtFeatureVec;
-}
-
-static std::vector
-resolveTargetAttrOverride(const std::vector ,
-  int XLen) {
-  auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
-  if (I == FeaturesVec.end())
-return FeaturesVec;
-
-  ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
-  std::vector NonISAExtFeature =
-  collectNonISAExtFeature(FeaturesNeedOverride, XLen);
-
-  std::vector ResolvedFeature(++I, FeaturesVec.end());
-  ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
- NonISAExtFeature.end());
-
-  return ResolvedFeature;
-}
-
 bool RISCVTargetInfo::initFeatureMap(
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures = std::vector(std::next(I), 
FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string ) {
+  assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+  std::string Ext = Feature.substr(1); // drop the +/-
+  return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+  std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
 
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+  }
+
+  // Otherwise, parse the features and add any implied extensions.
+  std::vector AllFeatures = FeaturesVec;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
   if (!ParseResult) {
 std::string Buffer;
 llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -295,21 +279,9 @@ bool RISCVTargetInfo::initFeatureMap(
 return false;
   }
 
-  // RISCVISAInfo makes implications for ISA features
-  std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
-
-  // parseFeatures normalizes the feature set by dropping any explicit
-  // negatives, and non-extension features.  We need to preserve the later
-  // for correctness and want

[clang] [clang] Fix CTAD for aggregates for nested template classes (PR #78387)

2024-01-16 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-clang

Author: None (antangelo)


Changes

Use the template pattern in determining whether to synthesize the aggregate 
deduction guide, and update DeclareImplicitDeductionGuideFromInitList to 
substitute outer template arguments.

Fixes #77599

---
Full diff: https://github.com/llvm/llvm-project/pull/78387.diff


4 Files Affected:

- (modified) clang/docs/ReleaseNotes.rst (+3) 
- (modified) clang/lib/Sema/SemaInit.cpp (+8-1) 
- (modified) clang/lib/Sema/SemaTemplate.cpp (+17-4) 
- (modified) clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp 
(+18-1) 


``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1eba8ab5590c52..db589beb46aadb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -928,6 +928,9 @@ Bug Fixes to C++ Support
   (`#57410 `_) and
   (`#76604 `_)
 
+- Fixes CTAD for aggregates on nested template classes. Fixes:
+  (`#77599 `_)
+
 Bug Fixes to AST Handling
 ^
 - Fixed an import failure of recursive friend class template.
diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index 408ee5f775804b..48235941f62aa2 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -10718,7 +10718,14 @@ QualType 
Sema::DeduceTemplateSpecializationFromInitializer(
 bool HasAnyDeductionGuide = false;
 
 auto SynthesizeAggrGuide = [&](InitListExpr *ListInit) {
-  auto *RD = cast(Template->getTemplatedDecl());
+  auto *Pattern = Template;
+  while (Pattern->getInstantiatedFromMemberTemplate()) {
+if (Pattern->isMemberSpecialization())
+  break;
+Pattern = Pattern->getInstantiatedFromMemberTemplate();
+  }
+
+  auto *RD = cast(Pattern->getTemplatedDecl());
   if (!(RD->getDefinition() && RD->isAggregate()))
 return;
   QualType Ty = Context.getRecordType(RD);
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 80a48c268a648b..8c2199c36f0fe3 100644
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -2418,6 +2418,9 @@ struct ConvertConstructorToDeductionGuideTransform {
 QualType Result = SemaRef.BuildFunctionType(DeducedType, ParamTypes, Loc,
 DeductionGuideName, EPI);
 TypeSourceInfo *TSI = SemaRef.Context.getTrivialTypeSourceInfo(Result, 
Loc);
+if (NestedPattern)
+  TSI = SemaRef.SubstType(TSI, OuterInstantiationArgs, Loc,
+  DeductionGuideName);
 
 FunctionProtoTypeLoc FPTL =
 TSI->getTypeLoc().castAs();
@@ -2425,9 +2428,13 @@ struct ConvertConstructorToDeductionGuideTransform {
 // Build the parameters, needed during deduction / substitution.
 SmallVector Params;
 for (auto T : ParamTypes) {
-  ParmVarDecl *NewParam = ParmVarDecl::Create(
-  SemaRef.Context, DC, Loc, Loc, nullptr, T,
-  SemaRef.Context.getTrivialTypeSourceInfo(T, Loc), SC_None, nullptr);
+  auto *TSI = SemaRef.Context.getTrivialTypeSourceInfo(T, Loc);
+  if (NestedPattern)
+TSI = SemaRef.SubstType(TSI, OuterInstantiationArgs, Loc,
+DeclarationName());
+  ParmVarDecl *NewParam =
+  ParmVarDecl::Create(SemaRef.Context, DC, Loc, Loc, nullptr,
+  TSI->getType(), TSI, SC_None, nullptr);
   NewParam->setScopeInfo(0, Params.size());
   FPTL.setParam(Params.size(), NewParam);
   Params.push_back(NewParam);
@@ -2670,8 +2677,14 @@ FunctionTemplateDecl 
*Sema::DeclareImplicitDeductionGuideFromInitList(
   if (BuildingDeductionGuides.isInvalid())
 return nullptr;
 
-  return cast(
+  ClassTemplateDecl *Pattern =
+  Transform.NestedPattern ? Transform.NestedPattern : Transform.Template;
+  ContextRAII SavedContext(*this, Pattern->getTemplatedDecl());
+
+  auto *DG = cast(
   Transform.buildSimpleDeductionGuide(ParamTypes));
+  SavedContext.pop();
+  return DG;
 }
 
 void Sema::DeclareImplicitDeductionGuides(TemplateDecl *Template,
diff --git a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp 
b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
index c44ec6918c7afb..f3af6e8d6c17da 100644
--- a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
+++ b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
@@ -1,5 +1,4 @@
 // RUN: %clang_cc1 -std=c++20 -verify %s
-// expected-no-diagnostics
 
 template struct S {
 template struct N {
@@ -58,3 +57,21 @@ template struct requires_clause {
 requires_clause::B req(1, 2);
 using RC = decltype(req);
 using RC = requires_clause::B;
+
+template struct nested_init_list {
+template Y>
+struct B { // #INIT_LIST_INNER
+X x;
+Y y;
+};
+};
+

[clang] [clang] Fix CTAD for aggregates for nested template classes (PR #78387)

2024-01-16 Thread via cfe-commits


https://github.com/antangelo created 
https://github.com/llvm/llvm-project/pull/78387

Use the template pattern in determining whether to synthesize the aggregate 
deduction guide, and update DeclareImplicitDeductionGuideFromInitList to 
substitute outer template arguments.

Fixes #77599

>From 50a9a2e9eeb8af3c36035ad167c224302c8ae269 Mon Sep 17 00:00:00 2001
From: Antonio Abbatangelo 
Date: Mon, 15 Jan 2024 22:50:58 -0500
Subject: [PATCH] [clang] Fix CTAD for aggregates for nested template classes

Use the template pattern in determining whether to synthesize the
aggregate deduction guide, and update DeclareImplicitDeductionGuideFromInitList
to substitute outer template arguments.
---
 clang/docs/ReleaseNotes.rst   |  3 +++
 clang/lib/Sema/SemaInit.cpp   |  9 +++-
 clang/lib/Sema/SemaTemplate.cpp   | 21 +++
 .../nested-implicit-deduction-guides.cpp  | 19 -
 4 files changed, 46 insertions(+), 6 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1eba8ab5590c52..db589beb46aadb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -928,6 +928,9 @@ Bug Fixes to C++ Support
   (`#57410 `_) and
   (`#76604 `_)
 
+- Fixes CTAD for aggregates on nested template classes. Fixes:
+  (`#77599 `_)
+
 Bug Fixes to AST Handling
 ^
 - Fixed an import failure of recursive friend class template.
diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index 408ee5f775804b..48235941f62aa2 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -10718,7 +10718,14 @@ QualType 
Sema::DeduceTemplateSpecializationFromInitializer(
 bool HasAnyDeductionGuide = false;
 
 auto SynthesizeAggrGuide = [&](InitListExpr *ListInit) {
-  auto *RD = cast(Template->getTemplatedDecl());
+  auto *Pattern = Template;
+  while (Pattern->getInstantiatedFromMemberTemplate()) {
+if (Pattern->isMemberSpecialization())
+  break;
+Pattern = Pattern->getInstantiatedFromMemberTemplate();
+  }
+
+  auto *RD = cast(Pattern->getTemplatedDecl());
   if (!(RD->getDefinition() && RD->isAggregate()))
 return;
   QualType Ty = Context.getRecordType(RD);
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 80a48c268a648b..8c2199c36f0fe3 100644
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -2418,6 +2418,9 @@ struct ConvertConstructorToDeductionGuideTransform {
 QualType Result = SemaRef.BuildFunctionType(DeducedType, ParamTypes, Loc,
 DeductionGuideName, EPI);
 TypeSourceInfo *TSI = SemaRef.Context.getTrivialTypeSourceInfo(Result, 
Loc);
+if (NestedPattern)
+  TSI = SemaRef.SubstType(TSI, OuterInstantiationArgs, Loc,
+  DeductionGuideName);
 
 FunctionProtoTypeLoc FPTL =
 TSI->getTypeLoc().castAs();
@@ -2425,9 +2428,13 @@ struct ConvertConstructorToDeductionGuideTransform {
 // Build the parameters, needed during deduction / substitution.
 SmallVector Params;
 for (auto T : ParamTypes) {
-  ParmVarDecl *NewParam = ParmVarDecl::Create(
-  SemaRef.Context, DC, Loc, Loc, nullptr, T,
-  SemaRef.Context.getTrivialTypeSourceInfo(T, Loc), SC_None, nullptr);
+  auto *TSI = SemaRef.Context.getTrivialTypeSourceInfo(T, Loc);
+  if (NestedPattern)
+TSI = SemaRef.SubstType(TSI, OuterInstantiationArgs, Loc,
+DeclarationName());
+  ParmVarDecl *NewParam =
+  ParmVarDecl::Create(SemaRef.Context, DC, Loc, Loc, nullptr,
+  TSI->getType(), TSI, SC_None, nullptr);
   NewParam->setScopeInfo(0, Params.size());
   FPTL.setParam(Params.size(), NewParam);
   Params.push_back(NewParam);
@@ -2670,8 +2677,14 @@ FunctionTemplateDecl 
*Sema::DeclareImplicitDeductionGuideFromInitList(
   if (BuildingDeductionGuides.isInvalid())
 return nullptr;
 
-  return cast(
+  ClassTemplateDecl *Pattern =
+  Transform.NestedPattern ? Transform.NestedPattern : Transform.Template;
+  ContextRAII SavedContext(*this, Pattern->getTemplatedDecl());
+
+  auto *DG = cast(
   Transform.buildSimpleDeductionGuide(ParamTypes));
+  SavedContext.pop();
+  return DG;
 }
 
 void Sema::DeclareImplicitDeductionGuides(TemplateDecl *Template,
diff --git a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp 
b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
index c44ec6918c7afb..f3af6e8d6c17da 100644
--- a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
+++ b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
@@ -1,5 +1,4 @@
 // RUN: %clang_cc1

[llvm] [clang] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)

2024-01-16 Thread Phoebe Wang via cfe-commits


phoebewang wrote:

Thanks @KanRobert !

https://github.com/llvm/llvm-project/pull/77733
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[llvm] [clang] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)

2024-01-16 Thread Phoebe Wang via cfe-commits


https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/77733
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[clang] 8d6e82d - [X86] Use vXi1 for `k` constraint in inline asm (#77733)

2024-01-16 Thread via cfe-commits


Author: Phoebe Wang
Date: 2024-01-17T11:40:32+08:00
New Revision: 8d6e82d501cda1946c7d99658241033d78676e95

URL: 
https://github.com/llvm/llvm-project/commit/8d6e82d501cda1946c7d99658241033d78676e95
DIFF: 
https://github.com/llvm/llvm-project/commit/8d6e82d501cda1946c7d99658241033d78676e95.diff

LOG: [X86] Use vXi1 for `k` constraint in inline asm (#77733)

Fixes #77172

Added: 


Modified: 
clang/lib/CodeGen/CGStmt.cpp
clang/lib/CodeGen/Targets/X86.cpp
clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/pr41678.ll

Removed: 




diff  --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index b89017de0bcf14..beff0ad9da2709 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -2399,9 +2399,9 @@ EmitAsmStores(CodeGenFunction , const AsmStmt ,
 Tmp = Builder.CreatePtrToInt(
 Tmp, llvm::IntegerType::get(CTX, (unsigned)TmpSize));
 Tmp = Builder.CreateTrunc(Tmp, TruncTy);
-  } else if (TruncTy->isIntegerTy()) {
+  } else if (Tmp->getType()->isIntegerTy() && TruncTy->isIntegerTy()) {
 Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
-  } else if (TruncTy->isVectorTy()) {
+  } else if (Tmp->getType()->isVectorTy() || TruncTy->isVectorTy()) {
 Tmp = Builder.CreateBitCast(Tmp, TruncTy);
   }
 }

diff  --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index d053f41ab168f5..2291c991fb1107 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -40,6 +40,11 @@ static llvm::Type* 
X86AdjustInlineAsmType(CodeGen::CodeGenFunction ,
 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
   }
 
+  if (Constraint == "k") {
+llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
+return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
+  }
+
   // No operation needed
   return Ty;
 }

diff  --git a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c 
b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
index b4939bfc2ca831..74b6719bf9cfdd 100644
--- a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
+++ b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
@@ -41,7 +41,7 @@ __m512i mask_Yk_i64(long long msk, __m512i x, __m512i y){
 }
 
 char k_wise_op_i8(char msk_src1,char msk_src2){
-//CHECK: i8 asm "kandb\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i8 
%{{.*}}, i8 %{{.*}})
+//CHECK: <8 x i1> asm "kandb\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<8 x i1> %{{.*}}, <8 x i1> %{{.*}})
   char msk_dst;
   asm ("kandb\t%2, %1, %0"
: "=k" (msk_dst)
@@ -50,7 +50,7 @@ char k_wise_op_i8(char msk_src1,char msk_src2){
 }
 
 short k_wise_op_i16(short msk_src1, short msk_src2){
-//CHECK: i16 asm "kandw\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i16 %{{.*}}, i16 %{{.*}})
+//CHECK: <16 x i1> asm "kandw\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<16 x i1> %{{.*}}, <16 x i1> %{{.*}})
   short msk_dst;
   asm ("kandw\t%2, %1, %0"
: "=k" (msk_dst)
@@ -59,7 +59,7 @@ short k_wise_op_i16(short msk_src1, short msk_src2){
 }
 
 int k_wise_op_i32(int msk_src1, int msk_src2){
-//CHECK: i32 asm "kandd\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i32 %{{.*}}, i32 %{{.*}})
+//CHECK: <32 x i1> asm "kandd\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<32 x i1> %{{.*}}, <32 x i1> %{{.*}})
   int msk_dst;
   asm ("kandd\t%2, %1, %0"
: "=k" (msk_dst)
@@ -68,7 +68,7 @@ int k_wise_op_i32(int msk_src1, int msk_src2){
 }
 
 long long k_wise_op_i64(long long msk_src1, long long msk_src2){
-//CHECK: i64 asm "kandq\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i64 %{{.*}}, i64 %{{.*}})
+//CHECK: <64 x i1> asm "kandq\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<64 x i1> %{{.*}}, <64 x i1> %{{.*}})
   long long msk_dst;
   asm ("kandq\t%2, %1, %0"
: "=k" (msk_dst)

diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e19128ec775651..ff2014d8fa7b1c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57085,17 +57085,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
TargetRegisterInfo *TRI,
   // in the normal allocation?
 case 'k':
   if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1 || VT == MVT::i1)
   return std::make_pair(0U, ::VK1RegClass);
-if (VT == MVT::i8)
+if (VT == MVT::v8i1 || VT == MVT::i8)
   return std::make_pair(0U, ::VK8RegClass);
-if (VT == MVT::i16)
+if (VT == MVT::v16i1 || VT == MVT::i16)
   return std::make_pair(0U, ::VK16RegClass);
   }
   if (Subtarget.hasBWI()) {
-if (VT == MVT::i32)
+if (VT ==

[llvm] [clang] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread Jessica Paquette via cfe-commits



@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
 return E->getOpcode() == BO_LAnd;
   }
 
-  /// Push an ID onto the corresponding RHS stack.
-  void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[CodeGenFunction::stripCond(E->getRHS())]);
-  }
-
-  /// Pop an ID from the corresponding RHS stack.
-  void popRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-if (!rhs.empty())
-  rhs.pop_back();
-  }
-
-  /// If the expected ID is on top, pop it off the corresponding RHS stack.
-  void popRHSifTop(const BinaryOperator *E) {
-if (!OrRHS.empty() && CondIDs[E] == OrRHS.back())
-  OrRHS.pop_back();
-else if (!AndRHS.empty() && CondIDs[E] == AndRHS.back())
-  AndRHS.pop_back();
-  }
-
 public:
   MCDCCoverageBuilder(CodeGenModule ,
   llvm::DenseMap ,
   llvm::DenseMap )
-  : CGM(CGM), CondIDs(CondIDMap), MCDCBitmapMap(MCDCBitmapMap) {}
+  : CGM(CGM), DecisionStack(1), CondIDs(CondIDMap),
+MCDCBitmapMap(MCDCBitmapMap) {}
 
-  /// Return the ID of the RHS of the next, upper nest-level logical-OR.
-  MCDCConditionID getNextLOrCondID() const {
-return OrRHS.empty() ? 0 : OrRHS.back();
-  }
+  /// Return whether the control flow map is not presently being built. This
+  /// can be used to determine whether the flow is at the root node of an

ornata wrote:

I find the comment here kind of confusing.

I'd assume that `isIdle() == !isBuilding()` from this comment.

https://github.com/llvm/llvm-project/pull/78202
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[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

2024-01-16 Thread Phoebe Wang via cfe-commits


https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/77686
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[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

2024-01-16 Thread Phoebe Wang via cfe-commits



@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
 #endif /* __x86_64__ */
 
 #ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile 
+///
+/// This intrinsic corresponds to the \c PUSHFQ + \c POP instruction sequence.

phoebewang wrote:

The mnemonic in SDM is PUSHFQ

https://github.com/llvm/llvm-project/pull/77686
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[llvm] [clang] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread Jessica Paquette via cfe-commits



@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
 return E->getOpcode() == BO_LAnd;
   }
 
-  /// Push an ID onto the corresponding RHS stack.
-  void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[CodeGenFunction::stripCond(E->getRHS())]);
-  }
-
-  /// Pop an ID from the corresponding RHS stack.
-  void popRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-if (!rhs.empty())
-  rhs.pop_back();
-  }
-
-  /// If the expected ID is on top, pop it off the corresponding RHS stack.
-  void popRHSifTop(const BinaryOperator *E) {
-if (!OrRHS.empty() && CondIDs[E] == OrRHS.back())
-  OrRHS.pop_back();
-else if (!AndRHS.empty() && CondIDs[E] == AndRHS.back())
-  AndRHS.pop_back();
-  }
-
 public:
   MCDCCoverageBuilder(CodeGenModule ,
   llvm::DenseMap ,
   llvm::DenseMap )
-  : CGM(CGM), CondIDs(CondIDMap), MCDCBitmapMap(MCDCBitmapMap) {}
+  : CGM(CGM), DecisionStack(1), CondIDs(CondIDMap),
+MCDCBitmapMap(MCDCBitmapMap) {}
 
-  /// Return the ID of the RHS of the next, upper nest-level logical-OR.
-  MCDCConditionID getNextLOrCondID() const {
-return OrRHS.empty() ? 0 : OrRHS.back();
-  }
+  /// Return whether the control flow map is not presently being built. This
+  /// can be used to determine whether the flow is at the root node of an
+  /// expression if that expression is mapped.
+  bool isIdle() { return (NextID == 1 && !NotMapped); }

ornata wrote:

these can be `const`

https://github.com/llvm/llvm-project/pull/78202
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[llvm] [clang] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread Jessica Paquette via cfe-commits



@@ -676,41 +679,25 @@ struct MCDCCoverageBuilder {
 return E->getOpcode() == BO_LAnd;
   }
 
-  /// Push an ID onto the corresponding RHS stack.
-  void pushRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-rhs.push_back(CondIDs[CodeGenFunction::stripCond(E->getRHS())]);
-  }
-
-  /// Pop an ID from the corresponding RHS stack.
-  void popRHS(const BinaryOperator *E) {
-llvm::SmallVector  = isLAnd(E) ? AndRHS : OrRHS;
-if (!rhs.empty())
-  rhs.pop_back();
-  }
-
-  /// If the expected ID is on top, pop it off the corresponding RHS stack.
-  void popRHSifTop(const BinaryOperator *E) {
-if (!OrRHS.empty() && CondIDs[E] == OrRHS.back())
-  OrRHS.pop_back();
-else if (!AndRHS.empty() && CondIDs[E] == AndRHS.back())
-  AndRHS.pop_back();
-  }
-
 public:
   MCDCCoverageBuilder(CodeGenModule ,
   llvm::DenseMap ,
   llvm::DenseMap )
-  : CGM(CGM), CondIDs(CondIDMap), MCDCBitmapMap(MCDCBitmapMap) {}
+  : CGM(CGM), DecisionStack(1), CondIDs(CondIDMap),

ornata wrote:

IIUC `DecisionStack(1)` is supposed to be a sentinel value.

Would it be possible to define a `DecisionStackSentinel` variable equal to 1, 
so we can document it?

https://github.com/llvm/llvm-project/pull/78202
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[llvm] [clang] [clang][CoverageMapping] Refactor when setting MC/DC True/False (PR #78202)

2024-01-16 Thread Jessica Paquette via cfe-commits



@@ -722,6 +709,12 @@ struct MCDCCoverageBuilder {
   return I->second;
   }
 
+  /// Return the LHS Decision ({0,0} if not set).
+  const DecisionIDPair () {
+assert(DecisionStack.size() >= 1);

ornata wrote:

This assert should be unnecessary. `SmallVector` already asserts for you:

```
  reference back() {
assert(!empty());
return end()[-1];
  }
  const_reference back() const {
assert(!empty());
return end()[-1];
  }
```

https://github.com/llvm/llvm-project/pull/78202
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[clang] [clang][PP] Add extension to predefine target OS macros (PR #74676)

2024-01-16 Thread Mike Hommey via cfe-commits


glandium wrote:

> It looks like this breaks building at least `MultiSource` from 
> https://github.com/llvm/llvm-test-suite/. The first failure I see is when 
> building `llvm-test-suite/MultiSource/Applications/ClamAV/zlib_zutil.c`
> 
> ```
> In file included from 
> /llvm-test-suite/MultiSource/Applications/ClamAV/zlib_zutil.c:10:
> In file included from 
> test-suites/llvm-test-suite/MultiSource/Applications/ClamAV/zlib/gzguts.h:21:
> ../usr/include/stdio.h:220:7: error: expected identifier or '('
>   220 | FILE*fdopen(int, const char *) 
> __DARWIN_ALIAS_STARTING(__MAC_10_6, __IPHONE_2_0, __DARWIN_ALIAS(fdopen));
>   |  ^
> llvm-test-suite/MultiSource/Applications/ClamAV/zlib/zutil.h:140:33: note: 
> expanded from macro 'fdopen'
>   140 | #define fdopen(fd,mode) NULL /* No fdopen() */
>   | ^
> llvm-project/builds/release-with-assertions/ccache-stage1/lib/clang/18/include/__stddef_null.h:26:16:
>  note: expanded from macro 'NULL'
>26 | #define NULL ((void*)0)
>   |^
> ```

These are actually part of zlib, so apart from llvm test suite having been 
broken by this (but was fixed), plain zlib has been broken too (although 
arguably, zlib is where the real issue is).

https://github.com/llvm/llvm-project/pull/74676
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[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Craig Topper via cfe-commits



@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures =
+std::vector(std::next(I), FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string ) {
+  assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+  std::string Ext = Feature.substr(1); // drop the +/-

topperc wrote:

StringRef Ext = Feature.drop_front(1)

https://github.com/llvm/llvm-project/pull/77426
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[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Craig Topper via cfe-commits



@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures =

topperc wrote:

`std::vector OverrideFeatures(std::next(I), FeaturesVec.end());`

https://github.com/llvm/llvm-project/pull/77426
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[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

2024-01-16 Thread Craig Topper via cfe-commits



@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap(
 Features["32bit"] = true;
   }
 
-  std::vector NewFeaturesVec =
-  resolveTargetAttrOverride(FeaturesVec, XLen);
+  // If a target attribute specified a full arch string, override all the ISA
+  // extension target features.
+  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures =
+std::vector(std::next(I), FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string ) {

topperc wrote:

`StringRef Feature`

https://github.com/llvm/llvm-project/pull/77426
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[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

2024-01-16 Thread Yeting Kuo via cfe-commits



@@ -27,6 +27,11 @@
 // DEFAULT-NOT: "-target-feature" "-save-restore"
 // DEFAULT-NOT: "-target-feature" "+save-restore"
 
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mforced-sw-shadow-stack 
2>&1 | FileCheck %s -check-prefix=FORCE-SW-SCS

yetingk wrote:

Done.

https://github.com/llvm/llvm-project/pull/68075
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[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

2024-01-16 Thread Yeting Kuo via cfe-commits



@@ -151,9 +157,12 @@ Usage
 
 To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
 to both compile and link command lines. On aarch64, you also need to pass
-``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3``
-(``gp``) is always reserved. It is, however, important to disable GP relaxation
-in the linker. This can be done with the ``--no-relax-gp`` flag in GNU ld.
+``-ffixed-x18`` unless your target already reserves ``x18``. No additional 
flags
+need to be passed on RISC-V because the software based shadow stack uses 
``x3`` (``gp``),
+which is always reserved, and the hardware based shadow call stack uses a 
dedicated register, ``ssp``.

yetingk wrote:

Done.

https://github.com/llvm/llvm-project/pull/68075
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[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

2024-01-16 Thread Yeting Kuo via cfe-commits



@@ -57,11 +57,16 @@ compiled application or the operating system. Integrating 
the runtime into
 the operating system should be preferred since otherwise all thread creation
 and destruction would need to be intercepted by the application.
 
-The instrumentation makes use of the platform register ``x18`` on AArch64 and
-``x3`` (``gp``) on RISC-V. For simplicity we will refer to this as the
-``SCSReg``. On some platforms, ``SCSReg`` is reserved, and on others, it is
-designated as a scratch register.  This generally means that any code that may
-run on the same thread as code compiled with ShadowCallStack must either target
+The instrumentation makes use of the platform register ``x18`` on AArch64,
+``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with
+hardware shadow stack, which needs `Zicfiss`_ and 
``-mno-forced-sw-shadow-stack``
+(default option). Note that with ``Zicfiss``_ the RISC-V backend will default 
to
+the hardware based shadow call stack. Users can force the RISC-V backend to
+generate the software shadow call stack with ``Zicfiss``_ by passing
+``-mforced-sw-shadow-stack``.
+For simplicity we will refer to this as the ``SCSReg``. On some platforms,
+``SCSReg`` is reserved, and on others, it is designated as a scratch register.
+This generally means that any code that may run on the same thread as code 
compiled with ShadowCallStack must either target

yetingk wrote:

Done.

https://github.com/llvm/llvm-project/pull/68075
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[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

2024-01-16 Thread Yeting Kuo via cfe-commits


https://github.com/yetingk updated 
https://github.com/llvm/llvm-project/pull/68075

>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo 
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/8] [RISCV] Implement shadow stack on shadow stack mode with
 Zicfiss.

There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular 
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.

[spec]: 
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp |  14 +-
 llvm/test/CodeGen/RISCV/shadowcallstack.ll   | 130 +++
 2 files changed, 142 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057c..6f043ade98f4093 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction , 
MachineBasicBlock ,
   CSI, [&](CalleeSavedInfo ) { return CSR.getReg() == RAReg; }))
 return;
 
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
+  if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+  }
+
   Register SCSPReg = RISCVABI::getSCSPReg();
 
-  const RISCVInstrInfo *TII = STI.getInstrInfo();
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
   int64_t SlotSize = STI.getXLen() / 8;
   // Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction , 
MachineBasicBlock ,
   CSI, [&](CalleeSavedInfo ) { return CSR.getReg() == RAReg; }))
 return;
 
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
+  if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+  }
+
   Register SCSPReg = RISCVABI::getSCSPReg();
 
-  const RISCVInstrInfo *TII = STI.getInstrInfo();
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
   int64_t SlotSize = STI.getXLen() / 8;
   // Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll 
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index b41b87aaf4d0d88..1861d2e36227c33 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
 ; RUN:   | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs 
< %s \
+; RUN:   | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs 
< %s \
+; RUN:   | FileCheck %s --check-prefix=RV64-ZICFISS
 
 define void @f1() shadowcallstack {
 ; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
 ; RV64-LABEL: f1:
 ; RV64:   # %bb.0:
 ; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS:   # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS:   # %bb.0:
+; RV64-ZICFISS-NEXT:ret
   ret void
 }
 
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
 ; RV64-LABEL: f2:
 ; RV64:   # %bb.0:
 ; RV64-NEXT:tail foo
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS:   # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS:   # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo
   tail call void @foo()
   ret void
 }
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
 ; RV64-NEXT:addi gp, gp, -8
 ; RV64-NEXT:.cfi_restore gp
 ; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS:   # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS:   # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
   %res = call i32 @bar()
   %res1 = add i32 %res, 1
   ret i32 %res
@@ -140,6 +186,68 @@ define

[clang] [clang] Emit error for invalid friend functions under [temp.friend]p9 (PR #78083)

2024-01-16 Thread via cfe-commits


https://github.com/antangelo closed 
https://github.com/llvm/llvm-project/pull/78083
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[clang] 46a395d - [clang] Emit error for invalid friend functions under [temp.friend]p9 (#78083)

2024-01-16 Thread via cfe-commits


Author: antangelo
Date: 2024-01-16T21:06:02-05:00
New Revision: 46a395d8c41f6009a7fbae51f408c3c6ea2399d3

URL: 
https://github.com/llvm/llvm-project/commit/46a395d8c41f6009a7fbae51f408c3c6ea2399d3
DIFF: 
https://github.com/llvm/llvm-project/commit/46a395d8c41f6009a7fbae51f408c3c6ea2399d3.diff

LOG: [clang] Emit error for invalid friend functions under [temp.friend]p9 
(#78083)

Emits an error for friend FunctionDecls that either:

* are not templates and have a requires clause
* are templates, and have a constrained parameter that depends on a
template parameter from an enclosing template

and are not a definition.

For a non-template friend function with a requires clause, if the
function is not templated then the original error message indicating
that such a function is disallowed is shown instead, as the function
will still be rejected if a definition is added.

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Sema/SemaDecl.cpp
clang/test/CXX/dcl.decl/dcl.decl.general/p4-20.cpp
clang/test/SemaTemplate/GH71595.cpp
clang/test/SemaTemplate/concepts-friends.cpp

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 36d9da9b89bab01..1eba8ab5590c521 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -560,6 +560,9 @@ Improvements to Clang's diagnostics
 - Clang now diagnoses unexpanded packs within the template argument lists of 
function template specializations.
 - Clang now diagnoses attempts to bind a bitfield to an NTTP of a reference 
type as erroneous
   converted constant expression and not as a reference to subobject.
+- Clang now diagnoses the requirement that non-template friend declarations 
with requires clauses
+  and template friend declarations with a constraint that depends on a 
template parameter from an
+  enclosing template must be a definition.
 
 
 Improvements to Clang's time-trace

diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 414779a7970ab8e..991c72cad33cad6 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -7006,6 +7006,11 @@ def err_member_decl_does_not_match : Error<
   "does not match any declaration in %1">;
 def err_friend_decl_with_def_arg_must_be_def : Error<
   "friend declaration specifying a default argument must be a definition">;
+def err_friend_decl_with_enclosing_temp_constraint_must_be_def : Error<
+  "friend declaration with a constraint that depends on an enclosing "
+  "template parameter must be a definition">;
+def err_non_temp_friend_decl_with_requires_clause_must_be_def : Error<
+  "non-template friend declaration with a requires clause must be a 
definition">;
 def err_friend_decl_with_def_arg_redeclared : Error<
   "friend declaration specifying a default argument must be the only 
declaration">;
 def err_friend_decl_does_not_match : Error<

diff  --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index c6d00ddf5c10885..bd38298a1481faa 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -10846,9 +10846,19 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator , 
DeclContext *DC,
 // Precalculate whether this is a friend function template with a 
constraint
 // that depends on an enclosing template, per [temp.friend]p9.
 if (isFriend && FunctionTemplate &&
-FriendConstraintsDependOnEnclosingTemplate(NewFD))
+FriendConstraintsDependOnEnclosingTemplate(NewFD)) {
   NewFD->setFriendConstraintRefersToEnclosingTemplate(true);
 
+  // C++ [temp.friend]p9:
+  //A friend function template with a constraint that depends on a
+  //template parameter from an enclosing template shall be a 
definition.
+  if (!D.isFunctionDefinition()) {
+Diag(NewFD->getBeginLoc(),
+ diag::err_friend_decl_with_enclosing_temp_constraint_must_be_def);
+NewFD->setInvalidDecl();
+  }
+}
+
 if (FunctionTemplate) {
   if (NewFD->isInvalidDecl())
 FunctionTemplate->setInvalidDecl();
@@ -12065,11 +12075,12 @@ bool Sema::CheckFunctionDeclaration(Scope *S, 
FunctionDecl *NewFD,
 checkThisInStaticMemberFunctionType(Method);
 }
 
-// C++20: dcl.decl.general p4:
-// The optional requires-clause ([temp.pre]) in an init-declarator or
-// member-declarator shall be present only if the declarator declares a
-// templated function ([dcl.fct]).
 if (Expr *TRC = NewFD->getTrailingRequiresClause()) {
+  // C++20: dcl.decl.general p4:
+  // The optional requires-clause ([temp.pre]) in an init-declarator or
+  // member-declarator shall be present only if the declarator declares a
+  // templated function ([dcl.fct]).
+  //
   //

[clang] [Clang][Sema] fix crash of attribute transform (PR #78088)

2024-01-16 Thread Qizhi Hu via cfe-commits


https://github.com/jcsxky updated 
https://github.com/llvm/llvm-project/pull/78088

>From d040754092faa2106dc0b63af5e8bc7d7e1e47c2 Mon Sep 17 00:00:00 2001
From: huqizhi 
Date: Sun, 14 Jan 2024 15:07:26 +0800
Subject: [PATCH 1/3] [Clang][Sema] fix crash of attribute transform

---
 clang/include/clang/AST/TypeLoc.h   |  4 
 clang/lib/Sema/TreeTransform.h  | 11 ---
 clang/test/Sema/attr-lifetimebound-no-crash.cpp | 17 +
 3 files changed, 29 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/Sema/attr-lifetimebound-no-crash.cpp

diff --git a/clang/include/clang/AST/TypeLoc.h 
b/clang/include/clang/AST/TypeLoc.h
index 471deb14aba51fc..04780fdeae3bc10 100644
--- a/clang/include/clang/AST/TypeLoc.h
+++ b/clang/include/clang/AST/TypeLoc.h
@@ -884,6 +884,10 @@ class AttributedTypeLoc : public 
ConcreteTypeLocgetEquivalentType(), getNonLocalData());
+  }
+
   /// The type attribute.
   const Attr *getAttr() const {
 return getLocalData()->TypeAttr;
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 1a1bc87d2b3203c..be5ba2000de197e 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -6124,7 +6124,11 @@ QualType 
TreeTransform::TransformFunctionProtoType(
   //   "pointer to cv-qualifier-seq X" between the optional cv-qualifer-seq
   //   and the end of the function-definition, member-declarator, or
   //   declarator.
-  Sema::CXXThisScopeRAII ThisScope(SemaRef, ThisContext, ThisTypeQuals);
+  auto *RD =
+  dyn_cast_or_null(SemaRef.getCurLexicalContext());
+  Sema::CXXThisScopeRAII ThisScope(
+  SemaRef, ThisContext == nullptr && nullptr != RD ? RD : ThisContext,
+  ThisTypeQuals);
 
   ResultType = getDerived().TransformType(TLB, TL.getReturnLoc());
   if (ResultType.isNull())
@@ -7083,8 +7087,9 @@ QualType TreeTransform::TransformAttributedType(
   modifiedType != oldType->getModifiedType()) {
 // TODO: this is really lame; we should really be rebuilding the
 // equivalent type from first principles.
-QualType equivalentType
-  = getDerived().TransformType(oldType->getEquivalentType());
+TypeLocBuilder AuxiliaryTLB;
+QualType equivalentType =
+getDerived().TransformType(AuxiliaryTLB, TL.getEquivalentTypeLoc());
 if (equivalentType.isNull())
   return QualType();
 
diff --git a/clang/test/Sema/attr-lifetimebound-no-crash.cpp 
b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
new file mode 100644
index 000..5b873fa30c6ff22
--- /dev/null
+++ b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+template
+struct Bar {
+int* data;
+
+auto operator[](const int index) const [[clang::lifetimebound]] -> 
decltype(data[index]) {
+return data[index];
+}
+};
+
+int main() {
+Bar b;
+(void)b[2];
+}
\ No newline at end of file

>From 3a87a52ada005e9fa4d77d990f5c233c646c35c0 Mon Sep 17 00:00:00 2001
From: Qizhi Hu <836744...@qq.com>
Date: Wed, 17 Jan 2024 10:03:52 +0800
Subject: [PATCH 2/3] Update TreeTransform.h

---
 clang/lib/Sema/TreeTransform.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index be5ba2000de197e..c8653017a034e71 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -7085,9 +7085,8 @@ QualType TreeTransform::TransformAttributedType(
   // FIXME: dependent operand expressions?
   if (getDerived().AlwaysRebuild() ||
   modifiedType != oldType->getModifiedType()) {
-// TODO: this is really lame; we should really be rebuilding the
-// equivalent type from first principles.
 TypeLocBuilder AuxiliaryTLB;
+AuxiliaryTLB.reserve(TL.getFullDataSize());
 QualType equivalentType =
 getDerived().TransformType(AuxiliaryTLB, TL.getEquivalentTypeLoc());
 if (equivalentType.isNull())

>From fb6aaee1834820dd4deb643c0f8f11f63020758c Mon Sep 17 00:00:00 2001
From: Qizhi Hu <836744...@qq.com>
Date: Wed, 17 Jan 2024 10:04:22 +0800
Subject: [PATCH 3/3] Update attr-lifetimebound-no-crash.cpp

---
 clang/test/Sema/attr-lifetimebound-no-crash.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/Sema/attr-lifetimebound-no-crash.cpp 
b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
index 5b873fa30c6ff22..e668a78790defd7 100644
--- a/clang/test/Sema/attr-lifetimebound-no-crash.cpp
+++ b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
@@ -14,4 +14,4 @@ struct Bar {
 int main() {
 Bar b;
 (void)b[2];
-}
\ No newline at end of file
+}

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[clang] [Clang][Sema] fix crash of attribute transform (PR #78088)

2024-01-16 Thread Qizhi Hu via cfe-commits


https://github.com/jcsxky updated 
https://github.com/llvm/llvm-project/pull/78088

>From d040754092faa2106dc0b63af5e8bc7d7e1e47c2 Mon Sep 17 00:00:00 2001
From: huqizhi 
Date: Sun, 14 Jan 2024 15:07:26 +0800
Subject: [PATCH 1/2] [Clang][Sema] fix crash of attribute transform

---
 clang/include/clang/AST/TypeLoc.h   |  4 
 clang/lib/Sema/TreeTransform.h  | 11 ---
 clang/test/Sema/attr-lifetimebound-no-crash.cpp | 17 +
 3 files changed, 29 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/Sema/attr-lifetimebound-no-crash.cpp

diff --git a/clang/include/clang/AST/TypeLoc.h 
b/clang/include/clang/AST/TypeLoc.h
index 471deb14aba51fc..04780fdeae3bc10 100644
--- a/clang/include/clang/AST/TypeLoc.h
+++ b/clang/include/clang/AST/TypeLoc.h
@@ -884,6 +884,10 @@ class AttributedTypeLoc : public 
ConcreteTypeLocgetEquivalentType(), getNonLocalData());
+  }
+
   /// The type attribute.
   const Attr *getAttr() const {
 return getLocalData()->TypeAttr;
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 1a1bc87d2b3203c..be5ba2000de197e 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -6124,7 +6124,11 @@ QualType 
TreeTransform::TransformFunctionProtoType(
   //   "pointer to cv-qualifier-seq X" between the optional cv-qualifer-seq
   //   and the end of the function-definition, member-declarator, or
   //   declarator.
-  Sema::CXXThisScopeRAII ThisScope(SemaRef, ThisContext, ThisTypeQuals);
+  auto *RD =
+  dyn_cast_or_null(SemaRef.getCurLexicalContext());
+  Sema::CXXThisScopeRAII ThisScope(
+  SemaRef, ThisContext == nullptr && nullptr != RD ? RD : ThisContext,
+  ThisTypeQuals);
 
   ResultType = getDerived().TransformType(TLB, TL.getReturnLoc());
   if (ResultType.isNull())
@@ -7083,8 +7087,9 @@ QualType TreeTransform::TransformAttributedType(
   modifiedType != oldType->getModifiedType()) {
 // TODO: this is really lame; we should really be rebuilding the
 // equivalent type from first principles.
-QualType equivalentType
-  = getDerived().TransformType(oldType->getEquivalentType());
+TypeLocBuilder AuxiliaryTLB;
+QualType equivalentType =
+getDerived().TransformType(AuxiliaryTLB, TL.getEquivalentTypeLoc());
 if (equivalentType.isNull())
   return QualType();
 
diff --git a/clang/test/Sema/attr-lifetimebound-no-crash.cpp 
b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
new file mode 100644
index 000..5b873fa30c6ff22
--- /dev/null
+++ b/clang/test/Sema/attr-lifetimebound-no-crash.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+template
+struct Bar {
+int* data;
+
+auto operator[](const int index) const [[clang::lifetimebound]] -> 
decltype(data[index]) {
+return data[index];
+}
+};
+
+int main() {
+Bar b;
+(void)b[2];
+}
\ No newline at end of file

>From 3a87a52ada005e9fa4d77d990f5c233c646c35c0 Mon Sep 17 00:00:00 2001
From: Qizhi Hu <836744...@qq.com>
Date: Wed, 17 Jan 2024 10:03:52 +0800
Subject: [PATCH 2/2] Update TreeTransform.h

---
 clang/lib/Sema/TreeTransform.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index be5ba2000de197e..c8653017a034e71 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -7085,9 +7085,8 @@ QualType TreeTransform::TransformAttributedType(
   // FIXME: dependent operand expressions?
   if (getDerived().AlwaysRebuild() ||
   modifiedType != oldType->getModifiedType()) {
-// TODO: this is really lame; we should really be rebuilding the
-// equivalent type from first principles.
 TypeLocBuilder AuxiliaryTLB;
+AuxiliaryTLB.reserve(TL.getFullDataSize());
 QualType equivalentType =
 getDerived().TransformType(AuxiliaryTLB, TL.getEquivalentTypeLoc());
 if (equivalentType.isNull())

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[llvm] [clang-tools-extra] [MLGO] Upstream the corpus extraction tooling (PR #72319)

2024-01-16 Thread Mircea Trofin via cfe-commits



@@ -0,0 +1,6 @@
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

mtrofin wrote:

why do we need `mlgo/mlgo` - could we just do `mlgo/corpus` and 
`mlgo/tests/corpus` - this leaves it open to add later non-corpus related 
things if needed.

Shouldn't the tests go under `llvm/test/tools` like the other utils? There 
should be a way to disable them if python version is under 3.8.

Also the `lit.local.cfg` should probably go through the dependency list of the 
package and skip the tests if the packages aren't available. I assume we can do 
that off `pyproject.toml`

https://github.com/llvm/llvm-project/pull/72319
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[llvm] [clang-tools-extra] [MLGO] Upstream the corpus extraction tooling (PR #72319)

2024-01-16 Thread Mircea Trofin via cfe-commits



@@ -0,0 +1,12 @@
+# MLGO Python Library
+
+This folder contains the MLGO python library. This library consists of telling

mtrofin wrote:

I wouldn't call it "the" MLGO python library, rather it's utilities for MLGO. 
Also please read the rest of the para (esp. first line)



https://github.com/llvm/llvm-project/pull/72319
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[clang-tools-extra] [llvm] [MLGO] Upstream the corpus extraction tooling (PR #72319)

2024-01-16 Thread Mircea Trofin via cfe-commits


https://github.com/mtrofin edited 
https://github.com/llvm/llvm-project/pull/72319
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[llvm] [clang-tools-extra] [MLGO] Upstream the corpus extraction tooling (PR #72319)

2024-01-16 Thread Mircea Trofin via cfe-commits


https://github.com/mtrofin commented:

I'm assuming the files were drop-in copied from google/ml-compiler-opt, so no 
need to comment there; also that we would subsequently delete them from there 
and depend on this package. 

https://github.com/llvm/llvm-project/pull/72319
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[clang] [clang] Fix assertion failure with deleted overloaded unary operators (PR #78316)

2024-01-16 Thread Shafik Yaghmour via cfe-commits



@@ -14310,8 +14310,8 @@ Sema::CreateOverloadedUnaryOp(SourceLocation OpLoc, 
UnaryOperatorKind Opc,
 PartialDiagnosticAt(OpLoc, PDiag(diag::err_ovl_deleted_oper)
<< UnaryOperator::getOpcodeStr(Opc)
<< Input->getSourceRange()),
-*this, OCD_AllCandidates, ArgsArray, UnaryOperator::getOpcodeStr(Opc),
-OpLoc);
+*this, OCD_AllCandidates, ArgsArray.slice(1),

shafik wrote:

Can you explain why `ArgArray.slice(1)` fixes the problem? It is not obvious to 
me from looking at `NoteCandidates`

https://github.com/llvm/llvm-project/pull/78316
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[clang] [coroutines][coro_lifetimebound] Detect lifetime issues with lambda captures (PR #77066)

2024-01-16 Thread Chuanqi Xu via cfe-commits


https://github.com/ChuanqiXu9 approved this pull request.

LGTM then

https://github.com/llvm/llvm-project/pull/77066
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[clang-tools-extra] [mlir] [llvm] [clang] Jf/promise interfaces (PR #78368)

2024-01-16 Thread Justin Fargnoli via cfe-commits


https://github.com/justinfargnoli updated 
https://github.com/llvm/llvm-project/pull/78368

>From 7edcf1ad0820457cc2c6530668dd30a758cf42f7 Mon Sep 17 00:00:00 2001
From: justinfargnoli 
Date: Thu, 11 Jan 2024 20:00:53 -0800
Subject: [PATCH 1/4] Declare Affine Interfaces

---
 mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/mlir/lib/Dialect/Affine/IR/AffineOps.cpp 
b/mlir/lib/Dialect/Affine/IR/AffineOps.cpp
index d5be2e906989fa..72ac9f30c2af54 100644
--- a/mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+++ b/mlir/lib/Dialect/Affine/IR/AffineOps.cpp
@@ -8,6 +8,7 @@
 
 #include "mlir/Dialect/Affine/IR/AffineOps.h"
 #include "mlir/Dialect/Affine/IR/AffineValueMap.h"
+#include "mlir/Interfaces/ValueBoundsOpInterface.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
 #include "mlir/Dialect/UB/IR/UBOps.h"
 #include "mlir/IR/AffineExprVisitor.h"
@@ -220,6 +221,9 @@ void AffineDialect::initialize() {
 #include "mlir/Dialect/Affine/IR/AffineOps.cpp.inc"
 >();
   addInterfaces();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
 }
 
 /// Materialize a single constant operation from a given attribute value with

>From fcee97c95daea0687cbbfc2e9d40e9bec089bf21 Mon Sep 17 00:00:00 2001
From: justinfargnoli 
Date: Tue, 16 Jan 2024 15:58:28 -0800
Subject: [PATCH 2/4] Declare most other dialect interface implementations

---
 mlir/lib/Dialect/Arith/IR/ArithDialect.cpp| 13 +
 .../Bufferization/IR/BufferizationDialect.cpp |  4 ++
 .../Dialect/ControlFlow/IR/ControlFlowOps.cpp |  7 +++
 mlir/lib/Dialect/GPU/IR/GPUDialect.cpp|  2 +
 mlir/lib/Dialect/Linalg/IR/LinalgDialect.cpp  |  5 ++
 mlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp  | 22 +
 mlir/lib/Dialect/SCF/IR/SCF.cpp   | 15 ++
 mlir/lib/Dialect/Shape/IR/Shape.cpp   |  3 ++
 .../SparseTensor/IR/SparseTensorDialect.cpp   | 25 ++
 mlir/lib/Dialect/Tensor/IR/TensorDialect.cpp  | 47 +++
 mlir/lib/Dialect/Vector/IR/VectorOps.cpp  | 17 +++
 11 files changed, 160 insertions(+)

diff --git a/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp 
b/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
index ed4b91cbe516c9..fea7ab05a69418 100644
--- a/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
+++ b/mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
@@ -7,7 +7,10 @@
 
//===--===//
 
 #include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/Bufferization/IR/BufferDeallocationOpInterface.h"
+#include "mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h"
 #include "mlir/Dialect/UB/IR/UBOps.h"
+#include "mlir/Interfaces/ValueBoundsOpInterface.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/DialectImplementation.h"
 #include "mlir/Transforms/InliningUtils.h"
@@ -44,6 +47,16 @@ void arith::ArithDialect::initialize() {
 #include "mlir/Dialect/Arith/IR/ArithOpsAttributes.cpp.inc"
   >();
   addInterfaces();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
 }
 
 /// Materialize an integer or floating point constant.
diff --git a/mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp 
b/mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
index e5a0c3c45b09e2..d8a38868ac862a 100644
--- a/mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
+++ b/mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
@@ -10,6 +10,7 @@
 #include "mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h"
 #include "mlir/Dialect/Bufferization/IR/Bufferization.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
+#include "mlir/Dialect/Func/IR/FuncOps.h"
 #include "mlir/Dialect/Tensor/IR/Tensor.h"
 #include "mlir/Interfaces/FunctionInterfaces.h"
 #include "mlir/Transforms/InliningUtils.h"
@@ -63,6 +64,9 @@ void mlir::bufferization::BufferizationDialect::initialize() {
 #include "mlir/Dialect/Bufferization/IR/BufferizationOps.cpp.inc"
   >();
   addInterfaces();
+  declarePromisedInterface();
+  declarePromisedInterface();
+  declarePromisedInterface();
 }
 
 LogicalResult BufferizationDialect::verifyRegionArgAttribute(
diff --git a/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp 
b/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
index fab6f341699908..6bbfb37d988549 100644
--- a/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
+++ b/mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
@@ -9,6 +9,8 @@
 #include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
 
 #include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/Bufferization/IR/BufferDeallocationOpInterface.h"
+#include "mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h"
 #include "mlir/IR/AffineExpr.h"
 #include "mlir/IR/AffineMap.h"
 #include "mlir/IR/Builders.h"
@@ -67,6 +69,11 @@ void

[clang] [coroutines][coro_lifetimebound] Detect lifetime issues with lambda captures (PR #77066)

2024-01-16 Thread Chuanqi Xu via cfe-commits



@@ -15845,8 +15845,10 @@ void Sema::CheckCoroutineWrapper(FunctionDecl *FD) {
   RecordDecl *RD = FD->getReturnType()->getAsRecordDecl();
   if (!RD || !RD->getUnderlyingDecl()->hasAttr())
 return;
-  // Allow `get_return_object()`.
-  if (FD->getDeclName().isIdentifier() &&
+  // Allow some_promise_type::get_return_object().
+  // Since we are still in the promise definition, we can only do this
+  // heuristically as the promise may not be yet associated to a coroutine.
+  if (isa(FD) && FD->getDeclName().isIdentifier() &&
   FD->getName().equals("get_return_object") && FD->param_empty())
 return;

ChuanqiXu9 wrote:

> I do not think that would work either. For example, consider TUs with only 
> promise definitions and no coroutine definitions. These attr would not be 
> available even in the end of TU.

Oh, yeah. I didn't think about modules : ).

>  @ChuanqiXu9 is it fine to add attributes to existing functions conditioned 
> on how they are used rather than how they are defined?

Then it is troublesome to use this attribute, which violates our intention.

https://github.com/llvm/llvm-project/pull/77066
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[clang] [clang][analyzer] Add function 'fscanf' to StreamChecker. (PR #78180)

2024-01-16 Thread Ben Shi via cfe-commits

=?utf-8?q?Bal=C3=A1zs_K=C3=A9ri?= 
Message-ID:
In-Reply-To: 


https://github.com/benshi001 approved this pull request.


https://github.com/llvm/llvm-project/pull/78180
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[clang-tools-extra] [llvm] [clang] [compiler-rt] [flang] workflows: Refactor release-tasks.yml (PR #69523)

2024-01-16 Thread Tom Stellard via cfe-commits


https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/69523

>From 6a7f298f403e0e454644f3d945242120f8b2b321 Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Wed, 18 Oct 2023 04:56:28 -0700
Subject: [PATCH 1/7] workflows: Refactor release-tasks.yml

* Split out the lit release job and the documentation build jobs into their
own workflow files.  This makes it possible to manually run these jobs
via workflow_dispatch.

* Improve tag/user validation and ensure it gets run for each release
task.
---
 .github/workflows/release-binaries.yml|  51 ---
 .github/workflows/release-documentation.yml   |  84 +++
 .github/workflows/release-doxygen.yml |  62 
 .github/workflows/release-lit.yml |  74 +
 .github/workflows/release-tasks.yml   | 140 ++
 .../workflows/set-release-binary-outputs.sh   |  18 +--
 llvm/utils/release/github-upload-release.py   |  22 ++-
 7 files changed, 321 insertions(+), 130 deletions(-)
 create mode 100644 .github/workflows/release-documentation.yml
 create mode 100644 .github/workflows/release-doxygen.yml
 create mode 100644 .github/workflows/release-lit.yml

diff --git a/.github/workflows/release-binaries.yml 
b/.github/workflows/release-binaries.yml
index 75d4f419ab1fdc..d8b732413d2bf6 100644
--- a/.github/workflows/release-binaries.yml
+++ b/.github/workflows/release-binaries.yml
@@ -1,20 +1,29 @@
 name: Release Binaries
 
 on:
-  push:
-tags:
-  - 'llvmorg-*'
   workflow_dispatch:
 inputs:
+  release-version:
+description: 'Release Version'
+required: true
+type: string
   upload:
 description: 'Upload binaries to the release page'
 required: true
-default: true
+default: false
 type: boolean
-  tag:
-description: 'Tag to build'
+
+  workflow_call:
+inputs:
+  release-version:
+description: 'Release Version'
 required: true
 type: string
+  upload:
+description: 'Upload binaries to the release page'
+required: true
+default: false
+type: boolean
 
 permissions:
   contents: read # Default everything to read-only
@@ -23,21 +32,26 @@ jobs:
   prepare:
 name: Prepare to build binaries
 runs-on: ubuntu-22.04
-if: github.repository == 'llvm/llvm-project'
 outputs:
-  release-version: ${{ steps.validate-tag.outputs.release-version }}
-  release: ${{ steps.validate-tag.outputs.release }}
-  build-dir: ${{ steps.validate-tag.outputs.build-dir }}
-  rc-flags: ${{ steps.validate-tag.outputs.rc-flags }}
-  ref: ${{ steps.validate-tag.outputs.ref }}
-  upload: ${{ steps.validate-tag.outputs.upload }}
+  release-version: ${{ steps.vars.outputs.release-version }}
+  release: ${{ steps.vars.outputs.release }}
+  build-dir: ${{ steps.vars.outputs.build-dir }}
+  rc-flags: ${{ steps.vars.outputs.rc-flags }}
+  ref: ${{ steps.vars.outputs.ref }}
+  upload: ${{ steps.vars.outputs.upload }}
 
 steps:
 - name: Checkout LLVM
   uses: actions/checkout@v4
 
-- name: Validate and parse tag
-  id: validate-tag
+- name: Check Permissions
+  env:
+GITHUB_TOKEN: ${{ github.token }}
+  run: |
+./llvm/utils/release/./github-upload-release.py --token 
"$GITHUB_TOKEN" --user ${{ github.actor }} check-permissions
+
+- name: Collect Variables
+  id: vars
   # In order for the test-release.sh script to run correctly, the LLVM
   # source needs to be at the following location relative to the build dir:
   # | X.Y.Z-rcN | ./rcN/llvm-project
@@ -47,15 +61,12 @@ jobs:
   # | X.Y.Z-rcN | -rc N -test-asserts
   # | X.Y.Z | -final
   run: |
-tag="${{ github.ref_name }}"
-trimmed=$(echo ${{ inputs.tag }} | xargs)
-[[ "$trimmed" != "" ]] && tag="$trimmed"
 if [ -n "${{ inputs.upload }}" ]; then
   upload="${{ inputs.upload }}"
 else
-  upload="true"
+  upload="false"
 fi
-bash .github/workflows/set-release-binary-outputs.sh "${{ github.actor 
}}" "$tag" "$upload"
+bash .github/workflows/set-release-binary-outputs.sh "${{ 
inputs.release-version }}" "$upload"
 
   # Try to get around the 6 hour timeout by first running a job to fill
   # the build cache.
diff --git a/.github/workflows/release-documentation.yml 
b/.github/workflows/release-documentation.yml
new file mode 100644
index 00..832570ed6fe93f
--- /dev/null
+++ b/.github/workflows/release-documentation.yml
@@ -0,0 +1,84 @@
+name: Release Documentation
+
+permissions:
+  contents: read
+
+on:
+  workflow_dispatch:
+inputs:
+  release-version:
+description: 'Release Version'
+required: true
+type: string
+  upload:
+description: 'Upload documentation'
+required: false
+type: boolean
+
+  workflow_call:
+

[clang] [llvm] [CloneFunction][DebugInfo] Avoid cloning DILocalVariables of inlined functions (PR #75385)

2024-01-16 Thread Davide Italiano via cfe-commits


dcci wrote:

Reverted in 
https://github.com/llvm/llvm-project/commit/b6f922fbf5e983122271aa12acb33f6172046d4d

https://github.com/llvm/llvm-project/pull/75385
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[clang] [clang] Fix parenthesized list initialization of arrays not working with `new` (PR #76976)

2024-01-16 Thread Alan Zhao via cfe-commits


https://github.com/alanzhao1 updated 
https://github.com/llvm/llvm-project/pull/76976

>From ee4e3c8634bb876166ee753a4ebcbf3c1699a175 Mon Sep 17 00:00:00 2001
From: Alan Zhao 
Date: Wed, 3 Jan 2024 12:29:21 -0800
Subject: [PATCH 1/7] [clang] Fix parenthesized list initialization of arrays
 not working with `new`

This bug is caused by parenthesized list initialization not being
implemented in `CodeGenFunction::EmitNewArrayInitializer(...)`.

Parenthesized list initialization of `struct`s  with `operator new`
already works in Clang and is not affected by this bug.

Additionally, fix the test new-delete.cpp as it incorrectly assumes that
using parentheses with operator new to initialize arrays is illegal for
C++ versions >= C++17.

Fixes #68198
---
 clang/docs/ReleaseNotes.rst|  3 +
 clang/lib/CodeGen/CGExprCXX.cpp| 17 ++---
 clang/lib/Sema/SemaExprCXX.cpp |  6 +-
 clang/test/CodeGen/paren-list-agg-init.cpp | 72 ++
 clang/test/SemaCXX/new-delete.cpp  | 20 +++---
 5 files changed, 98 insertions(+), 20 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index c7bf162426a68c..211fd62a1ee85f 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -844,6 +844,9 @@ Bug Fixes to C++ Support
 - Fix crash when parsing nested requirement. Fixes:
   (`#73112 `_)
 
+- Clang now allows parenthesized initialization of arrays in `operator new[]`.
+  Fixes: (`#68198 `_)
+
 Bug Fixes to AST Handling
 ^
 - Fixed an import failure of recursive friend class template.
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 98ae56e2df8818..72c61bfb5ec344 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -1038,11 +1038,13 @@ void CodeGenFunction::EmitNewArrayInitializer(
 return true;
   };
 
+  const InitListExpr *ILE = dyn_cast(Init);
+  const CXXParenListInitExpr *CPLIE = dyn_cast(Init);
   // If the initializer is an initializer list, first do the explicit elements.
-  if (const InitListExpr *ILE = dyn_cast(Init)) {
+  if (ILE || CPLIE) {
 // Initializing from a (braced) string literal is a special case; the init
 // list element does not initialize a (single) array element.
-if (ILE->isStringLiteralInit()) {
+if (ILE && ILE->isStringLiteralInit()) {
   // Initialize the initial portion of length equal to that of the string
   // literal. The allocation must be for at least this much; we emitted a
   // check for that earlier.
@@ -1073,7 +1075,7 @@ void CodeGenFunction::EmitNewArrayInitializer(
   return;
 }
 
-InitListElements = ILE->getNumInits();
+InitListElements = ILE ? ILE->getNumInits() : CPLIE->getInitExprs().size();
 
 // If this is a multi-dimensional array new, we will initialize multiple
 // elements with each init list element.
@@ -1101,7 +1103,8 @@ void CodeGenFunction::EmitNewArrayInitializer(
 }
 
 CharUnits StartAlign = CurPtr.getAlignment();
-for (unsigned i = 0, e = ILE->getNumInits(); i != e; ++i) {
+ArrayRef InitExprs = ILE ? ILE->inits() : CPLIE->getInitExprs();
+for (unsigned i = 0; i < InitExprs.size(); ++i) {
   // Tell the cleanup that it needs to destroy up to this
   // element.  TODO: some of these stores can be trivially
   // observed to be unnecessary.
@@ -,8 +1114,8 @@ void CodeGenFunction::EmitNewArrayInitializer(
   // FIXME: If the last initializer is an incomplete initializer list for
   // an array, and we have an array filler, we can fold together the two
   // initialization loops.
-  StoreAnyExprIntoOneUnit(*this, ILE->getInit(i),
-  ILE->getInit(i)->getType(), CurPtr,
+  Expr *IE = InitExprs[i];
+  StoreAnyExprIntoOneUnit(*this, IE, IE->getType(), CurPtr,
   AggValueSlot::DoesNotOverlap);
   CurPtr = Address(Builder.CreateInBoundsGEP(
CurPtr.getElementType(), CurPtr.getPointer(),
@@ -1122,7 +1125,7 @@ void CodeGenFunction::EmitNewArrayInitializer(
 }
 
 // The remaining elements are filled with the array filler expression.
-Init = ILE->getArrayFiller();
+Init = ILE ? ILE->getArrayFiller() : CPLIE->getArrayFiller();
 
 // Extract the initializer for the individual array elements by pulling
 // out the array filler from all the nested initializer lists. This avoids
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index 4ae04358d5df7c..71e420648ce7af 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -1947,11 +1947,11 @@ Sema::ActOnCXXNew(SourceLocation StartLoc, bool 
UseGlobal,
 }
 
 static bool isLegalArrayNewInitializer(CXXNewInitializationStyle Style,
-

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