[clang] 4431d64 - Support ExtVectorType conditional operator

Author: Min-Yih Hsu Date: 2020-06-02T16:35:42Z New Revision: 4431d64c10cb681986e752420f1136f259daa5a7 URL: https://github.com/llvm/llvm-project/commit/4431d64c10cb681986e752420f1136f259daa5a7 DIFF: https://github.com/llvm/llvm-project/commit/4431d64c10cb681986e752420f1136f259daa5a7.diff LOG:

[clang] e620bea - [M68k] Allow user to preserve certain registers

Author: Min-Yih Hsu Date: 2021-05-20T13:57:22-07:00 New Revision: e620bea21199791513f3193a71b819b20a707ab1 URL: https://github.com/llvm/llvm-project/commit/e620bea21199791513f3193a71b819b20a707ab1 DIFF: https://github.com/llvm/llvm-project/commit/e620bea21199791513f3193a71b819b20a707ab1.diff

[clang] dccf5c7 - [M68k] Support for inline asm operands w/ simple constraints

Author: Min-Yih Hsu Date: 2021-05-20T14:00:09-07:00 New Revision: dccf5c7dfb9e68f8750947f5c10ad3227cd92b50 URL: https://github.com/llvm/llvm-project/commit/dccf5c7dfb9e68f8750947f5c10ad3227cd92b50 DIFF: https://github.com/llvm/llvm-project/commit/dccf5c7dfb9e68f8750947f5c10ad3227cd92b50.diff

[clang] 6685a3f - [cfe] Support target-specific escaped character in inline asm

Author: Min-Yih Hsu Date: 2021-05-24T21:39:21-07:00 New Revision: 6685a3f3e4c497a3a0fd06aa4e77cb442325d1ba URL: https://github.com/llvm/llvm-project/commit/6685a3f3e4c497a3a0fd06aa4e77cb442325d1ba DIFF: https://github.com/llvm/llvm-project/commit/6685a3f3e4c497a3a0fd06aa4e77cb442325d1ba.diff

[clang] 5509748 - [cfe][driver][M68k](8/8) Clang driver support

Author: Min-Yih Hsu Date: 2021-03-08T12:30:57-08:00 New Revision: 5509748f2ce5e06bda7da754297d09a0e68a1f30 URL: https://github.com/llvm/llvm-project/commit/5509748f2ce5e06bda7da754297d09a0e68a1f30 DIFF: https://github.com/llvm/llvm-project/commit/5509748f2ce5e06bda7da754297d09a0e68a1f30.diff

[clang] 5eb7a58 - [cfe][M68k](7/8) Clang basic support

Author: Min-Yih Hsu Date: 2021-03-08T12:30:57-08:00 New Revision: 5eb7a5814a5c629378ba2a4a45fc65cd7f183c9c URL: https://github.com/llvm/llvm-project/commit/5eb7a5814a5c629378ba2a4a45fc65cd7f183c9c DIFF: https://github.com/llvm/llvm-project/commit/5eb7a5814a5c629378ba2a4a45fc65cd7f183c9c.diff

[clang] 59437cb - [M68k] Fix empty builtin va_list kind

Author: Min-Yih Hsu Date: 2021-04-16T11:09:22-07:00 New Revision: 59437cb7d7c30054f0e77b2369c0aeffed3ccb14 URL: https://github.com/llvm/llvm-project/commit/59437cb7d7c30054f0e77b2369c0aeffed3ccb14 DIFF: https://github.com/llvm/llvm-project/commit/59437cb7d7c30054f0e77b2369c0aeffed3ccb14.diff

[clang-tools-extra] Add flags to dump IR to a file before and after LLVM passes (PR #65179)

@@ -830,6 +831,182 @@ void PrintIRInstrumentation::registerCallbacks( } } +void DumpIRInstrumentation::registerCallbacks( +PassInstrumentationCallbacks ) { + + if (!(shouldDumpBeforeSomePass() || shouldDumpAfterSomePass())) +return; + + this->PIC = + +

[clang] Add flags to dump IR to a file before and after LLVM passes (PR #65179)

@@ -830,6 +831,182 @@ void PrintIRInstrumentation::registerCallbacks( } } +void DumpIRInstrumentation::registerCallbacks( +PassInstrumentationCallbacks ) { + + if (!(shouldDumpBeforeSomePass() || shouldDumpAfterSomePass())) +return; + + this->PIC = + +

[clang] [NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (PR #66295)

https://github.com/mshockwave approved this pull request. https://github.com/llvm/llvm-project/pull/66295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 230558e - [Clang][M68k] Use `DefineStd` for target-specific macros

Author: Min-Yih Hsu Date: 2023-09-01T23:25:08-07:00 New Revision: 230558e444c2e1af8f34f99e59433a3fb87ed758 URL: https://github.com/llvm/llvm-project/commit/230558e444c2e1af8f34f99e59433a3fb87ed758 DIFF: https://github.com/llvm/llvm-project/commit/230558e444c2e1af8f34f99e59433a3fb87ed758.diff

[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/70242 Use ".ld.stats" instead of ".stats" for stats file generated by LTO backend. The new extension makes it easier to search for LTO'd stats file and be consistent with LTO'd optimization remarks files' naming

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/71197 Previously, if a linker flag (i.e. -Wl) is presented before any input filenames, Gnu driver would use the InputInfo object of that flag to generate stats filename for LTO backend, causing an empty filename.

[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/70242 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)

mshockwave wrote: > I can understand the rationale, but adding this special case feels stranger > to me.. I'm fine with not having a special file extension for LTO'd stats file, hence closing this PR. That said, it would be really helpful if you could help me to review a related PR #71197 .

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

@@ -535,7 +535,15 @@ void tools::gnutools::Linker::ConstructJob(Compilation , const JobAction , if (D.isUsingLTO()) { assert(!Inputs.empty() && "Must have at least one input."); -addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0], +// Find the first

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/71197 >From 8d5acb56b364648d1abd6bfff6815af71e131d6e Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Thu, 2 Nov 2023 17:26:17 -0700 Subject: [PATCH 1/2] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

@@ -20,6 +20,8 @@ // CHECK-INVALID: invalid value 'bla' in '-save-stats=bla' // RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO +// Previously `-plugin-opt=stats-file` would use empty

[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/71197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/8] [RISCV][GISel] Add ISel supports for SHXADD from Zba

[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/8] [RISCV][GISel] Add ISel supports for SHXADD from Zba

[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/7] [RISCV][GISel] Add ISel supports for SHXADD from Zba

[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/7] [RISCV][GISel] Add ISel supports for SHXADD from Zba

[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/67863 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/6] [RISCV][GISel] Add ISel supports for SHXADD from Zba

[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/67863 >From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 29 Sep 2023 15:17:43 -0700 Subject: [PATCH 1/6] [RISCV][GISel] Add ISel supports for SHXADD from Zba

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/69747 Translate `-fglobal-isel` to `-plugin-opt=-global-isel=1`. >From 8abc9204d4148f1b224623ac54d5f58e2ab04e6b Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 20 Oct 2023 11:03:30 -0700 Subject: [PATCH]

[clang] fd4f962 - [Clang][M68k] Add Clang support for the new M68k_RTD CC

Author: Min-Yih Hsu Date: 2023-10-15T16:13:43-07:00 New Revision: fd4f96290ac99bf8b9284d3b32743cac0bb135ea URL: https://github.com/llvm/llvm-project/commit/fd4f96290ac99bf8b9284d3b32743cac0bb135ea DIFF: https://github.com/llvm/llvm-project/commit/fd4f96290ac99bf8b9284d3b32743cac0bb135ea.diff

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/69747 >From 8abc9204d4148f1b224623ac54d5f58e2ab04e6b Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Fri, 20 Oct 2023 11:03:30 -0700 Subject: [PATCH 1/2] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/69747 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)

@@ -694,6 +694,16 @@ void tools::addLTOOptions(const ToolChain , const ArgList , CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) + ParallelismOpt + Parallelism)); + // Pass down GlobalISel options. + if (Arg *A =

[clang] effd75b - [M68k][Driver] Rename target features and macros test files

Author: Min-Yih Hsu Date: 2022-10-25T11:24:48-07:00 New Revision: effd75bda4b1a9b26e554c1cda3e3b4c72fa0aa8 URL: https://github.com/llvm/llvm-project/commit/effd75bda4b1a9b26e554c1cda3e3b4c72fa0aa8 DIFF: https://github.com/llvm/llvm-project/commit/effd75bda4b1a9b26e554c1cda3e3b4c72fa0aa8.diff

[clang] 7335cd0 - [M68k] Add support for basic memory constraints in inline asm

Author: Min-Yih Hsu Date: 2023-03-08T13:52:34-08:00 New Revision: 7335cd05137076c69ce4716ac8f30a99fc95c406 URL: https://github.com/llvm/llvm-project/commit/7335cd05137076c69ce4716ac8f30a99fc95c406 DIFF: https://github.com/llvm/llvm-project/commit/7335cd05137076c69ce4716ac8f30a99fc95c406.diff

[clang] 9b61708 - [M68k] Add basic Clang support for M68881/2

Author: Min-Yih Hsu Date: 2023-04-24T09:32:49-07:00 New Revision: 9b617081420dc579c52b53a4d8929b206b206eed URL: https://github.com/llvm/llvm-project/commit/9b617081420dc579c52b53a4d8929b206b206eed DIFF: https://github.com/llvm/llvm-project/commit/9b617081420dc579c52b53a4d8929b206b206eed.diff

[flang] [clang-tools-extra] [compiler-rt] [llvm] [clang] [Legalizer] Expand fmaximum and fminimum (PR #67301)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/67301 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[compiler-rt] [flang] [clang-tools-extra] [clang] [llvm] [Legalizer] Expand fmaximum and fminimum (PR #67301)

@@ -523,9 +523,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine , setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom); -if (Subtarget.hasStdExtZfa()) +if (Subtarget.hasStdExtZfa()) {

[clang-tools-extra] [llvm] [clang] [flang] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)

https://github.com/mshockwave approved this pull request. LGTM. It will be great if you could add RISCV test too, but please don't let this block you. https://github.com/llvm/llvm-project/pull/67301 ___ cfe-commits mailing list

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From b4e14471727c59634daeec58ff60b8c32c5f2961 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/2] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -92,6 +92,7 @@ on support follow. ``M``Supported ``Smaia``Supported ``Ssaia``Supported + ``Smepmp`` Supported mshockwave wrote: Done. https://github.com/llvm/llvm-project/pull/78489

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -56,6 +56,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"smaia", {1, 0}}, {"ssaia", {1, 0}}, +{"smepmp", {1, 0}}, mshockwave wrote: Done. https://github.com/llvm/llvm-project/pull/78489

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From b4e14471727c59634daeec58ff60b8c32c5f2961 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From 84783b38744bc2bb46cb8d62db206864709a5e22 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/2] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

mshockwave wrote: > Needs to be added to RISCVUsage.rst, and probably a note in the release docs > as well. It's done now. https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -716,6 +716,13 @@ def FeatureStdExtSmaia "AIA specifies for a hart, over all privilege levels.)", []>; +def FeatureStdExtSmepmp mshockwave wrote: > Can we keep smaia and ssaia together since they come from the

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From a69c187716153c90f50b2859212a0e5af9102fd1 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -722,6 +722,11 @@ def FeatureStdExtSsaia "'Ssaia' (Advanced Interrupt Architecture Supervisor " "Level)", []>; +def FeatureStdExtSmepmp +: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", +

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489 >From ab316ea2c76320ec2f044c43bb9f6ed82f6802c3 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/4] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -1047,6 +1048,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s // CHECK-SSAIA-EXT: __riscv_ssaia 100{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -116,6 +116,7 @@ // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} +// CHECK-NOT: __riscv_smepmp {{.*$}} mshockwave wrote: It's fixed now. https://github.com/llvm/llvm-project/pull/78489

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

https://github.com/mshockwave approved this pull request. Thank you! LGTM https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

mshockwave wrote: Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing between a7 and sp? Also, could you add a simple test? https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [clang-tools-extra] [flang] [llvm] [mlir] [polly] [test]: fix filecheck annotation typos (PR #91854)

@@ -96,7 +96,7 @@ for.end: ; preds = %for.end.loopexit, % ; Specify a smaller minimum VF (via `-epilogue-vectorization-minimum-VF=4`) and ; make sure the epilogue gets vectorized in that case. -; CHECK-MIN-D-LABLE: @f3 +;

[clang] [clang-tools-extra] [flang] [llvm] [mlir] [polly] [test]: fix filecheck annotation typos (PR #91854)

@@ -335,7 +335,7 @@ define void @cannot_sink_reduction(i32 %x, ptr %ptr, i64 %tc) { -; CHECK-NET: ret void +; CHECK-NEXT:ret void mshockwave wrote: please remove this line as it has been covered by line 333 (which was probably generated by UTC).