[PATCH] D129562: [SystemZ] Enable `-mtune=` option in clang.

uweigand accepted this revision. uweigand added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129562/new/ https://reviews.llvm.org/D129562

[PATCH] D133338: [clang][PowerPC] PPC64 VAArg use coerced integer type for direct aggregate fits in register

uweigand added a comment. I think it is correct to implement this in Clang. Note that on SystemZ (another big-endian platform), we also implement this in `EmitVAArg`. Of course the details are different since we're not using `emitVoidPtrVAArg` on that platform. However, I'm not sure if

[PATCH] D136145: [IR][RFC] Restrict read only when cache type of llvm.prefetch is instruction

uweigand added inline comments. Comment at: llvm/test/CodeGen/SystemZ/prefetch-01.ll:18 -; Check that instruction write prefetches are ignored. -define dso_local void @f2(ptr %ptr) { -; CHECK-LABEL: f2: -; CHECK-NOT: %r2 -; CHECK: br %r14 - call void @llvm.prefetch(ptr %ptr,

[PATCH] D136040: [X86] Support PREFETCHI instructions

uweigand added a comment. In D136040#3862225 , @pengfei wrote: > 3. Add semacheck for prefetch write to instruction cache; > > I think the affected ARM and SystemZ tests are not valid before. Could > @t.p.northover and @uweigand help to have a look?

[PATCH] D136040: [X86] Support PREFETCHI instructions

uweigand added a comment. In D136040#3862386 , @pengfei wrote: > Sure, it is possible. But at least for now, there's no real target requires > it. Checked with `grep -rwn 'llvm.prefetch.*i32 0\s*)' llvm/test/CodeGen/`. But that's just within the LLVM

[PATCH] D133338: [clang][PowerPC] PPC64 VAArg use coerced integer type for direct aggregate fits in register

uweigand added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:5471 +if (CoerceTy->isIntegerTy() && CoerceTy->getIntegerBitWidth() < GPRBits) + ForceRightAdjust = true; + } Are all these checks really necessary here? This seems

[PATCH] D133338: [clang][PowerPC] PPC64 VAArg use coerced integer type for direct aggregate fits in register

uweigand added a comment. This LGTM now, but maybe some of the PowerPC reviewers would like to comment as well. @nemanjai ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D18/new/ https://reviews.llvm.org/D18

[PATCH] D139444: [ZOS] Convert tests to check 'target={{.*}}-zos'

uweigand added a comment. In D139444#3983679 , @uweigand wrote: > In D139444#3982205 , @probinson > wrote: > >> If you can tell me the `platform.system()` value to look for to detect z/OS, >> I can do that. > >

[PATCH] D139444: [ZOS] Convert tests to check 'target={{.*}}-zos'

uweigand accepted this revision. uweigand added a comment. This revision is now accepted and ready to land. LGTM, thanks! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139444/new/ https://reviews.llvm.org/D139444 ___ cfe-commits mailing list

[PATCH] D139444: [ZOS] Convert tests to check 'target={{.*}}-zos'

uweigand added a comment. In D139444#3982205 , @probinson wrote: > If you can tell me the `platform.system()` value to look for to detect z/OS, > I can do that. I don't know - this value is defined by the Python implementation on z/OS. On most

[PATCH] D139444: [ZOS] Convert tests to check 'target={{.*}}-zos'

uweigand added a comment. In D139444#3975182 , @probinson wrote: > The changes in this patch assume that there aren't any possible suffixes > after the `-zos` part of the triple (no version numbers, like you might find > with darwin or macos, and

[PATCH] D149548: [IR] Update to use new shufflevector semantics

uweigand added a comment. In D149548#4413639 , @nlopes wrote: > If a vector is fully initialized with `insertvector` (i.e., one operation per > index), then the value of the base vector is irrelevant. It can be poison. > Poison in vectors is

[PATCH] D149548: [IR] Update to use new shufflevector semantics

uweigand added a comment. So the semantics of the `vec_promote(a, b)` intrinsic is defined as: > Returns a vector with a in element position b. The result is a vector with a > in element position b. [...] The other elements of the vector are undefined. This is currently implemented by using

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