[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:194 HasV = true; -else if (Feature == "+experimental-zfh") + HasRISCVVTypes = true; +} else if (Feature == "+experimental-zfh") HasRISCVVTypes is an undefined

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 317916. khchen added a comment. address reviewer's suggestion, do not include test generator related part. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files:

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added a comment. Really thanks for @jrtc27 and @craig.topper 's review suggestions. Before I upload the patch, I would want to discuss about the test generator, because if we don't want to upstream it, I don't need to fix some issues which are addressed by reivewers. @asb @jrtc27

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 318102. khchen marked 74 inline comments as done. khchen added a comment. 1. use exponent LMUL. 2. address @Paul-C-Anagnostopoulos 's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added a comment. marked some inline comments as done except the test generator related part. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 ___

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 317919. khchen added a comment. apply clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: clang/include/clang/Basic/BuiltinsRISCV.def

[PATCH] D94403: [RISCV] Implement new architecture extension macros

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 ___

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 319000. khchen marked 7 inline comments as done. khchen added a comment. 1. address @HsiangKai's comments 2. remove test generator to make td simpler. 3. remove MangledSuffix, it should be MangledName Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:161 + // This builtin is valid for the given exponental LMULs. + list ELMUL = [0, 1, 2, 3, -1, -2, -3]; + HsiangKai wrote: > EMUL according to specification. Here ELMUL means

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 318423. khchen added a comment. 1. address @craig.topper's comment. 2. rewrite script as python. I'm still have no idea to make generating tests mechanism be more elegant... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 318447. khchen marked 2 inline comments as done. khchen added a comment. 1. do not need to manually define new op in gen-rvv-tests.py. 2. do not need to manually add new op define in ALL marco. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen marked 7 inline comments as done. khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:191 +defvar suffix = s_p[1]; +defvar prototype = s_p[2]; + Paul-C-Anagnostopoulos wrote: > Well now, thanks for

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, HsiangKai, evandro, liaolucy, arcbbb, monkchiang. Herald added subscribers: dexonsmith, NickHung, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:10 + +// ASM-NOT: warning +#include jrtc27 wrote: > Asm checks are discouraged in Clang. If you want to check for Clang warnings, > use -verify, and in this

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 319488. khchen marked 21 inline comments as done. khchen added a comment. 1. address @jrtc27's comments. I really appreciate your help very much. 2. use downstream test generator and move all tests to rvv-intrinsics-generic and rvv-intrinsics. Repository:

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#2762120 , @jrtc27 wrote: > In D71387#2762115 , @khchen wrote: > >> In D71387#1820995 , @efriedma wrote: >> >>> Okay. Please let me know if

[PATCH] D102051: [RISCV] Consider scalar types for required extensions.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. Good catch! LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102051/new/ https://reviews.llvm.org/D102051

[PATCH] D102086: [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. Good catch, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102086/new/ https://reviews.llvm.org/D102086

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen updated this revision to Diff 345712. khchen added a comment. Herald added a subscriber: vkmr. Pass -target-abi option into LTO codegenerator base on D102582 patch. please see D102582 for more detal. Repository: rG

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#1820995 , @efriedma wrote: > Okay. Please let me know if you want me to review anything. Hi all, We had encoded the target-abi into module now, but I feel it does not make sense to support overwrite ABI option and

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen updated this revision to Diff 348870. khchen added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Revert to previous revision Diff 347356 and add empty module flag could be empty in test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen created this revision. khchen added reviewers: jrtc27, asb, luismarques. Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng,

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102582/new/ https://reviews.llvm.org/D102582 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen updated this revision to Diff 356425. khchen added a comment. Update test cases. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71387/new/ https://reviews.llvm.org/D71387 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen added inline comments. Comment at: llvm/test/CodeGen/RISCV/module-target-abi-tests.ll:5 +; RUN: cat %s > %t.emptyabi +; RUN: echo '!0 = !{i32 1, !"target-abi", !""}' >> %t.emptyabi +; RUN: llc -mtriple=riscv32 < %t.emptyabi -o /dev/null jrtc27 wrote: >

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 357148. khchen added a comment. Herald added subscribers: llvm-commits, dexonsmith, hiraditya. Herald added a project: LLVM. address jrtc27's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

khchen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:195 if (MArch.startswith_insensitive("rv32")) { // FIXME: parse `March` to find `D` extension properly if (MArch.substr(4).contains_insensitive("d") || I think

[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1148 +if (HasPolicy) { + ProtoMaskSeq.push_back("z"); +} maybe the policy argument should be a constant value ("Kz")? Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

khchen added a comment. This all looks good to me except adding back the asm check. BTW, do we need to attach the half-precision floating point spec link? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105001/new/ https://reviews.llvm.org/D105001

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen updated this revision to Diff 357420. khchen added a comment. rebase on D102582 report a error if target-abi module flag is is empty. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102582/new/

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c:13 +// ASM-NOT: warning #include HsiangKai wrote: > craig.topper wrote: > > Do you plan to bring back the ASM check for all tests? > No, I will remove it.

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

khchen added inline comments. Comment at: clang/test/Driver/riscv-abi.c:68 -// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -march=rv64d -mabi=lp64d 2>&1 \ +// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -march=rv64ifd -mabi=lp64d 2>&1 \ // RUN: |

[PATCH] D100821: [RISCV] Implement the vmmv.m/vmnot.m builtin.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100821/new/ https://reviews.llvm.org/D100821

[PATCH] D100824: [RISCV] Implement the vwcvt{u}.x.x.v/vncvt.x.x.w builtin.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100824/new/ https://reviews.llvm.org/D100824

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

khchen added a comment. @thakis https://reviews.llvm.org/D100611 had landed, could you check your bot to see the cycle time? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99741/new/ https://reviews.llvm.org/D99741

[PATCH] D101700: [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Thanks for improvement! Comment at: clang/include/clang/Basic/riscv_vector.td:192 - // When the order of the parameters of clang builtin do not match the order of

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

khchen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:180 + // as described in RISC-V User-Level ISA 20191213. SmallVector Split; Exts.split(Split, StringRef("_")); If we want to update the arch string rules to ISA 20191213,

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. Herald added a subscriber: vkmr. Hi, I would like to add ilp32e ABI support in llvm Is there anyone working on this? It seem the one thing missed is ilp32e ABI should disallow D ISA extension. Is there anything else? Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2 -RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 322300. khchen added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: clang/include/clang/Basic/BuiltinsRISCV.def

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 322297. khchen marked 3 inline comments as done. khchen added a comment. 1. address Jim's comment. 2. remove suffix `_vl` according by https://github.com/riscv/rvv-intrinsic-doc/pull/64 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:89 +#define BUILTIN(ID, TYPE, ATTRS) \ + {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#include "clang/Basic/BuiltinsRISCV.def"

[PATCH] D99151: [RISCV][Clang] Add RVV vleff intrinsic functions.

khchen added a comment. maybe we could merge different test into one vleff.c? Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vle16ff.c:9 +// RUN: -target-feature +experimental-zfh -target-feature +m -fallow-half-arguments-and-returns -Werror -Wall -S -o - %s >/dev/null

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

khchen updated this revision to Diff 332852. khchen added a comment. Fix unintended change. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99189/new/ https://reviews.llvm.org/D99189 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

This revision was automatically updated to reflect the committed changes. Closed by commit rG88c2d4c8eb0e: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions. (authored by khchen). Changed prior to commit: https://reviews.llvm.org/D98848?vs=332660=332850#toc Repository: rG LLVM

[PATCH] D99082: [RISCV][NFC] Fix RVV intrinsic tests.

khchen added a comment. In D99082#2643322 , @jrtc27 wrote: > Most likely because you're adding assembly tests in Clang, which won't work > if the backend isn't present (and needs a REQUIRES line). Assembly tests in > Clang are generally bad practice and

[PATCH] D99082: [RISCV][NFC] Fix RVV intrinsic tests.

This revision was automatically updated to reflect the committed changes. Closed by commit rGab082b582dd0: [RISCV][NFC] Fix RVV intrinsic tests. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99082/new/

[PATCH] D99082: [RISCV][NFC] Fix RVV intrinsic tests.

khchen added a comment. I need to take a look why Buildbot run failed: https://lab.llvm.org/buildbot/#/builders/139/builds/1615 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99082/new/ https://reviews.llvm.org/D99082

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

khchen marked 3 inline comments as done. khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c:11 // ASM-NOT: warning -#include +#include liaolucy wrote: > riscv_vector_overloaded.h ? Sorry, I forget to have a

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

khchen updated this revision to Diff 332660. khchen marked 8 inline comments as done. khchen added a comment. 1. address Craig's comments. 2. add 'REQUIRES: riscv-registered-target' for tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

khchen updated this revision to Diff 333298. khchen marked an inline comment as done. khchen added a comment. Emit riscv_vector_overloaded.h into riscv_vector.h Remove riscv_vector_overloaded.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D99151: [RISCV][Clang] Add RVV vleff intrinsic functions.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vle16ff.c:9 +// RUN: -target-feature +experimental-zfh -target-feature +m -fallow-half-arguments-and-returns -Werror -Wall -S -o - %s >/dev/null 2>%t +// RUN: FileCheck --check-prefix=ASM

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

This revision was automatically updated to reflect the committed changes. Closed by commit rG821547cabb58: [RISCV][Clang] Update new overloading rules for RVV intrinsics. (authored by khchen). Changed prior to commit: https://reviews.llvm.org/D99189?vs=333486=333727#toc Repository: rG LLVM

[PATCH] D99524: [RISCV][Clang] Add some RVV Integer intrinsic functions.

khchen updated this revision to Diff 334164. khchen added a comment. 1. Address Craig's comments. 2. I didn't add common class for shift instruction. I will add it when we add other shift instruction which have the same argments. Does it make sense? Repository: rG LLVM Github Monorepo

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

khchen updated this revision to Diff 334178. khchen added a comment. Create a common class. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99526/new/ https://reviews.llvm.org/D99526 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99528: [RISCV][Clang] Add more RVV Integer intrinsic functions.

khchen updated this revision to Diff 334188. khchen added a comment. Create a common class. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99528/new/ https://reviews.llvm.org/D99528 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99610: [RISCV][Clang] Add all RVV Fixed-Point Arithmetic intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99528: [RISCV][Clang] Add more RVV Integer intrinsic functions.

khchen updated this revision to Diff 334205. khchen added a comment. [NFC] move class position. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99528/new/ https://reviews.llvm.org/D99528 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

khchen updated this revision to Diff 334659. khchen added a comment. rebase and refine multiclass. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99669/new/ https://reviews.llvm.org/D99669 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99668: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99524: [RISCV][Clang] Add some RVV Integer intrinsic functions.

This revision was automatically updated to reflect the committed changes. Closed by commit rG66c05609e0d5: [RISCV][Clang] Add some RVV Integer intrinsic functions. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99524/new/

[PATCH] D99525: [RISCV][Clang] Add RVV vnsra, vnsrl and vwmul intrinsic functions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG0a18ea01f197: [RISCV][Clang] Add RVV vnsra, vnsrl and vwmul intrinsic functions. (authored by khchen). Changed prior to commit:

[PATCH] D99528: [RISCV][Clang] Add more RVV Integer intrinsic functions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGfe252b509ee6: [RISCV][Clang] Add more RVV Integer intrinsic functions. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D99610: [RISCV][Clang] Add all RVV Fixed-Point Arithmetic intrinsic functions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf2a3601aa5a5: [RISCV][Clang] Add all RVV Fixed-Point Arithmetic intrinsic functions. (authored by khchen). Repository: rG LLVM Github Monorepo

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c:35 +vint16mf4_t test_vwadd_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) { + return vwadd_vx(op1, op2, vl); +} khchen wrote: > craig.topper wrote: > > Why do

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

khchen updated this revision to Diff 333486. khchen added a comment. remove riscv_vector_overloaded.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99189/new/ https://reviews.llvm.org/D99189 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99524: [RISCV][Clang] Add some RVV Integer intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99525: [RISCV][Clang] Add RVV vnsra, vnsrl and vwmul intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99528: [RISCV][Clang] Add more RVV Integer intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99524: [RISCV][Clang] Add some RVV Integer intrinsic functions.

khchen added a comment. So sorry.. those huge tests make the browser so slowly, should I split them in the different patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99524/new/ https://reviews.llvm.org/D99524

[PATCH] D99668: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions.

khchen updated this revision to Diff 334644. khchen added a comment. Fix vfrdiv. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99668/new/ https://reviews.llvm.org/D99668 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c:35 +vint16mf4_t test_vwadd_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) { + return vwadd_vx(op1, op2, vl); +} craig.topper wrote: > Why do scalars require

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

khchen updated this revision to Diff 334647. khchen added a comment. Address Craig's comments. Sorry for a lot of typos. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99526/new/ https://reviews.llvm.org/D99526 Files:

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

khchen updated this revision to Diff 334648. khchen added a comment. update missed part for Log2LMUL. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99526/new/ https://reviews.llvm.org/D99526 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

khchen marked 2 inline comments as done. khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:315 +multiclass RVVFloatingWidenTerBuiltinSet { + let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in { +defm "" :

[PATCH] D99964: [RISCV][Clang] Add all RVV Reduction intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D99965: [RISCV][Clang] Add more RVV load/store intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy, jrtc27. Herald added subscribers: vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGd6a0560bf258: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. (authored by khchen). Changed prior to commit:

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

khchen marked 6 inline comments as done. khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:689 + skew = 1; +for (unsigned i = 0; i < PermuteOperands.size(); ++i) { + if (i != PermuteOperands[i]) rogfer01 wrote: >

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

khchen created this revision. khchen added reviewers: craig.topper, jrtc27, rogfer01, frasercrmck, HsiangKai, evandro. Herald added subscribers: vkmr, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck,

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen updated this revision to Diff 331267. khchen marked 2 inline comments as done. khchen added a comment. 1. address Craig's comments. 2. update test by using 2>&1 instead of 2>%t Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96843/new/

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:687 + +unsigned Skew = 0; +if (HasMaskedOffOperand) craig.topper wrote: > ``` > unsigned Skew = HasMaskedOffOperand ? 1 : 0; > ``` > > unless this needs to get more

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen marked an inline comment as done. khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:169 +Builder.defineMacro("__rvv_e64", "3"); +Builder.defineMacro("__rvv_e128", "4"); + craig.topper wrote: > Are intending to support

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added a comment. @jrtc27, please advise if there is anything more should to be changed, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 ___

[PATCH] D99082: [RISCV][NFC] Fix RVV intrinsic tests.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, HsiangKai, evandro, liaolucy. Herald added subscribers: vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng,

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

khchen updated this revision to Diff 332307. khchen added a comment. Remove half type in TypeList. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98848/new/ https://reviews.llvm.org/D98848 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

khchen updated this revision to Diff 332341. khchen added a comment. update tests, remove target-feature zfh. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98848/new/ https://reviews.llvm.org/D98848 Files:

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

This revision was automatically updated to reflect the committed changes. Closed by commit rG95c0125f2bc6: [Clang][RISCV] Add rvv vsetvl and vsetvlmax intrinsic functions. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

khchen marked an inline comment as done. khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:700 +for (auto Idx : CTypeOrder) { + if (Seen.count(Idx)) +PrintFatalError( craig.topper wrote: > You can use > > ``` > if

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 327363. khchen marked 11 inline comments as done. khchen added a comment. address @jrtc27's comments, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files:

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326107. khchen marked 2 inline comments as done. khchen added a comment. address https://reviews.llvm.org/D95016?id=324197#inline-912573 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326104. khchen marked 10 inline comments as done. khchen added a comment. 1. Rebase 2. Address Craig's comments. 3. Change the operand orders of builtin to the same order of IR intrinsics. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:899 +// (operand) in ProtoSeq. ProtoSeq[0] is output operand. +SmallVector ProtoSeq; +const StringRef Primaries("evwqom0ztc"); craig.topper wrote: > I think this is

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen updated this revision to Diff 326612. khchen marked 3 inline comments as done. khchen added a comment. address Craig's comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96843/new/ https://reviews.llvm.org/D96843 Files:

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1052 uint8_t PrevExt = (*Defs.begin())->getRISCV_Extensions(); - bool NeedEndif = emitExtDefStr(PrevExt, OS); + bool NeedEndif = + (*Defs.begin())->hasAutoDef() ? emitExtDefStr(PrevExt,

[PATCH] D97826: [RISCV] Make use of the required features in BuiltinInfo to store that V extension builtins require 'experimental-v'.

khchen added a comment. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97826/new/ https://reviews.llvm.org/D97826 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

khchen added a comment. I didn't check why I got error in Failed Tests (1): Clang :: Driver/riscv64-toolchain.c Could you please double check it? Thanks! Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1599 +static std::string getGCCPath(const Driver , const ArgList ) {

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