[clang] 4bc8dbe - [RISCV] Add SiFive cores E and S series

2021-09-09 Thread Alexander Pivovarov via cfe-commits 

Author: Alexander Pivovarov
Date: 2021-09-08T23:59:04-07:00
New Revision: 4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6

URL: 
https://github.com/llvm/llvm-project/commit/4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6
DIFF: 
https://github.com/llvm/llvm-project/commit/4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6.diff

LOG: [RISCV] Add SiFive cores E and S series

Add SiFive cores E20, E21, E24, E34, S21, S54 and S76

Differential Revision: https://reviews.llvm.org/D109260

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/RISCVTargetParser.def
llvm/lib/Target/RISCV/RISCV.td

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 6caf24ca4ef77..56f91b4e5877f 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -73,7 +73,14 @@ Modified Compiler Flags
 
 - Support has been added for the following processors (``-mcpu`` identifiers 
in parentheses):
 
+  - RISC-V SiFive E20 (``sifive-e20``).
+  - RISC-V SiFive E21 (``sifive-e21``).
+  - RISC-V SiFive E24 (``sifive-e24``).
+  - RISC-V SiFive E34 (``sifive-e34``).
+  - RISC-V SiFive S21 (``sifive-s21``).
   - RISC-V SiFive S51 (``sifive-s51``).
+  - RISC-V SiFive S54 (``sifive-s54``).
+  - RISC-V SiFive S76 (``sifive-s76``).
 
 Removed Compiler Flags
 -

diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 4c26bf8751c27..444b0aef623a1 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,39 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with default march
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck 
-check-prefix=MCPU-SIFIVE-E20 %s
+// MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20"
+// MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SIFIVE-E20: "-target-abi" "ilp32"
+
+// mcpu with default march
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck 
-check-prefix=MCPU-SIFIVE-E21 %s
+// MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21"
+// MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+c"
+// MCPU-SIFIVE-E21: "-target-abi" "ilp32"
+
+// mcpu with default march
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck 
-check-prefix=MCPU-SIFIVE-E24 %s
+// MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24"
+// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f"
+// MCPU-SIFIVE-E24: "-target-feature" "+c"
+// MCPU-SIFIVE-E24: "-target-abi" "ilp32"
+
+// mcpu with default march
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck 
-check-prefix=MCPU-SIFIVE-E34 %s
+// MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34"
+// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f"
+// MCPU-SIFIVE-E34: "-target-feature" "+c"
+// MCPU-SIFIVE-E34: "-target-abi" "ilp32"
+
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
+// MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21"
+// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"
+
 // mcpu with mabi option
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
 // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
@@ -52,6 +85,20 @@
 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
 
+// mcpu with default march
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck 
-check-prefix=MCPU-SIFIVE-S54 %s
+// MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54"
+// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S54: "-target-abi" "lp64d"
+
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck 
-check-prefix=MCPU-SIFIVE-S76 %s
+// MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76"
+// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S76: "-target-abi" "lp64d"
+
 // mcpu with default march

[clang] 6cd4b50 - [RISCV] Add SiFive core S51

2021-09-02 Thread Alexander Pivovarov via cfe-commits 

Author: Alexander Pivovarov
Date: 2021-09-02T18:45:25-07:00
New Revision: 6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e

URL: 
https://github.com/llvm/llvm-project/commit/6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e
DIFF: 
https://github.com/llvm/llvm-project/commit/6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e.diff

LOG: [RISCV] Add SiFive core S51

Add SiFive core s51 as rv64imac RocketModel

Reviewed-By: MaskRay, evandro
Differential Revision: https://reviews.llvm.org/D108886

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/RISCVTargetParser.def
llvm/lib/Target/RISCV/RISCV.td

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 8bae1ed29eeb8..c62cefc54a663 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -71,7 +71,9 @@ Deprecated Compiler Flags
 Modified Compiler Flags
 ---
 
-- ...
+- Support has been added for the following processors (``-mcpu`` identifiers 
in parentheses):
+
+  - RISC-V SiFive S51 (``sifive-s51``).
 
 Removed Compiler Flags
 -

diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index bca25059fd21d..4c26bf8751c27 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | 
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 837ec4a6a4427..8963c309e6dbe 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -196,7 +196,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -204,4 +204,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
+// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, 
sifive-7-series

diff  --git a/llvm/include/llvm/Support/RISCVTargetParser.def 
b/llvm/include/llvm/Support/RISCVTargetParser.def
index 6a06f9258105c..01f560ae99a0e 100644
--- a/llvm/include/llvm/Support/RISCVTargetParser.def
+++ b/llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@ PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})

diff  --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 52e8d8cdc7742..61034fd7295c7 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@ def : ProcessorModel<"sifive-e31", RocketModel, 
[FeatureStdExtM,
  FeatureStdExtA,
  FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+