[PATCH] D72184: [BPF] support atomic instructions

jackmanb added a comment. > I did not see kernel has atomic_store, do you mean atomic_set? Sorry yep I meant `atomic_set` > Do you suggest we also implement atomic_set? There is no need for 64-bit > architecture like x64, right? Yeah actually now I think about it, `atomic_set` is pretty

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added a comment. BTW to investigate my previous comment I tried compiling this code: // SPDX-License-Identifier: GPL-2.0 #include #include #include __u64 add64_value = 1; __u64 add64_result; __u32 add32_value = 1; __u32 add32_result; __u64 add_stack_value_copy;

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added a comment. I thought a little more about something I was saying in the office hours. I'm pretty sure GCC's `__atomic_store(, , order)` should fail to compile for anything other than `order=__ATOMIC_RELAXED`, since with the current kernel patchset we have `BPF_SET` (which is

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added a comment. Can we please keep barriers out of scope? I think there's a lot of design to be done there and I'd rather just get the core atomics working first. BTW I got [ 31%] Building LanaiGenDAGISel.inc...

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added inline comments. Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:699 + let Inst{51-48} = addr{19-16}; // base reg + let Inst{55-52} = dst; + let Inst{47-32} = addr{15-0}; // offset There is another mismatch between what I implemented in the

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added inline comments. Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:684 + let Inst{47-32} = addr{15-0}; // offset + let Inst{11-8} = val; + let Inst{7-4} = Opc.Value; yonghong-song wrote: > jackmanb wrote: > > jackmanb wrote: > > > jackmanb wrote:

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added inline comments. Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:684 + let Inst{47-32} = addr{15-0}; // offset + let Inst{11-8} = val; + let Inst{7-4} = Opc.Value; jackmanb wrote: > jackmanb wrote: > > Sorry I'm a beginner with the LLVM code,

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added inline comments. Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:684 + let Inst{47-32} = addr{15-0}; // offset + let Inst{11-8} = val; + let Inst{7-4} = Opc.Value; jackmanb wrote: > Sorry I'm a beginner with the LLVM code, could you explain

[PATCH] D72184: [BPF] support atomic instructions

jackmanb added a comment. Sorry I was disrupted and not able to work on this last week! I've just got started trying to integrate this with my kernel patches. Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:666 +def XADDD : XADD; + } +} FYI - I just

[PATCH] D72184: [WIP][BPF] support exchange/compare-and-exchange instruction

jackmanb added inline comments. Comment at: llvm/lib/Target/BPF/BPFInstrFormats.td:98 + +def BPF_ATOMIC_FETCH : BPFAtomicFlag<0x1>; Per Alexei's email comments let's call this BPF_FETCH? Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:765 +