[PATCH] D155688: [PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

After this patch, I'm seeing a lot of `invariant.gep` created by LICM. For 
example, in `LBM_performStreamCollide` in 470.lbm there are 65 of them. On 
RISC-V, these all get created in registers outside the loop and get spilled. Is 
ARM seeing anything like this or do you have more addressing modes that allow 
CodeGenPrepare to bring these back into the loop?


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[PATCH] D151730: [RISCV] Support target attribute for function

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craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D151730: [RISCV] Support target attribute for function

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:229
+collectNonISAExtFeature(const std::vector , int XLen) 
{
+  auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  auto FeatureNeedOveride = std::vector(FeaturesVec.begin(), I);

Do we need to call find again? We already did it in the caller, can we pass 
that information somehow?



Comment at: clang/lib/Basic/Targets/RISCV.cpp:230
+  auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  auto FeatureNeedOveride = std::vector(FeaturesVec.begin(), I);
+  auto ParseResult =

`std::vector FeaturesNeedOverride(FeaturesVec.begin(), I);`



Comment at: clang/lib/Basic/Targets/RISCV.cpp:243
+
+  for (auto Feat : FeatureNeedOveride) {
+if (!llvm::is_contained(ImpliedFeatures, Feat))

`llvm::copy_if(FeatureNeedOveride, std::back_inserter(NonISAExtFeatureVec), 
[&](const std::string ) { return !llvm::is_contained(ImpliedFeatures, 
Feat); });`


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[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.

LGTM


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[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2509
   // Attempt to parse token as a register.
-  if (parseRegister(Operands, true).isSuccess())
+  if (parseRegister(Operands, true).isSuccess()) {
+// Parse memory base register if present (CORE-V only)

Is it possible to use a custom parser instead of adding a special case to the 
generic parser?


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[PATCH] D151730: [RISCV] Support target attribute for function

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:370
+ std::vector ) {
+  Features.push_back("__RISCV_TargetAttrNeedOverride");
+  auto RII = llvm::RISCVISAInfo::parseArchString(

Why do we need "__RISCV_TargetAttrNeedOverride"?



Comment at: clang/lib/Basic/Targets/RISCV.cpp:434
+if (MarchFromCPU != "") {
+  Ret.Features.clear();
+  handleFullArchString(MarchFromCPU, Ret.Features);

BeMg wrote:
> craig.topper wrote:
> > Why does this clear Ret.Features, but full-arch-string doesn't?
> I think full-arch-string also clear the Ret.Features in line 398 right after 
> `if (Feature.startswith("arch="))`.
Thanks. I missed it.


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[PATCH] D151730: [RISCV] Support target attribute for function

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:229
+resolveTargetAttrOverride(const std::vector ) {
+  if (!llvm::is_contained(FeaturesVec, "__RISCV_TargetAttrNeedOverride"))
+return FeaturesVec;

Can we use something like

```
auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
if (I == FeaturesVec.end())
  return FeaturesVec;

return std::vector(I++, FeaturesVec.end());
```



Comment at: clang/lib/Basic/Targets/RISCV.cpp:255
 
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  std::vector NewFeaturesVec =
+  resolveTargetAttrOverride(FeaturesVec);

Does this lose features like `relax` and `save-restore`? Those aren't part of 
the -march so they don't appear after `__RISCV_TargetAttrNeedOverride`



Comment at: clang/lib/Basic/Targets/RISCV.cpp:424
+  continue;
+} else if (Feature.startswith("cpu=")) {
+  if (!Ret.CPU.empty())

You don't need an `else` since the body of the `if` ended in `continue`. When 
the `if` is taken control flow will never reach here.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:434
+if (MarchFromCPU != "") {
+  Ret.Features.clear();
+  handleFullArchString(MarchFromCPU, Ret.Features);

Why does this clear Ret.Features, but full-arch-string doesn't?



Comment at: clang/lib/Basic/Targets/RISCV.cpp:440
+  continue;
+} else if (Feature.startswith("tune=")) {
+  if (!Ret.Tune.empty())

No need for `else` here


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Need to update the table here 
https://clang.llvm.org/docs/LanguageExtensions.html#vector-operations to 
include RVV


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[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16200
   SDValue Hi;
-  if (VA.getLocReg() == RISCV::X17) {
 // Second half of f64 is passed on the stack.

This code has been rewritten recently. Please rebase


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[PATCH] D151869: [RISCV] Enable more builtin for zvfhmin without zvfh

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:479
+  // 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`,
+  // `unsigned long long` and `double` to have 4-bytes alignment. This
+  // behavior may be changed when RV32E/ILP32E is ratified.

4-bytes -> 4-byte



Comment at: clang/test/Preprocessor/riscv-target-features.c:6
 
+// CHECK-NOT: __riscv_32e
 // CHECK-NOT: __riscv_div {{.*$}}

__riscv_64e too



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:937
   // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 

This needs to be rebased. These FIXMEs were removed.


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[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

[Craig Topper via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc9db799dda69: [RISCV] Dont add -unaligned-scalar-mem 
to target features by default. (authored by craig.topper).

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Files:
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  clang/test/Driver/riscv-default-features.c
  clang/test/Driver/riscv-features.c


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -39,8 +39,6 @@
 // NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
 // UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
 // NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
-// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
-// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,10 +3,8 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
-// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
-// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -169,15 +169,17 @@
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
   bool HasV = llvm::is_contained(Features, "+zve32x");
-  if (Args.hasFlag(options::OPT_munaligned_access,
-   options::OPT_mno_unaligned_access, false)) {
-Features.push_back("+unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("+unaligned-vector-mem");
-  } else {
-Features.push_back("-unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("-unaligned-vector-mem");
+  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access)) {
+if (A->getOption().matches(options::OPT_munaligned_access)) {
+  Features.push_back("+unaligned-scalar-mem");
+  if (HasV)
+Features.push_back("+unaligned-vector-mem");
+} else {
+  Features.push_back("-unaligned-scalar-mem");
+  if (HasV)
+Features.push_back("-unaligned-vector-mem");
+}
   }
 
   // Now add any that the user explicitly requested on the command line,


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -39,8 +39,6 @@
 // NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
 // UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
 // NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
-// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
-// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,10 +3,8 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
-// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
-// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -169,15 +169,17 @@
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
   bool HasV = llvm::is_contained(Features, "+zve32x");
-  if (Args.hasFlag(options::OPT_munaligned_access,
-   options::OPT_mno_unaligned_access, false)) {
-Features.push_back("+unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("+unaligned-vector-mem");
-  } else {
-Features.push_back("-unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("-unaligned-vector-mem");
+  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access)) {
+if 

[PATCH] D158255: [RISCV][NFC] Update compile options for some vector crypto C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 554561.
craig.topper added a comment.

Remove change to sifive-x280.


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Files:
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  clang/test/Driver/riscv-default-features.c
  clang/test/Driver/riscv-features.c


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -39,8 +39,6 @@
 // NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
 // UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
 // NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
-// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
-// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,10 +3,8 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
-// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
-// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -169,15 +169,17 @@
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
   bool HasV = llvm::is_contained(Features, "+zve32x");
-  if (Args.hasFlag(options::OPT_munaligned_access,
-   options::OPT_mno_unaligned_access, false)) {
-Features.push_back("+unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("+unaligned-vector-mem");
-  } else {
-Features.push_back("-unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("-unaligned-vector-mem");
+  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access)) {
+if (A->getOption().matches(options::OPT_munaligned_access)) {
+  Features.push_back("+unaligned-scalar-mem");
+  if (HasV)
+Features.push_back("+unaligned-vector-mem");
+} else {
+  Features.push_back("-unaligned-scalar-mem");
+  if (HasV)
+Features.push_back("-unaligned-vector-mem");
+}
   }
 
   // Now add any that the user explicitly requested on the command line,


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -39,8 +39,6 @@
 // NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
 // UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
 // NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
-// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
-// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,10 +3,8 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
-// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
-// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -169,15 +169,17 @@
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
   bool HasV = llvm::is_contained(Features, "+zve32x");
-  if (Args.hasFlag(options::OPT_munaligned_access,
-   options::OPT_mno_unaligned_access, false)) {
-Features.push_back("+unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("+unaligned-vector-mem");
-  } else {
-Features.push_back("-unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("-unaligned-vector-mem");
+  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access)) {
+if (A->getOption().matches(options::OPT_munaligned_access)) {
+  

[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:185
+   FeatureStdExtZbb,
+   FeatureUnalignedScalarMem],
   [TuneSiFive7,

wangpc wrote:
> This can be tested in `clang/test/Driver/riscv-cpus.c`.
This shouldn’t be in here. That was for testing and I accidentally committed it


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[PATCH] D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: wangpc, kito-cheng, asb, reames, jrtc27.
Herald added subscribers: jobnoorman, luke, sunshaoce, VincentWu, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
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Herald added a project: All.
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Herald added projects: clang, LLVM.

Only pass it +unaligned-scalar-mem/-unaligned-scalar-mem if the
user has passed one of the alignment options.

This allows us to add unaligned-scalar-mem as a feature on CPUs
that support it.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-default-features.c
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCVProcessors.td


Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -181,7 +181,8 @@
FeatureStdExtZfh,
FeatureStdExtZvfh,
FeatureStdExtZba,
-   FeatureStdExtZbb],
+   FeatureStdExtZbb,
+   FeatureUnalignedScalarMem],
   [TuneSiFive7,
TuneDLenFactor2]>;
 
Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -39,8 +39,6 @@
 // NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
 // UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
 // NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
-// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
-// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,10 +3,8 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
-// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
-// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -169,15 +169,17 @@
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
   bool HasV = llvm::is_contained(Features, "+zve32x");
-  if (Args.hasFlag(options::OPT_munaligned_access,
-   options::OPT_mno_unaligned_access, false)) {
-Features.push_back("+unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("+unaligned-vector-mem");
-  } else {
-Features.push_back("-unaligned-scalar-mem");
-if (HasV)
-  Features.push_back("-unaligned-vector-mem");
+  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access)) {
+if (A->getOption().matches(options::OPT_munaligned_access)) {
+  Features.push_back("+unaligned-scalar-mem");
+  if (HasV)
+Features.push_back("+unaligned-vector-mem");
+} else {
+  Features.push_back("-unaligned-scalar-mem");
+  if (HasV)
+Features.push_back("-unaligned-vector-mem");
+}
   }
 
   // Now add any that the user explicitly requested on the command line,


Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -181,7 +181,8 @@
FeatureStdExtZfh,
FeatureStdExtZvfh,
FeatureStdExtZba,
-   FeatureStdExtZbb],
+   FeatureStdExtZbb,
+   FeatureUnalignedScalarMem],
   [TuneSiFive7,
TuneDLenFactor2]>;
 
Index: clang/test/Driver/riscv-features.c

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D152279#4612087 , @MaskRay wrote:

> I am still interested in moving this forward. What should be done here? If 
> the decision is to keep the current odd default 8 for 
> `toolchains::RISCVToolChain`, I guess I'll have to take the compromise as 
> making a step forward is better than nothing.

On 1 RV64 CPU I tried in our RTL simulator, changing from 8 to 0 reduced 
dhrystone score by 2.7%. Using 16, or 32 gave the same score as 8. Reducing 8 
to 4 improved the score by 0.5%.


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[PATCH] D157953: [CGCall][RISCV] Handle function calls with parameter of RVV tuple type

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D158402: [Clang][RISCV] Add vcreate intrinsics for RVV tuple types

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D157130: [RISCV] Check type size for lax conversions between RVV builtin types and VectorType::RVVFixedLengthDataVector.

[Craig Topper via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG33af2f131db7: [RISCV] Check type size for lax conversions 
between RVV builtin types and… (authored by craig.topper).

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Files:
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  clang/test/Sema/riscv-rvv-lax-vector-conversions.c


Index: clang/test/Sema/riscv-rvv-lax-vector-conversions.c
===
--- clang/test/Sema/riscv-rvv-lax-vector-conversions.c
+++ clang/test/Sema/riscv-rvv-lax-vector-conversions.c
@@ -2,8 +2,6 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f 
-target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 
-flax-vector-conversions=integer -ffreestanding -fsyntax-only 
-verify=lax-vector-integer %s
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f 
-target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 
-flax-vector-conversions=all -ffreestanding -fsyntax-only 
-verify=lax-vector-all %s
 
-// lax-vector-all-no-diagnostics
-
 // REQUIRES: riscv-registered-target
 
 #define RVV_FIXED_ATTR 
__attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
@@ -20,6 +18,8 @@
 typedef __rvv_float32m1_t vfloat32m1_t;
 typedef __rvv_float64m1_t vfloat64m1_t;
 
+typedef __rvv_int64m2_t vint64m2_t;
+
 typedef vfloat32m1_t rvv_fixed_float32m1_t RVV_FIXED_ATTR;
 typedef vint32m1_t rvv_fixed_int32m1_t RVV_FIXED_ATTR;
 typedef float gnu_fixed_float32m1_t GNU_FIXED_ATTR;
@@ -76,3 +76,17 @@
   // lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka 
'__rvv_float64m1_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka 
'__rvv_float64m1_t') from incompatible type}}
 }
+
+void not_allowed() {
+  rvv_fixed_int32m1_t fi32m1;
+  vint64m2_t si64m2;
+
+  fi32m1 = si64m2;
+  // lax-vector-none-error@-1 {{assigning to 'rvv_fixed_int32m1_t' (vector of 
16 'int' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_int32m1_t' (vector 
of 16 'int' values) from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'rvv_fixed_int32m1_t' (vector of 
16 'int' values) from incompatible type}}
+  si64m2 = fi32m1;
+  // lax-vector-none-error@-1 {{assigning to 'vint64m2_t' (aka 
'__rvv_int64m2_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'vint64m2_t' (aka 
'__rvv_int64m2_t') from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'vint64m2_t' (aka 
'__rvv_int64m2_t') from incompatible type}}
+}
Index: clang/lib/AST/ASTContext.cpp
===
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -9612,9 +9612,8 @@
   const LangOptions::LaxVectorConversionKind LVCKind =
   getLangOpts().getLaxVectorConversions();
 
-  // If __riscv_v_fixed_vlen != N do not allow GNU vector lax conversion.
-  if (VecTy->getVectorKind() == VectorType::GenericVector &&
-  getTypeSize(SecondType) != getRVVTypeSize(*this, BT))
+  // If __riscv_v_fixed_vlen != N do not allow vector lax conversion.
+  if (getTypeSize(SecondType) != getRVVTypeSize(*this, BT))
 return false;
 
   // If -flax-vector-conversions=all is specified, the types are


Index: clang/test/Sema/riscv-rvv-lax-vector-conversions.c
===
--- clang/test/Sema/riscv-rvv-lax-vector-conversions.c
+++ clang/test/Sema/riscv-rvv-lax-vector-conversions.c
@@ -2,8 +2,6 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=integer -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=all -ffreestanding -fsyntax-only -verify=lax-vector-all %s
 
-// lax-vector-all-no-diagnostics
-
 // REQUIRES: riscv-registered-target
 
 #define RVV_FIXED_ATTR __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
@@ -20,6 +18,8 @@
 typedef __rvv_float32m1_t vfloat32m1_t;
 typedef __rvv_float64m1_t vfloat64m1_t;
 
+typedef __rvv_int64m2_t vint64m2_t;
+
 typedef vfloat32m1_t rvv_fixed_float32m1_t RVV_FIXED_ATTR;
 typedef vint32m1_t rvv_fixed_int32m1_t RVV_FIXED_ATTR;
 typedef float gnu_fixed_float32m1_t GNU_FIXED_ATTR;
@@ -76,3 +76,17 @@
   // lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}}
 }
+
+void not_allowed() {
+  rvv_fixed_int32m1_t fi32m1;
+  vint64m2_t si64m2;
+
+  fi32m1 = si64m2;
+ 

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/test/Driver/riscv-rvv-vector-bits.c:43
+// RUN: %clang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv \
+// RUN:  -mrvv-vector-bits=64 2>&1 | FileCheck 
--check-prefix=CHECK-BAD-VALUE-ERROR %s
+

wangpc wrote:
> Why isn't 64 an valid value?
Because the command line contains ‘v’, zvl128b is implied. So rvv-vector-bits 
must be at least 128.


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[PATCH] D157953: [CGCall][RISCV] Handle function calls with parameter of RVV tuple type

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/CodeGen/CGCall.cpp:5278
+  for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
+llvm::Value *LI = Builder.CreateExtractValue(
+StoredStructValue, i, Src.getName() + ".extract" + Twine(i));

`LI` meant LoadInst in the original code.


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[PATCH] D156821: [CodeGen] [ubsan] Respect integer overflow handling in abs builtin

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D156821#4600550 , @MaskRay wrote:

>> Currenly both Clang and GCC support the following set of flags that control
>
> code gen of signed overflow:
>
>> [...]
>> Howerver, clang ignores these flags for __builtin_abs(int) and its 
>> higher-width
>
> versions, so passing minimum integer value always causes poison.
>
> This paragraph reads as if GCC emits a trap for `__builtin_abs` in -ftrapv 
> mode, but it doesn't. That said, its `-fsanitize=signed-integer-overflow` 
> does handle `__builtin_abs`.

On X86 at least, gcc does call `__negvsi2` for __builtin_abs under -ftrapv. 
https://godbolt.org/z/8dhn9bsv5


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[PATCH] D158257: [RISCV] Add feature checks for vector crypto C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D158255: [RISCV][NFC] Update compile options for some vector crypto C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c:4
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b 
\
+// RUN:   -target-feature +experimental-zvbb \
+// RUN:   -target-feature +experimental-zvbc \

We should use the minimum number of command line options for what is being 
tested.


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[PATCH] D156821: [CodeGen] [ubsan] Respect integer overflow handling in abs builtin

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

I just put up a patch for RISC-V failure related to this 
https://reviews.llvm.org/D158304 change.


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

[Craig Topper via Phabricator via cfe-commits]

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Comment at: clang/lib/Sema/SemaChecking.cpp:14906
+// specified
+if (S.Context.areCompatibleRVVTypes(QualType(OriginalTarget, 0),
+QualType(Source, 0)) ||

Why do we need this, but SVE doesn't?



Comment at: clang/lib/Sema/SemaExpr.cpp:12294
 
+  if ((LHSBuiltinTy && LHSBuiltinTy->isSVEBool()) ||
+  (RHSBuiltinTy && RHSBuiltinTy->isSVEBool())) {

This code looks identical to the code above it.



Comment at: clang/lib/Sema/SemaExpr.cpp:16322
   break;
-else if (resultType->isSveVLSBuiltinType()) // SVE vectors allow + and -
+else if (resultType->isVLSBuiltinType()) // SVE vectors allow + and -
   break;

Update "SVE" to mention "RVV" too?


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[PATCH] D157953: [CGCall][RISCV] Handle function calls with parameter of RVV tuple type

[Craig Topper via Phabricator via cfe-commits]

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Comment at: clang/lib/CodeGen/CGCall.cpp:5268
+  assert(STy->containsHomogeneousScalableVectorTypes() &&
+ "ABI only supports structure with hmogeneous scalable vector "
+ "type");

Homogeneous


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[PATCH] D158067: [RISCV] Bump vector crypto to v1.0 RC2

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
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This revision is now accepted and ready to land.

LGTM


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
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This revision is now accepted and ready to land.

LGTM


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:37
+  let Inst{12} = 0;
+  let Inst{11-7} = rs1;
+  let Inst{6-2} = 0b0;

Do we need the rs1 variable or can we use rs1val here? We usually have the rs1 
field because the encoder maps ins/outs operand names to the field name. In 
this case we have an explicit immediate passed as rs1val. Is the encoding value 
coming from the operand or from the immediate? I can't tell with the name 
conflict.


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[PATCH] D151730: [RISCV] Support target attribute for function

[Craig Topper via Phabricator via cfe-commits]

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Comment at: clang/lib/Basic/Targets/RISCV.cpp:417
+  continue;
+} else if (Feature.startswith("no-"))
+  Ret.Features.push_back("-" + Feature.split("-").second.str());

Is this tested? I don't see any "no-" in the the test


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[PATCH] D152423: [RISCV] Add function that check extension name with version

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:32
+
+class RVC_SSInst rs1, RegisterClass reg_class, string opcodestr> :
+  RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], 
InstFormatOther> {

Can you call this `rs1val` instead of `rs1` since $rs1 is part of the ins.


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:88
+
+let Predicates = [HasStdExtZicfiss, HasStdExtC] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 
in

Is it compatible with Zca?


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[PATCH] D157362: [RISCV] Add MC layer support for Zicfilp.

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D157362: [RISCV] Add MC layer support for Zicfilp.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:665
 
+let Predicates = [HasStdExtZicfilp] in {
+def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;

There is a designated spot in this file for InstAliases.


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[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh or Zhinx is available

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D157651: [RISCV] Rewrite CheckInvalidVLENandLMUL to avoid floating point.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGee6befe26437: [RISCV] Rewrite CheckInvalidVLENandLMUL to 
avoid floating point. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D157651?vs=549634=549636#toc

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Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4474,14 +4474,24 @@
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  uint64_t ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  uint64_t ElemCount = Type->isRVVType(1) ? 1 :
-   Type->isRVVType(2) ? 2 :
-   Type->isRVVType(4) ? 4 :
-   Type->isRVVType(8) ? 8 :
-   16;
-  float Lmul = (float)(ElemSize * ElemCount) / llvm::RISCV::RVVBitsPerBlock;
-  uint64_t MinRequiredVLEN = std::max(EGW / Lmul, (float)ElemSize);
+  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
+  unsigned MinElemCount = Type->isRVVType(1)   ? 1
+  : Type->isRVVType(2) ? 2
+  : Type->isRVVType(4) ? 4
+  : Type->isRVVType(8) ? 8
+   : 16;
+
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is less than or equal to the minimum number of elements, then the
+  // type is valid.
+  if (EGS <= MinElemCount)
+return false;
+
+  // Otherwise, we need vscale to be at least EGS / MinElemCont.
+  assert(EGS % MinElemCount == 0);
+  unsigned VScaleFactor = EGS / MinElemCount;
+  // Vscale is VLEN/RVVBitsPerBlock.
+  unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
   std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";
   if (!TI.hasFeature(RequiredExt))
 return S.Diag(TheCall->getBeginLoc(),


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4474,14 +4474,24 @@
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  uint64_t ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  uint64_t ElemCount = Type->isRVVType(1) ? 1 :
-   Type->isRVVType(2) ? 2 :
-   Type->isRVVType(4) ? 4 :
-   Type->isRVVType(8) ? 8 :
-   16;
-  float Lmul = (float)(ElemSize * ElemCount) / llvm::RISCV::RVVBitsPerBlock;
-  uint64_t MinRequiredVLEN = std::max(EGW / Lmul, (float)ElemSize);
+  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
+  unsigned MinElemCount = Type->isRVVType(1)   ? 1
+  : Type->isRVVType(2) ? 2
+  : Type->isRVVType(4) ? 4
+  : Type->isRVVType(8) ? 8
+   : 16;
+
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is less than or equal to the minimum number of elements, then the
+  // type is valid.
+  if (EGS <= MinElemCount)
+return false;
+
+  // Otherwise, we need vscale to be at least EGS / MinElemCont.
+  assert(EGS % MinElemCount == 0);
+  unsigned VScaleFactor = EGS / MinElemCount;
+  // Vscale is VLEN/RVVBitsPerBlock.
+  unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
   std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";
   if (!TI.hasFeature(RequiredExt))
 return S.Diag(TheCall->getBeginLoc(),
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[PATCH] D157651: [RISCV] Rewrite CheckInvalidVLENandLMUL to avoid floating point.

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 549634.
craig.topper added a comment.

Revise coment, rename variable.


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Files:
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Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4474,14 +4474,22 @@
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  uint64_t ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  uint64_t ElemCount = Type->isRVVType(1) ? 1 :
-   Type->isRVVType(2) ? 2 :
-   Type->isRVVType(4) ? 4 :
-   Type->isRVVType(8) ? 8 :
-   16;
-  float Lmul = (float)(ElemSize * ElemCount) / llvm::RISCV::RVVBitsPerBlock;
-  uint64_t MinRequiredVLEN = std::max(EGW / Lmul, (float)ElemSize);
+  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
+  unsigned MinElemCount = Type->isRVVType(1)   ? 1
+  : Type->isRVVType(2) ? 2
+  : Type->isRVVType(4) ? 4
+  : Type->isRVVType(8) ? 8
+   : 16;
+
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is less than or equal to the minimum number of elements we're done.
+  if (EGS <= MinElemCount)
+return false;
+
+  // We need vscale to be at least this value.
+  unsigned VScaleFactor = EGS / MinElemCount;
+  // Vscale is VLEN/RVVBitsPerBlock.
+  unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
   std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";
   if (!TI.hasFeature(RequiredExt))
 return S.Diag(TheCall->getBeginLoc(),


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4474,14 +4474,22 @@
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  uint64_t ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  uint64_t ElemCount = Type->isRVVType(1) ? 1 :
-   Type->isRVVType(2) ? 2 :
-   Type->isRVVType(4) ? 4 :
-   Type->isRVVType(8) ? 8 :
-   16;
-  float Lmul = (float)(ElemSize * ElemCount) / llvm::RISCV::RVVBitsPerBlock;
-  uint64_t MinRequiredVLEN = std::max(EGW / Lmul, (float)ElemSize);
+  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
+  unsigned MinElemCount = Type->isRVVType(1)   ? 1
+  : Type->isRVVType(2) ? 2
+  : Type->isRVVType(4) ? 4
+  : Type->isRVVType(8) ? 8
+   : 16;
+
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is less than or equal to the minimum number of elements we're done.
+  if (EGS <= MinElemCount)
+return false;
+
+  // We need vscale to be at least this value.
+  unsigned VScaleFactor = EGS / MinElemCount;
+  // Vscale is VLEN/RVVBitsPerBlock.
+  unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
   std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";
   if (!TI.hasFeature(RequiredExt))
 return S.Diag(TheCall->getBeginLoc(),
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[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh is available

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/docs/LanguageExtensions.rst:815
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh is available)
 

Zhinx also


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[PATCH] D157130: [RISCV] Check type size for lax conversions between RVV builtin types and VectorType::RVVFixedLengthDataVector.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Ping


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Please update docs/RISCVUsage.rst


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[PATCH] D157651: [RISCV] Rewrite CheckInvalidVLENandLMUL to avoid floating point.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: 4vtomat, kito-cheng, reames, asb.
Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, rogfer01, shiva0217, simoncook, 
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This avoids needing an FP value to represent LMUL.


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Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4473,14 +4473,22 @@
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  uint64_t ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  uint64_t ElemCount = Type->isRVVType(1) ? 1 :
+  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
+  unsigned ElemCount = Type->isRVVType(1) ? 1 :
Type->isRVVType(2) ? 2 :
Type->isRVVType(4) ? 4 :
Type->isRVVType(8) ? 8 :
16;
-  float Lmul = (float)(ElemSize * ElemCount) / llvm::RISCV::RVVBitsPerBlock;
-  uint64_t MinRequiredVLEN = std::max(EGW / Lmul, (float)ElemSize);
+
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is more than our minimum number of elements we're done.
+  if (EGS <= ElemCount)
+return false;
+
+  // We need vscale to be at least this value.
+  unsigned VScaleFactor = EGS / ElemCount;
+  // Vscale is VLEN/RVVBitsPerBlock.
+  unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
   std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";
   if (!TI.hasFeature(RequiredExt))
 return S.Diag(TheCall->getBeginLoc(),


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4473,14 +4473,22 @@
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  uint64_t ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  uint64_t ElemCount = Type->isRVVType(1) ? 1 :
+  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
+  unsigned ElemCount = Type->isRVVType(1) ? 1 :
Type->isRVVType(2) ? 2 :
Type->isRVVType(4) ? 4 :
Type->isRVVType(8) ? 8 :
16;
-  float Lmul = (float)(ElemSize * ElemCount) / llvm::RISCV::RVVBitsPerBlock;
-  uint64_t MinRequiredVLEN = std::max(EGW / Lmul, (float)ElemSize);
+
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is more than our minimum number of elements we're done.
+  if (EGS <= ElemCount)
+return false;
+
+  // We need vscale to be at least this value.
+  unsigned VScaleFactor = EGS / ElemCount;
+  // Vscale is VLEN/RVVBitsPerBlock.
+  unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
   std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";
   if (!TI.hasFeature(RequiredExt))
 return S.Diag(TheCall->getBeginLoc(),
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[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/test/Sema/rvv-required-features-invalid.c:16
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { // expected-note 
{{'test_sf_vc_x_se_u64m1' declared here}}
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to 
undeclared function '__riscv_sf_vc_x_se_u64m1'}} expected-note {{did you mean 
'test_sf_vc_x_se_u64m1'?}}
+}

This doesn't mention the xsfvcp extension. So it doesn't look like the 
diagnostic in the code is being hit.


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[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Is it possible to test?


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D156821: [CodeGen] [ubsan] Respect integer overflow handling in abs builtin

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This looks good to me, but I'm not sure I'm a fully qualified reviewer here.


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[PATCH] D157130: [RISCV] Check type size for lax conversions between RVV builtin types and VectorType::RVVFixedLengthDataVector.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: aaron.ballman, c-rhodes.
Herald added subscribers: jobnoorman, luke, VincentWu, ctetreau, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
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This code was copied from SVE and modified for RVV. For SVE, there
is only one size for builtin types so they didn't need to check
the size. For RVV, due to LMUL there are 7 different sizes of builtin
types so we do need to check the size.

I'm not sure we should have lax vector conversions at all for RVV.
That appears to be contributing to 
https://github.com/llvm/llvm-project/issues/64404

This patch at least fixes the obvious correctness issue.
This should be backported to LLVM 17.


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Files:
  clang/lib/AST/ASTContext.cpp
  clang/test/Sema/riscv-rvv-lax-vector-conversions.c


Index: clang/test/Sema/riscv-rvv-lax-vector-conversions.c
===
--- clang/test/Sema/riscv-rvv-lax-vector-conversions.c
+++ clang/test/Sema/riscv-rvv-lax-vector-conversions.c
@@ -2,8 +2,6 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f 
-target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 
-flax-vector-conversions=integer -ffreestanding -fsyntax-only 
-verify=lax-vector-integer %s
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f 
-target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 
-flax-vector-conversions=all -ffreestanding -fsyntax-only 
-verify=lax-vector-all %s
 
-// lax-vector-all-no-diagnostics
-
 // REQUIRES: riscv-registered-target
 
 #define RVV_FIXED_ATTR 
__attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
@@ -20,6 +18,8 @@
 typedef __rvv_float32m1_t vfloat32m1_t;
 typedef __rvv_float64m1_t vfloat64m1_t;
 
+typedef __rvv_int64m2_t vint64m2_t;
+
 typedef vfloat32m1_t rvv_fixed_float32m1_t RVV_FIXED_ATTR;
 typedef vint32m1_t rvv_fixed_int32m1_t RVV_FIXED_ATTR;
 typedef float gnu_fixed_float32m1_t GNU_FIXED_ATTR;
@@ -76,3 +76,17 @@
   // lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka 
'__rvv_float64m1_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka 
'__rvv_float64m1_t') from incompatible type}}
 }
+
+void not_allowed() {
+  rvv_fixed_int32m1_t fi32m1;
+  vint64m2_t si64m2;
+
+  fi32m1 = si64m2;
+  // lax-vector-none-error@-1 {{assigning to 'rvv_fixed_int32m1_t' (vector of 
16 'int' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_int32m1_t' (vector 
of 16 'int' values) from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'rvv_fixed_int32m1_t' (vector of 
16 'int' values) from incompatible type}}
+  si64m2 = fi32m1;
+  // lax-vector-none-error@-1 {{assigning to 'vint64m2_t' (aka 
'__rvv_int64m2_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'vint64m2_t' (aka 
'__rvv_int64m2_t') from incompatible type}}
+  // lax-vector-all-error@-3 {{assigning to 'vint64m2_t' (aka 
'__rvv_int64m2_t') from incompatible type}}
+}
Index: clang/lib/AST/ASTContext.cpp
===
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -9612,9 +9612,8 @@
   const LangOptions::LaxVectorConversionKind LVCKind =
   getLangOpts().getLaxVectorConversions();
 
-  // If __riscv_v_fixed_vlen != N do not allow GNU vector lax conversion.
-  if (VecTy->getVectorKind() == VectorType::GenericVector &&
-  getTypeSize(SecondType) != getRVVTypeSize(*this, BT))
+  // If __riscv_v_fixed_vlen != N do not allow vector lax conversion.
+  if (getTypeSize(SecondType) != getRVVTypeSize(*this, BT))
 return false;
 
   // If -flax-vector-conversions=all is specified, the types are


Index: clang/test/Sema/riscv-rvv-lax-vector-conversions.c
===
--- clang/test/Sema/riscv-rvv-lax-vector-conversions.c
+++ clang/test/Sema/riscv-rvv-lax-vector-conversions.c
@@ -2,8 +2,6 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=integer -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=all -ffreestanding -fsyntax-only -verify=lax-vector-all %s
 
-// lax-vector-all-no-diagnostics

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.

LGTM


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[PATCH] D155145: [X86] Add AVX-VNNI-INT16 instructions.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D155145#4556157 , @anna wrote:

> In D155145#4554786 , @anna wrote:
>
>>> Can you capture the values of EAX, EBX, ECX, and EDX after the two calls to 
>>> getX86CpuIDAndInfoEx that have 0x7 as the first argument? Maybe there's a 
>>> bug in CPUID on Sandy Bridge.
>>
>> Sure, on the original code before the patch you suggested right?
>> The two calls are:
>>
>>bool HasLeaf7 =
>>   MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, , , , 
>> );
>>   +   llvm::errs() << "Before setting fsgsbase the value for EAX: " << EAX
>>   + << " EBX: " << EBX << " ECX: " << ECX << "  EDX: " 
>> << EDX
>>   + << "\n";
>> 
>>   Features["fsgsbase"]   = HasLeaf7 && ((EBX >>  0) & 1);
>>   
>>   bool HasLeaf7Subleaf1 =
>>   MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, , , , 
>> );
>>   +   llvm::errs() << "Before setting sha512 the value for EAX: " << EAX
>>   + << " EBX: " << EBX << " ECX: " << ECX << "  EDX: " 
>> << EDX
>>   + << "\n";
>>   Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
>>   ...
>>   we set avxvnniint16 after this
>>
>> Takes a while to get a build on this machine, should have the output soon.
>
> @craig.topper here is the output:
>
>   Before setting fsgsbase the value for EAX: 0 EBX: 0 ECX: 0  EDX: 2617246720 
> // this is after the HasLeaf7 calculation
>   Before setting sha512 the value for EAX: 0 EBX: 0 ECX: 0  EDX: 2617246720 
> // this is after the HasLeaf7Subleaf1 calculation
>
> So, with your patch `HasLeaf7Subleaf1` is 0 as EAX is 0. Pls let me know if 
> you need  any additional diagnostics output (we actually lose access to the 
> machine on friday, since it is being retired!).
>
>> The documentation says that invalid subleaves of leaf 7 should return all 
>> 0s. So we thought it was safe to check the bits of sub leaf 1 even if eax 
>> from subleaf 0 doesn't say subleaf 1 is supported.
>
> This means the CPUID doesn't satisfy the documentation since EDX != 0 for 
> SubLeaf1?

Interestingly all of the bits set in EDX are features that were things that 
were added in microcode patches in the wake of vulnerabilities like Spectre and 
Meltdown. Maybe the microcode patch forgot to check the subleaf since there was 
no subleaf implemented when sandy bridge was originally made.

I think my patch is the correct fix given that information. I'll post a patch 
for review shortly.


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:4496
 
+static bool CheckInValidEGW(const TargetInfo , CallExpr *TheCall, Sema ,
+QualType Type, int EGW) {

InValid -> Invalid



Comment at: clang/lib/Sema/SemaChecking.cpp:4499
+  assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
+  llvm::SmallVector> ValidPairs128 =
+  {{1, "zvl256b"}, {2, "zvl128b"}, {4, "zvl64b"}};

Can this be a plain array or a std::array instead of SmallVector since the size 
is fixed.



Comment at: clang/lib/Sema/SemaChecking.cpp:4693
+  }
+  case RISCVVector::BI__builtin_rvv_vaesdf_vv:
+  case RISCVVector::BI__builtin_rvv_vaesdf_vs:

Are there `tu` versions of these builtins?



Comment at: clang/test/Sema/zvk-invalid.c:19
+  __riscv_vaesdf_vv_u32mf2(vd, vs2, vl); // expected-error {{RISC-V type 
'vuint32mf2_t' (aka '__rvv_uint32mf2_t') requires the 'zvl256b' extension}}
+}

Test a _vs intrinsic since the vs operand has a different type than the result?


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[PATCH] D155145: [X86] Add AVX-VNNI-INT16 instructions.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D155145#4553922 , @anna wrote:

> In D155145#4551621 , @craig.topper 
> wrote:
>
>> In D155145#4551526 , @anna wrote:
>>
>>> In D155145#4544068 , @pengfei 
>>> wrote:
>>>
 In D155145#4543326 , @anna wrote:

> We see a crash bisected to this patch about using an illegal instruction. 
> Here's the CPUInfo for the machine:
>
>   CPU info:
>   current cpu id: 22
>   total 32(physical cores 16) (assigned logical cores 32) (assigned 
> physical cores 16) (assigned_sockets:2 of 2) (8 cores per cpu, 2 threads 
> per core) family 6 model 45 stepping 7 microcode 0x71a, cmov, cx8, fxsr, 
> mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, vzeroupper, avx, 
> aes, clmul, ht, tsc, tscinvbit, tscinv, clflush
>   AvgLoads: 0.30, 0.10, 0.18
>   CPU Model and flags from /proc/cpuinfo:
>   model name  : Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz
>   flags   : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge 
> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe 
> syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good 
> nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor 
> ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic 
> popcnt tsc_deadline_timer aes xsave avx lahf_lm epb pti ssbd ibrs ibpb 
> stibp tpr_shadow vnmi flexpriority ept vpid xsaveopt dtherm ida arat pln 
> pts md_clear flush_l1d
>   Online cpus: 0-31
>   Offline cpus:
>   BIOS frequency limitation: 
>   Frequency switch latency (ns): 2
>   Available cpu frequencies: 
>   Current governor: schedutil
>   Core performance/turbo boost: 
>
> I don't see `avxvnniint16` in the flags list nor avx2. So, this 
> (relatively new) instruction shouldn't be generated for this machine. Any 
> ideas on why this might be happening?

 As far as I can see from the patch, the only way to generate avxvnniint16 
 instructions is to call its specific intrinsics explicitly. And we will 
 check compiling options in FE before allowing to call the intrinsics. We 
 do have an optimization to generate vnni instructions without intrinsics, 
 but we haven't extend it to avxvnniint16 so far.
 So I don't know what's wrong in your case, could you provide a reproducer 
 for your problem?
>>>
>>> I've investigated what is going on. With this patch, we are now passing in 
>>> `+avxvnniint16` into machine attributes. With that attribute, we now 
>>> generate an instruction which is illegal on sandybridge machine:
>>>
>>>0x3013f2af:  jmpq   0x3013f09b
>>>  0x3013f2b4:mov%rax,%rdi
>>>  0x3013f2b7:and$0xfff0,%rdi
>>>   => 0x3013f2bb:vpbroadcastd %xmm0,%ymm2
>>>  0x3013f2c0:vpbroadcastd %xmm1,%ymm3
>>>
>>> The instruction `vpbroadcastd %xmm0,%ymm2` requires `AVX2` CPU flag: 
>>> https://www.felixcloutier.com/x86/vpbroadcast. However, the machine has 
>>> only AVX flag.
>>>
>>> This is the complete mattr generated:
>>>
>>>   !3 = 
>>> !{!"-mattr=-prfchw,-cldemote,+avx,+aes,+sahf,+pclmul,-xop,+crc32,-xsaves,-avx512fp16,-sm4,+sse4.1,-avx512ifma,+xsave,-avx512pf,+sse4.2,-tsxldtrk,-ptwrite,-widekl,-sm3,-invpcid,+64bit,-xsavec,-avx512vpopcntdq,+cmov,-avx512vp2intersect,-avx512cd,-movbe,-avxvnniint8,-avx512er,-amx-int8,-kl,-sha512,-avxvnni,-rtm,-adx,-avx2,-hreset,-movdiri,-serialize,-vpclmulqdq,-avx512vl,-uintr,-clflushopt,-raoint,-cmpccxadd,-bmi,-amx-tile,+sse,-gfni,+avxvnniint16,-amx-fp16,+xsaveopt,-rdrnd,-avx512f,-amx-bf16,-avx512bf16,-avx512vnni,+cx8,-avx512bw,+sse3,-pku,-fsgsbase,-clzero,-mwaitx,-lwp,-lzcnt,-sha,-movdir64b,-wbnoinvd,-enqcmd,-prefetchwt1,-avxneconvert,-tbm,-pconfig,-amx-complex,+ssse3,+cx16,-bmi2,-fma,+popcnt,-avxifma,-f16c,-avx512bitalg,-rdpru,-clwb,+mmx,+sse2,-rdseed,-avx512vbmi2,-prefetchi,-rdpid,-fma4,-avx512vbmi,-shstk,-vaes,-waitpkg,-sgx,+fxsr,-avx512dq,-sse4a"}
>>>
>>> I've confirmed if we changed to `-avxvnniint16` we do not generate 
>>> `vpbroadcastd`.
>>>
>>> W.r.t. how we get the machine attributes generated through our front-end:
>>>
>>>   if (!sys::getHostCPUFeatures(Features))
>>> return std::move(mattr);
>>> 
>>>   // Fill mattr with default values.
>>>   mattr.reserve(Features.getNumItems());
>>>   for (auto  : Features) {
>>> std::string attr(I.first());
>>> mattr.emplace_back(std::string(I.second ? "+" : "-") + attr);
>>>   }
>>>
>>> So, the problem is in getHostCPUFeatures, possibly this line from the patch 
>>> : 
>>> `Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && 
>>> HasAVXSave;`.
>>
>> Does this patch help
>>
>>   diff --git 

[PATCH] D156851: [RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC

[Craig Topper via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG36ac6ac1dbd0: [RISCV] Merge rv32 and rv64 Zvb* intrinsic 
tests. NFC (authored by craig.topper).

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Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
@@ -0,0 +1,53 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV32ZBKX
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBKX
+
+#include 
+
+#if __riscv_xlen == 32
+// RV32ZBKX-LABEL: @xperm8_32(
+// RV32ZBKX-NEXT:  entry:
+// RV32ZBKX-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT:ret i32 [[TMP0]]
+//
+uint32_t xperm8_32(uint32_t rs1, uint32_t rs2)
+{
+  return __builtin_riscv_xperm8_32(rs1, rs2);
+}
+
+// RV32ZBKX-LABEL: @xperm4_32(
+// RV32ZBKX-NEXT:  entry:
+// RV32ZBKX-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT:ret i32 [[TMP0]]
+//
+uint32_t xperm4_32(uint32_t rs1, uint32_t rs2)
+{
+  return __builtin_riscv_xperm4_32(rs1, rs2);
+}
+#endif
+
+#if __riscv_xlen == 64
+// RV64ZBKX-LABEL: @xperm8_64(
+// RV64ZBKX-NEXT:  entry:
+// RV64ZBKX-NEXT:[[TMP0:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT:ret i64 [[TMP0]]
+//
+uint64_t xperm8_64(uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_xperm8_64(rs1, rs2);
+}
+
+// RV64ZBKX-LABEL: @xperm4_64(
+// RV64ZBKX-NEXT:  entry:
+// RV64ZBKX-NEXT:[[TMP0:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT:ret i64 [[TMP0]]
+//
+uint64_t xperm4_64(uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_xperm4_64(rs1, rs2);
+}
+#endif
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
@@ -1,10 +1,14 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV32ZBKC
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZBKC
 
 #include 
 
+#if __riscv_xlen == 64
 // RV64ZBKC-LABEL: @clmul_64(
 // RV64ZBKC-NEXT:  entry:
 // RV64ZBKC-NEXT:[[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
@@ -22,7 +26,13 @@
 uint64_t clmulh_64(uint64_t a, uint64_t b) {
   return __builtin_riscv_clmulh_64(a, b);
 }
+#endif
 
+// RV32ZBKC-LABEL: @clmul_32(
+// RV32ZBKC-NEXT:  entry:
+// RV32ZBKC-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT:ret i32 [[TMP0]]
+//
 // RV64ZBKC-LABEL: @clmul_32(
 // RV64ZBKC-NEXT:  entry:
 // RV64ZBKC-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
@@ -31,3 +41,14 @@
 uint32_t clmul_32(uint32_t a, uint32_t b) {
   return __builtin_riscv_clmul_32(a, b);
 }
+
+#if __riscv_xlen == 32
+// RV32ZBKC-LABEL: @clmulh_32(
+// RV32ZBKC-NEXT:  entry:
+// RV32ZBKC-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT:ret i32 [[TMP0]]
+//
+uint32_t clmulh_32(uint32_t a, uint32_t b) {
+  return __builtin_riscv_clmulh_32(a, b);
+}
+#endif
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1972
 
+// Control Flow Integerity
+include "RISCVInstrInfoZicfiss.td"

Put this with the other RISCVInstrInfoZi* files under "Integer"



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:92
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 
in
+def C_SSPUSHX1 : RVC_SSInst<0b1, "c.sspush", "x1">;
+

Can we merge the X1 and X5 instructions? Looks like the register is encoded?


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[PATCH] D156851: [RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: asb, wangpc, kito-cheng, reames.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: cfe-commits, eopXD, MaskRay.
Herald added a project: clang.

There was some duplication between these tests and
we can merge them by checking __riscv_xlen for the parts
that aren't duplicated.


Repository:
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https://reviews.llvm.org/D156851

Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
@@ -0,0 +1,53 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV32ZBKX
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBKX
+
+#include 
+
+#if __riscv_xlen == 32
+// RV32ZBKX-LABEL: @xperm8_32(
+// RV32ZBKX-NEXT:  entry:
+// RV32ZBKX-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT:ret i32 [[TMP0]]
+//
+uint32_t xperm8_32(uint32_t rs1, uint32_t rs2)
+{
+  return __builtin_riscv_xperm8_32(rs1, rs2);
+}
+
+// RV32ZBKX-LABEL: @xperm4_32(
+// RV32ZBKX-NEXT:  entry:
+// RV32ZBKX-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT:ret i32 [[TMP0]]
+//
+uint32_t xperm4_32(uint32_t rs1, uint32_t rs2)
+{
+  return __builtin_riscv_xperm4_32(rs1, rs2);
+}
+#endif
+
+#if __riscv_xlen == 64
+// RV64ZBKX-LABEL: @xperm8_64(
+// RV64ZBKX-NEXT:  entry:
+// RV64ZBKX-NEXT:[[TMP0:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT:ret i64 [[TMP0]]
+//
+uint64_t xperm8_64(uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_xperm8_64(rs1, rs2);
+}
+
+// RV64ZBKX-LABEL: @xperm4_64(
+// RV64ZBKX-NEXT:  entry:
+// RV64ZBKX-NEXT:[[TMP0:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT:ret i64 [[TMP0]]
+//
+uint64_t xperm4_64(uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_xperm4_64(rs1, rs2);
+}
+#endif
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
@@ -1,10 +1,14 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV32ZBKC
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZBKC
 
 #include 
 
+#if __riscv_xlen == 64
 // RV64ZBKC-LABEL: @clmul_64(
 // RV64ZBKC-NEXT:  entry:
 // RV64ZBKC-NEXT:[[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
@@ -22,7 +26,13 @@
 uint64_t clmulh_64(uint64_t a, uint64_t b) {
   return __builtin_riscv_clmulh_64(a, b);
 }
+#endif
 
+// RV32ZBKC-LABEL: @clmul_32(
+// RV32ZBKC-NEXT:  entry:
+// RV32ZBKC-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT:ret i32 [[TMP0]]
+//
 // RV64ZBKC-LABEL: @clmul_32(
 // RV64ZBKC-NEXT:  entry:
 // RV64ZBKC-NEXT:[[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
@@ -31,3 +41,14 @@
 uint32_t clmul_32(uint32_t a, uint32_t 

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 546315.
craig.topper added a comment.

Add riscv_bitmanip.h to cover all of Zbb and Zbkb


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Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_bitmanip.h
  clang/lib/Headers/riscv_crypto.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c

Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
@@ -6,7 +6,7 @@
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSH
 
-#include 
+#include 
 
 // RV32ZKSH-LABEL: @sm3p0(
 // RV32ZKSH-NEXT:  entry:
@@ -19,7 +19,7 @@
 // RV64ZKSH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm3p0(uint32_t rs1) {
-  return __builtin_riscv_sm3p0(rs1);
+  return __riscv_sm3p0(rs1);
 }
 
 
@@ -34,5 +34,5 @@
 // RV64ZKSH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm3p1(uint32_t rs1) {
-  return __builtin_riscv_sm3p1(rs1);
+  return __riscv_sm3p1(rs1);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
@@ -6,7 +6,7 @@
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSED
 
-#include 
+#include 
 
 // RV32ZKSED-LABEL: @sm4ks(
 // RV32ZKSED-NEXT:  entry:
@@ -19,7 +19,7 @@
 // RV64ZKSED-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm4ks(uint32_t rs1, uint32_t rs2) {
-  return __builtin_riscv_sm4ks(rs1, rs2, 0);
+  return __riscv_sm4ks(rs1, rs2, 0);
 }
 
 // RV32ZKSED-LABEL: @sm4ed(
@@ -33,5 +33,5 @@
 // RV64ZKSED-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm4ed(uint32_t rs1, uint32_t rs2) {
-  return __builtin_riscv_sm4ed(rs1, rs2, 0);
+  return __riscv_sm4ed(rs1, rs2, 0);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
@@ -3,7 +3,7 @@
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKNH
 
-#include 
+#include 
 
 // RV64ZKNH-LABEL: @sha512sig0(
 // RV64ZKNH-NEXT:  entry:
@@ -11,7 +11,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sig0(uint64_t rs1) {
-  return __builtin_riscv_sha512sig0(rs1);
+  return __riscv_sha512sig0(rs1);
 }
 
 
@@ -21,7 +21,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sig1(uint64_t rs1) {
-  return __builtin_riscv_sha512sig1(rs1);
+  return __riscv_sha512sig1(rs1);
 }
 
 
@@ -31,7 +31,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sum0(uint64_t rs1) {
-  return __builtin_riscv_sha512sum0(rs1);
+  return __riscv_sha512sum0(rs1);
 }
 
 
@@ -41,7 +41,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sum1(uint64_t rs1) {
-  return __builtin_riscv_sha512sum1(rs1);
+  return __riscv_sha512sum1(rs1);
 }
 
 
@@ -51,7 +51,7 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sig0(uint32_t rs1) {
-  return __builtin_riscv_sha256sig0(rs1);
+  return __riscv_sha256sig0(rs1);
 }
 
 // RV64ZKNH-LABEL: @sha256sig1(
@@ -60,7 +60,7 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sig1(uint32_t rs1) {
-  return __builtin_riscv_sha256sig1(rs1);
+  return __riscv_sha256sig1(rs1);
 }
 
 
@@ -70,7 +70,7 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sum0(uint32_t rs1) {
-  return __builtin_riscv_sha256sum0(rs1);
+  return __riscv_sha256sum0(rs1);
 }
 
 // RV64ZKNH-LABEL: @sha256sum1(
@@ -79,5 +79,5 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sum1(uint32_t rs1) {
-  return __builtin_riscv_sha256sum1(rs1);
+  return __riscv_sha256sum1(rs1);
 }
Index: 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:233
 
+def uimm10 : Operand, ImmLeaf(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<10>;

Is this used?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:35
+class RV_SSPop _rd, bits<5> _rs1, string opcodestr, string argstr> :
+  RVInstI<0b100, OPC_SYSTEM, (outs GPR:$rd), (ins GPR:$rs1), opcodestr, 
argstr> {
+  let rd = _rd;

Why are there ins and outs here that aren't encoded?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:56
+let Predicates = [HasStdExtZicfiss] in {
+def SSLoadX1: RV_SSPop<0b1, 0b0, "ssload", "x1">;
+def SSLoadX5: RV_SSPop<0b00101, 0b0, "ssload", "x5">;

Need to be able to parse with `ra` instead of x1 and `t0` instead of x5. 

I think you might need a new Operand type so the parse can parse it as a 
register.


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Please update llvm/docs/RISCVUsage.rst


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[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

I think another option could be to do this in SemaChecking.cpp where we 
implement __builtin_riscv_ntl_load and __builtin_riscv_ntl_store. We already do 
custom type checking there. We could detect the missing argument and give it a 
default.


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[PATCH] D155145: [X86] Add AVX-VNNI-INT16 instructions.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D155145#4551526 , @anna wrote:

> In D155145#4544068 , @pengfei wrote:
>
>> In D155145#4543326 , @anna wrote:
>>
>>> We see a crash bisected to this patch about using an illegal instruction. 
>>> Here's the CPUInfo for the machine:
>>>
>>>   CPU info:
>>>   current cpu id: 22
>>>   total 32(physical cores 16) (assigned logical cores 32) (assigned 
>>> physical cores 16) (assigned_sockets:2 of 2) (8 cores per cpu, 2 threads 
>>> per core) family 6 model 45 stepping 7 microcode 0x71a, cmov, cx8, fxsr, 
>>> mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, vzeroupper, avx, aes, 
>>> clmul, ht, tsc, tscinvbit, tscinv, clflush
>>>   AvgLoads: 0.30, 0.10, 0.18
>>>   CPU Model and flags from /proc/cpuinfo:
>>>   model name  : Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz
>>>   flags   : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge 
>>> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall 
>>> nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl 
>>> xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl 
>>> vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic popcnt 
>>> tsc_deadline_timer aes xsave avx lahf_lm epb pti ssbd ibrs ibpb stibp 
>>> tpr_shadow vnmi flexpriority ept vpid xsaveopt dtherm ida arat pln pts 
>>> md_clear flush_l1d
>>>   Online cpus: 0-31
>>>   Offline cpus:
>>>   BIOS frequency limitation: 
>>>   Frequency switch latency (ns): 2
>>>   Available cpu frequencies: 
>>>   Current governor: schedutil
>>>   Core performance/turbo boost: 
>>>
>>> I don't see `avxvnniint16` in the flags list nor avx2. So, this (relatively 
>>> new) instruction shouldn't be generated for this machine. Any ideas on why 
>>> this might be happening?
>>
>> As far as I can see from the patch, the only way to generate avxvnniint16 
>> instructions is to call its specific intrinsics explicitly. And we will 
>> check compiling options in FE before allowing to call the intrinsics. We do 
>> have an optimization to generate vnni instructions without intrinsics, but 
>> we haven't extend it to avxvnniint16 so far.
>> So I don't know what's wrong in your case, could you provide a reproducer 
>> for your problem?
>
> I've investigated what is going on. With this patch, we are now passing in 
> `+avxvnniint16` into machine attributes. With that attribute, we now generate 
> an instruction which is illegal on sandybridge machine:
>
>0x3013f2af:jmpq   0x3013f09b
>  0x3013f2b4:  mov%rax,%rdi
>  0x3013f2b7:  and$0xfff0,%rdi
>   => 0x3013f2bb:  vpbroadcastd %xmm0,%ymm2
>  0x3013f2c0:  vpbroadcastd %xmm1,%ymm3
>
> The instruction `vpbroadcastd %xmm0,%ymm2` requires `AVX2` CPU flag: 
> https://www.felixcloutier.com/x86/vpbroadcast. However, the machine has only 
> AVX flag.
>
> This is the complete mattr generated:
>
>   !3 = 
> !{!"-mattr=-prfchw,-cldemote,+avx,+aes,+sahf,+pclmul,-xop,+crc32,-xsaves,-avx512fp16,-sm4,+sse4.1,-avx512ifma,+xsave,-avx512pf,+sse4.2,-tsxldtrk,-ptwrite,-widekl,-sm3,-invpcid,+64bit,-xsavec,-avx512vpopcntdq,+cmov,-avx512vp2intersect,-avx512cd,-movbe,-avxvnniint8,-avx512er,-amx-int8,-kl,-sha512,-avxvnni,-rtm,-adx,-avx2,-hreset,-movdiri,-serialize,-vpclmulqdq,-avx512vl,-uintr,-clflushopt,-raoint,-cmpccxadd,-bmi,-amx-tile,+sse,-gfni,+avxvnniint16,-amx-fp16,+xsaveopt,-rdrnd,-avx512f,-amx-bf16,-avx512bf16,-avx512vnni,+cx8,-avx512bw,+sse3,-pku,-fsgsbase,-clzero,-mwaitx,-lwp,-lzcnt,-sha,-movdir64b,-wbnoinvd,-enqcmd,-prefetchwt1,-avxneconvert,-tbm,-pconfig,-amx-complex,+ssse3,+cx16,-bmi2,-fma,+popcnt,-avxifma,-f16c,-avx512bitalg,-rdpru,-clwb,+mmx,+sse2,-rdseed,-avx512vbmi2,-prefetchi,-rdpid,-fma4,-avx512vbmi,-shstk,-vaes,-waitpkg,-sgx,+fxsr,-avx512dq,-sse4a"}
>
> I've confirmed if we changed to `-avxvnniint16` we do not generate 
> `vpbroadcastd`.
>
> W.r.t. how we get the machine attributes generated through our front-end:
>
>   if (!sys::getHostCPUFeatures(Features))
> return std::move(mattr);
> 
>   // Fill mattr with default values.
>   mattr.reserve(Features.getNumItems());
>   for (auto  : Features) {
> std::string attr(I.first());
> mattr.emplace_back(std::string(I.second ? "+" : "-") + attr);
>   }
>
> So, the problem is in getHostCPUFeatures, possibly this line from the patch : 
> `Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && 
> HasAVXSave;`.

Does this patch help

  diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
  index 1141df09307c..11a6879fb76a 100644
  --- a/llvm/lib/TargetParser/Host.cpp
  +++ b/llvm/lib/TargetParser/Host.cpp
  @@ -1769,7 +1769,7 @@ bool sys::getHostCPUFeatures(StringMap ) 
{
 Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
 Features["amx-int8"]   = 

[PATCH] D156821: [CodeGen] [ubsan] Respect integer overflow handling in abs builtin

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:1807
+
+  // Do not emit checks for disabled sanitizers to support recover
+  SmallVector, 2> Checks;

recover -> recovery?

Period at the end of the comment


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[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/AST/Type.cpp:2356
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType())
+return true;




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[PATCH] D155668: [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D155668#4548454 , @jrtc27 wrote:

> Uh, why are there clang/test/Sema/aarch64* tests full of RISC-V extension 
> names? That's not right at all. One of them is coming from 
> https://reviews.llvm.org/D135011, I haven't traced the rest back, but that's 
> clearly wrong. The test looks to be a copy of the RISC-V one with tweaks to 
> change riscv(64) to arm/aarch64, and `  -target-feature +sve` (with two 
> spaces) added.

Fixed in 690edeab78ba6996a44f6fd9e8fce79cb78e7737 



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[PATCH] D156507: [RISCV] Upgrade Zihintntl extension to version 1.0 and move out of experimental state.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

We already have https://reviews.llvm.org/D151547 in review


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[PATCH] D156321: [Clang][RISCV] Remove RVV intrinsics `vread_csr`,`vwrite_csr`

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

I have deleted the two TODOs in r02c11c5aed59624046125cf512c12f70d2fa358d


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 

craig.topper wrote:
> asb wrote:
> > imkiva wrote:
> > > wangpc wrote:
> > > > I think the comment is outdated here. `E` can be combined with all 
> > > > other extensions according to spec:
> > > > > Unless otherwise stated, standard extensions compatible with RV32I 
> > > > > and RV64I are also compatible with RV32E and RV64E, respectively.
> > > > And, please see also D70401 for more context.
> > > I downloaded the specification from 
> > > [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf),
> > >  and in page 34 the footnote says:
> > > 
> > > > RV32E can be combined with all current standard extensions. Defining 
> > > > the F, D, and Q extensions as having a 16-entry floating point register 
> > > > file when combined with RV32E was considered but **decided against**. 
> > > > To support systems with reduced floating-point register state, we 
> > > > intend to define a “Zfinx” extension...
> > > 
> > > It seems in the spec version 20191213, they rejected the combination of 
> > > `E` with standard floating-point extensions, instead, a separate 
> > > extension `Zfinx` is chosen for the original purpose.
> > > I am not sure if there's any newer specification that decides to allow 
> > > this combination.
> > > 
> > > 
> > There's a link to the ratified version on 
> > https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see 
> > https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view
> > 
> > As @wangpc says, the restriction was removed and so the comment is out of 
> > date.
> > RV32E can be combined with all current standard extensions. Defining the F, 
> > D, and Q extensions as having a 16-entry floating point register file when 
> > combined with RV32E was considered but decided against. To support systems 
> > with reduced floating-point register state, we intend to define a “Zfinx” 
> > extension...
> 
> That really only says that the register file for F and D is still 32 entries 
> with RV32E. It doesn't say they are incompatible. Maybe there was some even 
> older text?
There was older text removed here 
https://github.com/riscv/riscv-isa-manual/commit/4845f5d61f96a827ec4d21d2c5a80b6bf7881e56


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 

asb wrote:
> imkiva wrote:
> > wangpc wrote:
> > > I think the comment is outdated here. `E` can be combined with all other 
> > > extensions according to spec:
> > > > Unless otherwise stated, standard extensions compatible with RV32I and 
> > > > RV64I are also compatible with RV32E and RV64E, respectively.
> > > And, please see also D70401 for more context.
> > I downloaded the specification from 
> > [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf),
> >  and in page 34 the footnote says:
> > 
> > > RV32E can be combined with all current standard extensions. Defining the 
> > > F, D, and Q extensions as having a 16-entry floating point register file 
> > > when combined with RV32E was considered but **decided against**. To 
> > > support systems with reduced floating-point register state, we intend to 
> > > define a “Zfinx” extension...
> > 
> > It seems in the spec version 20191213, they rejected the combination of `E` 
> > with standard floating-point extensions, instead, a separate extension 
> > `Zfinx` is chosen for the original purpose.
> > I am not sure if there's any newer specification that decides to allow this 
> > combination.
> > 
> > 
> There's a link to the ratified version on 
> https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see 
> https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view
> 
> As @wangpc says, the restriction was removed and so the comment is out of 
> date.
> RV32E can be combined with all current standard extensions. Defining the F, 
> D, and Q extensions as having a 16-entry floating point register file when 
> combined with RV32E was considered but decided against. To support systems 
> with reduced floating-point register state, we intend to define a “Zfinx” 
> extension...

That really only says that the register file for F and D is still 32 entries 
with RV32E. It doesn't say they are incompatible. Maybe there was some even 
older text?


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
   // Additional dependency checks.
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
+  // The 'q' extension requires rv64.
+  if (XLen != 64 && Exts.count("q"))

craig.topper wrote:
> I'm not sure this is true.
The restriction was removed 4 years ago 
https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
   // Additional dependency checks.
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
+  // The 'q' extension requires rv64.
+  if (XLen != 64 && Exts.count("q"))

I'm not sure this is true.


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:75
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zicfisslp {{.*$}}
 

This needs to be renamed to remove lp



Comment at: clang/test/Preprocessor/riscv-target-features.c:725
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfisslp0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISSLP-EXT %s

This needs to be renamed to remove lp



Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:84
+: SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",
+   "'zicfiss' (Shadow stack)">;
+def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,

Zicfiss



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1921
 include "RISCVInstrInfoZicond.td"
+include "RISCVInstrInfoZicfiss.td"
 

This needs to be rebased, the files here were moved into groups.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:1
+//===-- RISCVInstrInfoZ.td - RISC-V CFG -*- tablegen -*-===//
+//

Filename doesn't match



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:35
+class RV_SSPop rd, bits<5> rs1, string opcodestr, string argstr> :
+  RVInst<(outs GPR:$rd), (ins GPR:$rs1), opcodestr, argstr, [], InstFormatI> {
+  let Inst{31-20} = 0b10011100;

Can we use RVInstI by adding `let imm12 = 0b10011100` to the body?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:66
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSPINC : RVInst<(outs), (ins uimm5nonzero:$imm), "sspinc", "$imm", [], 
InstFormatI> {
+  bits<5> imm;

Can this use RVInstI with lets for imm12, rs1, and rd?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:75
+
+def SSPRR : RVInst<(outs GPRNoX0:$rd), (ins), "ssprr", "$rd", [], InstFormatR> 
{
+  bits<5> rd;

Can this use RVInstR?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:87
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 
in {
+def SSPUSH : RVInst<(outs), (ins GPRRA:$rs2), "sspush", "$rs2", [], 
InstFormatR> {
+  bits<5> rs2;

Can this use RVInstR?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:98
+def SSAMOSWAP :
+  RVInst<(outs GPRNoX0:$dest), (ins GPR:$addr, GPR:$src),
+ "ssamoswap", "$dest, $src, (${addr})", [], InstFormatR> {

RVInstR


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[PATCH] D156248: [Headers][doc] Add description of _mm256_movemask_epi8

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 542121.
craig.topper added a comment.

Rebase after using mem2reg.
Fix a couple copy/paste mistakes that were much easier to spot with mem2reg.


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  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_crypto.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c

Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
@@ -6,7 +6,7 @@
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSH
 
-#include 
+#include 
 
 // RV32ZKSH-LABEL: @sm3p0(
 // RV32ZKSH-NEXT:  entry:
@@ -19,7 +19,7 @@
 // RV64ZKSH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm3p0(uint32_t rs1) {
-  return __builtin_riscv_sm3p0(rs1);
+  return __riscv_sm3p0(rs1);
 }
 
 
@@ -34,5 +34,5 @@
 // RV64ZKSH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm3p1(uint32_t rs1) {
-  return __builtin_riscv_sm3p1(rs1);
+  return __riscv_sm3p1(rs1);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
@@ -6,7 +6,7 @@
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSED
 
-#include 
+#include 
 
 // RV32ZKSED-LABEL: @sm4ks(
 // RV32ZKSED-NEXT:  entry:
@@ -19,7 +19,7 @@
 // RV64ZKSED-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm4ks(uint32_t rs1, uint32_t rs2) {
-  return __builtin_riscv_sm4ks(rs1, rs2, 0);
+  return __riscv_sm4ks(rs1, rs2, 0);
 }
 
 // RV32ZKSED-LABEL: @sm4ed(
@@ -33,5 +33,5 @@
 // RV64ZKSED-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sm4ed(uint32_t rs1, uint32_t rs2) {
-  return __builtin_riscv_sm4ed(rs1, rs2, 0);
+  return __riscv_sm4ed(rs1, rs2, 0);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
@@ -3,7 +3,7 @@
 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKNH
 
-#include 
+#include 
 
 // RV64ZKNH-LABEL: @sha512sig0(
 // RV64ZKNH-NEXT:  entry:
@@ -11,7 +11,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sig0(uint64_t rs1) {
-  return __builtin_riscv_sha512sig0(rs1);
+  return __riscv_sha512sig0(rs1);
 }
 
 
@@ -21,7 +21,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sig1(uint64_t rs1) {
-  return __builtin_riscv_sha512sig1(rs1);
+  return __riscv_sha512sig1(rs1);
 }
 
 
@@ -31,7 +31,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sum0(uint64_t rs1) {
-  return __builtin_riscv_sha512sum0(rs1);
+  return __riscv_sha512sum0(rs1);
 }
 
 
@@ -41,7 +41,7 @@
 // RV64ZKNH-NEXT:ret i64 [[TMP0]]
 //
 uint64_t sha512sum1(uint64_t rs1) {
-  return __builtin_riscv_sha512sum1(rs1);
+  return __riscv_sha512sum1(rs1);
 }
 
 
@@ -51,7 +51,7 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sig0(uint32_t rs1) {
-  return __builtin_riscv_sha256sig0(rs1);
+  return __riscv_sha256sig0(rs1);
 }
 
 // RV64ZKNH-LABEL: @sha256sig1(
@@ -60,7 +60,7 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sig1(uint32_t rs1) {
-  return __builtin_riscv_sha256sig1(rs1);
+  return __riscv_sha256sig1(rs1);
 }
 
 
@@ -70,7 +70,7 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sum0(uint32_t rs1) {
-  return __builtin_riscv_sha256sum0(rs1);
+  return __riscv_sha256sum0(rs1);
 }
 
 // RV64ZKNH-LABEL: @sha256sum1(
@@ -79,5 +79,5 @@
 // RV64ZKNH-NEXT:ret i32 [[TMP0]]
 //
 uint32_t sha256sum1(uint32_t rs1) {
-  return __builtin_riscv_sha256sum1(rs1);
+  return __riscv_sha256sum1(rs1);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
===
--- 

[PATCH] D155668: [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3055c5815ac0: [RISCV] Upgrade Zvfh version to 1.0 and move 
out of experimental state. (authored by craig.topper).

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clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  

[PATCH] D155674: [RISCV] Update zihintntl to 1p0

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Looks like we have two patches for this now. D151547 



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[PATCH] D155668: [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: asb, reames, kito-cheng.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, 
hiraditya, arichardson, qcolombet, MatzeB.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This has been ratified according to 
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155668

Files:
  clang/lib/Sema/SemaChecking.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:4576
+  case RISCVVector::BI__builtin_rvv_vaeskf1_vi_ta:
+  case RISCVVector::BI__builtin_rvv_vsm4k_vi_ta:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);

craig.topper wrote:
> craig.topper wrote:
> > eopXD wrote:
> > > Valid range of `vaeskf1`, `vaeskf2` seems to be 0 to 15. [0]
> > > Valid range of `vsm4k` seems to be 0 to 7 [1].
> > > 
> > > 
> > > 
> > > [0] 
> > > https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vaeskf1.adoc
> > >  
> > > [1] 
> > > https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vsm4k.adoc
> > I think the field in the instruction is 5 bits, but vaeskf1 and vaeskf2 
> > ignore bit 4. The true valid range is 1-10. The other values are aliased to 
> > one of the valid values. Should the intrinsic interface expose all 32 
> > possible values or just 1-10?
> 1-10 is the valid range for vaeskf1. vaeskf2 is 2-14.
Let's leave it 0-31 for now and maybe start a conversation on crypto or 
intrinsic github.


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[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 541759.
craig.topper added a comment.

Fix name of zip/unzip builtin


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155647/new/

https://reviews.llvm.org/D155647

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_crypto.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c

Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
@@ -4,45 +4,57 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSH
 
-#include 
+#include 
 
 // RV32ZKSH-LABEL: @sm3p0(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p0(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p0(uint32_t rs1) {
-  return __builtin_riscv_sm3p0(rs1);
+  return __riscv_sm3p0(rs1);
 }
 
 
 // RV32ZKSH-LABEL: @sm3p1(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p1(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p1(uint32_t rs1) {
-  return __builtin_riscv_sm3p1(rs1);
+  return __riscv_sm3p1(rs1);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
@@ -4,7 +4,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSED
 
-#include 

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 541752.
craig.topper added a comment.

Fix file description


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155647/new/

https://reviews.llvm.org/D155647

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_crypto.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c

Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
@@ -4,45 +4,57 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSH
 
-#include 
+#include 
 
 // RV32ZKSH-LABEL: @sm3p0(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p0(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p0(uint32_t rs1) {
-  return __builtin_riscv_sm3p0(rs1);
+  return __riscv_sm3p0(rs1);
 }
 
 
 // RV32ZKSH-LABEL: @sm3p1(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p1(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p1(uint32_t rs1) {
-  return __builtin_riscv_sm3p1(rs1);
+  return __riscv_sm3p1(rs1);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
@@ -4,7 +4,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSED
 
-#include 

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 541751.
craig.topper added a comment.

git add the header


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155647/new/

https://reviews.llvm.org/D155647

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/riscv_crypto.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c

Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
@@ -4,45 +4,57 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSH
 
-#include 
+#include 
 
 // RV32ZKSH-LABEL: @sm3p0(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p0(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p0(uint32_t rs1) {
-  return __builtin_riscv_sm3p0(rs1);
+  return __riscv_sm3p0(rs1);
 }
 
 
 // RV32ZKSH-LABEL: @sm3p1(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p1(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p1(uint32_t rs1) {
-  return __builtin_riscv_sm3p1(rs1);
+  return __riscv_sm3p1(rs1);
 }
Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
@@ -4,7 +4,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSED
 
-#include 
+#include 

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: asb, VincentWu, wangpc, kito-cheng.
Herald added subscribers: jobnoorman, luke, vkmr, frasercrmck, luismarques, 
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
niosHD, sabuasal, simoncook, johnrusso, rbar, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: eopXD, MaskRay.
Herald added a project: clang.

This adds riscv_crypto.h

This is based on the proposed spec here 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

Tests that previously used builtins directly now use the intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155647

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c

Index: clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
===
--- clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
+++ clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
@@ -4,45 +4,57 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64ZKSH
 
-#include 
+#include 
 
 // RV32ZKSH-LABEL: @sm3p0(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p0(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[TMP1]])
+// RV64ZKSH-NEXT:ret i32 [[TMP2]]
 //
 uint32_t sm3p0(uint32_t rs1) {
-  return __builtin_riscv_sm3p0(rs1);
+  return __riscv_sm3p0(rs1);
 }
 
 
 // RV32ZKSH-LABEL: @sm3p1(
 // RV32ZKSH-NEXT:  entry:
+// RV32ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV32ZKSH-NEXT:ret i32 [[TMP1]]
+// RV32ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV32ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// RV32ZKSH-NEXT:ret i32 [[TMP2]]
 //
 // RV64ZKSH-LABEL: @sm3p1(
 // RV64ZKSH-NEXT:  entry:
+// RV64ZKSH-NEXT:[[__X_ADDR_I:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:[[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV64ZKSH-NEXT:store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV64ZKSH-NEXT:[[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKSH-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP0]])
-// RV64ZKSH-NEXT:ret i32 [[TMP1]]
+// RV64ZKSH-NEXT:store i32 [[TMP0]], ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP1:%.*]] = load i32, ptr [[__X_ADDR_I]], align 4
+// RV64ZKSH-NEXT:[[TMP2:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[TMP1]])
+// 

[PATCH] D155414: [Clang][RISCV] Guard RVV intrinsics types that is not available when ELEN < 64

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155414/new/

https://reviews.llvm.org/D155414

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[PATCH] D155416: [Clang][RISCV] Improve diagnostic message for full multiply intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM for now, but long term I think we need a mechanism to do this builtins 
that require extensions like vector crypto.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155416/new/

https://reviews.llvm.org/D155416

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[PATCH] D155495: [RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd53d842d12ce: [RISCV][AArch64][IRGen] Add a special case to 
CodeGenFunction::EmitCall for… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D155495?vs=541123=541614#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155495/new/

https://reviews.llvm.org/D155495

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c


Index: clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
===
--- clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
+++ clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
@@ -38,11 +38,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <8 x i32>, align 8
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i32>, ptr [[COERCE1]], align 8, 
!tbaa [[TBAA4:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  
@llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], 
i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 vint32m1_t sizeless_caller(vint32m1_t x) {
   return fixed_callee(x);
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -41,11 +41,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 16
-// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[COERCE1]], align 16, 
!tbaa [[TBAA6:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  
@llvm.vector.insert.nxv4i32.v16i32( undef, <16 x i32> 
[[TMP1]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 svint32_t sizeless_caller(svint32_t x) {
   return fixed_callee(x);
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -5743,6 +5743,20 @@
 llvm_unreachable("bad evaluation kind");
   }
 
+  // If coercing a fixed vector from a scalable vector for ABI
+  // compatibility, and the types match, use the llvm.vector.extract
+  // intrinsic to perform the conversion.
+  if (auto *FixedDst = dyn_cast(RetIRTy)) {
+llvm::Value *V = CI;
+if (auto *ScalableSrc = 
dyn_cast(V->getType())) {
+  if (FixedDst->getElementType() == ScalableSrc->getElementType()) {
+llvm::Value *Zero = llvm::Constant::getNullValue(CGM.Int64Ty);
+V = Builder.CreateExtractVector(FixedDst, V, Zero, "cast.fixed");
+return RValue::get(V);
+  }
+}
+  }
+
   Address DestPtr = ReturnValue.getValue();
   bool DestIsVolatile = ReturnValue.isVolatile();
 


Index: clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
===
--- clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
+++ clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
@@ -38,11 +38,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <8 x i32>, align 8
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i32>, ptr [[COERCE1]], align 8, !tbaa [[TBAA4:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 vint32m1_t sizeless_caller(vint32m1_t x) {
   return fixed_callee(x);
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -41,11 +41,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 16
-// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[COERCE1]], align 16, !tbaa [[TBAA6:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  @llvm.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP1]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 svint32_t sizeless_caller(svint32_t x) {
   return fixed_callee(x);
Index: clang/lib/CodeGen/CGCall.cpp

[PATCH] D155222: [RISCV][AArch64][IRGen] Add scalable->fixed as a special case in CreateCoercedStore.

[Craig Topper via Phabricator via cfe-commits]

craig.topper abandoned this revision.
craig.topper added a comment.

Abandoning in favor of D155495 


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:4576
+  case RISCVVector::BI__builtin_rvv_vaeskf1_vi_ta:
+  case RISCVVector::BI__builtin_rvv_vsm4k_vi_ta:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);

craig.topper wrote:
> eopXD wrote:
> > Valid range of `vaeskf1`, `vaeskf2` seems to be 0 to 15. [0]
> > Valid range of `vsm4k` seems to be 0 to 7 [1].
> > 
> > 
> > 
> > [0] 
> > https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vaeskf1.adoc
> >  
> > [1] 
> > https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vsm4k.adoc
> I think the field in the instruction is 5 bits, but vaeskf1 and vaeskf2 
> ignore bit 4. The true valid range is 1-10. The other values are aliased to 
> one of the valid values. Should the intrinsic interface expose all 32 
> possible values or just 1-10?
1-10 is the valid range for vaeskf1. vaeskf2 is 2-14.


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:12
+//
+vint16mf4_t test_vwsll_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+  return __riscv_vwsll_vv_i16mf4(op1, op2, vl);

craig.topper wrote:
> It doesn't make sense for op2 to be signed. It's a shift amount, its always a 
> positive number
The spec doesn't define signed versions of these instrinsics from what I can 
see.


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2405
+  defvar suffix = !if(IsVV, "vv", "vi");
+  defvar prototype = !if(IsVV, "UvUvUvUv", "UvUvUvKz");
+  defm "" : RVVBuiltinSet;

Can we split this into two classes and get rid of IsVV?


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:4576
+  case RISCVVector::BI__builtin_rvv_vaeskf1_vi_ta:
+  case RISCVVector::BI__builtin_rvv_vsm4k_vi_ta:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);

eopXD wrote:
> Valid range of `vaeskf1`, `vaeskf2` seems to be 0 to 15. [0]
> Valid range of `vsm4k` seems to be 0 to 7 [1].
> 
> 
> 
> [0] 
> https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vaeskf1.adoc
>  
> [1] 
> https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vsm4k.adoc
I think the field in the instruction is 5 bits, but vaeskf1 and vaeskf2 ignore 
bit 4. The true valid range is 1-10. The other values are aliased to one of the 
valid values. Should the intrinsic interface expose all 32 possible values or 
just 1-10?



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:12
+//
+vint16mf4_t test_vwsll_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+  return __riscv_vwsll_vv_i16mf4(op1, op2, vl);

It doesn't make sense for op2 to be signed. It's a shift amount, its always a 
positive number



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:22
+//
+vint16mf4_t test_vwsll_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) {
+  return __riscv_vwsll_vx_i16mf4(op1, op2, vl);

scalar shift amounts should be size_t


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[PATCH] D155414: [Clang][RISCV] Guard RVV intrinsics types that is not available when ELEN < 64

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:5336
+  // least zve64x
+  if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) &&
+   !TI.hasFeature("zve64x")) ||

Can we do

```
if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) ||
 Ty->isRVVType(/* ElementCount */ 1)) &&
!TI.hasFeature("zve64x"))
```


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[PATCH] D155495: [RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
craig.topper added reviewers: bsmith, sdesmalen, c-rhodes, joechrisellis.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
kristof.beyls, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: wangpc, alextsao1999, eopXD.
Herald added a project: clang.

Before falling back to CreateCoercedStore, detect a scalable vector
return being coerced to fixed vector. Handle it using a vector.extract
intrinsic without going through memory.

This is an alternative to D155222 .


Repository:
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Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c


Index: clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
===
--- clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
+++ clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
@@ -38,11 +38,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <8 x i32>, align 8
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i32>, ptr [[COERCE1]], align 8, 
!tbaa [[TBAA4:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  
@llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], 
i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 vint32m1_t sizeless_caller(vint32m1_t x) {
   return fixed_callee(x);
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -41,11 +41,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 16
-// CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[COERCE1]], align 16, 
!tbaa [[TBAA6:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  
@llvm.vector.insert.nxv4i32.v16i32( undef, <16 x i32> 
[[TMP1]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 svint32_t sizeless_caller(svint32_t x) {
   return fixed_callee(x);
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -5743,6 +5743,20 @@
 llvm_unreachable("bad evaluation kind");
   }
 
+  // If coercing a fixed vector from a scalable vector for ABI
+  // compatibility, and the types match, use the llvm.vector.extract
+  // intrinsic to perform the conversion.
+  if (auto *FixedDst = 
dyn_cast(ConvertType(RetTy))) {
+llvm::Value *V = CI;
+if (auto *ScalableSrc = 
dyn_cast(V->getType())) {
+  if (FixedDst->getElementType() == ScalableSrc->getElementType()) {
+llvm::Value *Zero = llvm::Constant::getNullValue(CGM.Int64Ty);
+V = Builder.CreateExtractVector(FixedDst, V, Zero, "cast.fixed");
+return RValue::get(V);
+  }
+}
+  }
+
   Address DestPtr = ReturnValue.getValue();
   bool DestIsVolatile = ReturnValue.isVolatile();
 


Index: clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
===
--- clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
+++ clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
@@ -38,11 +38,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <8 x i32>, align 8
-// CHECK-NEXT:store  [[X:%.*]], ptr [[COERCE1]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load <8 x i32>, ptr [[COERCE1]], align 8, !tbaa [[TBAA4:![0-9]+]]
-// CHECK-NEXT:[[CASTSCALABLESVE2:%.*]] = tail call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE2]]
+// CHECK-NEXT:ret  [[X:%.*]]
 //
 vint32m1_t sizeless_caller(vint32m1_t x) {
   return fixed_callee(x);
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -41,11 +41,7 @@
 
 // CHECK-LABEL: @sizeless_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[COERCE1:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:store  [[X:%.*]], ptr 

[PATCH] D154647: [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa64b3e92c7cb: [RISCV] Re-define sha256, Zksed, and Zksh 
intrinsics to use i32 types. (authored by craig.topper).

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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
  llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
  llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

Index: llvm/test/CodeGen/RISCV/sextw-removal.ll
===
--- llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1319,13 +1319,11 @@
 ; NOREMOVAL-NEXT:addi sp, sp, 32
 ; NOREMOVAL-NEXT:ret
 bb:
-  %sext = sext i32 %arg1 to i64
-  %i = call i64 @llvm.riscv.sha256sig0.i64(i64 %sext)
-  %trunc = trunc i64 %i to i32
+  %i = call i32 @llvm.riscv.sha256sig0(i32 %arg1)
   br label %bb2
 
 bb2:  ; preds = %bb2, %bb
-  %i3 = phi i32 [ %trunc, %bb ], [ %i5, %bb2 ]
+  %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
@@ -1334,7 +1332,7 @@
 bb7:  ; preds = %bb2
   ret void
 }
-declare i64 @llvm.riscv.sha256sig0.i64(i64)
+declare i32 @llvm.riscv.sha256sig0(i32)
 
 ; The type promotion of %7 forms a sext_inreg, but %7 and %6 are combined to
 ; form a sh2add. This leaves behind a sext.w that isn't needed.
Index: llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
 
-declare i64 @llvm.riscv.sm3p0.i64(i64);
+declare i32 @llvm.riscv.sm3p0(i32);
 
-define i64 @sm3p0_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p0_i64:
+define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p0_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p0 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p0.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
+  ret i32 %val
 }
 
-declare i64 @llvm.riscv.sm3p1.i64(i64);
+declare i32 @llvm.riscv.sm3p1(i32);
 
-define i64 @sm3p1_i64(i64 %a) nounwind {
-; RV64ZKSH-LABEL: sm3p1_i64:
+define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
+; RV64ZKSH-LABEL: sm3p1_i32:
 ; RV64ZKSH:   # %bb.0:
 ; RV64ZKSH-NEXT:sm3p1 a0, a0
 ; RV64ZKSH-NEXT:ret
-  %val = call i64 @llvm.riscv.sm3p1.i64(i64 %a)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
+  ret i32 %val
 }
Index: llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
@@ -2,24 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zksed -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZKSED
 
-declare i64 @llvm.riscv.sm4ks.i64(i64, i64, i32);
+declare i32 @llvm.riscv.sm4ks(i32, i32, i32);
 
-define i64 @sm4ks_i64(i64 %a, i64 %b) nounwind {
-; RV64ZKSED-LABEL: sm4ks_i64:
+define signext i32 @sm4ks_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZKSED-LABEL: sm4ks_i32:
 ; RV64ZKSED:   # %bb.0:
-; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 0
+; RV64ZKSED-NEXT:sm4ks a0, a0, a1, 2
 ; RV64ZKSED-NEXT:ret
-  %val = call i64 @llvm.riscv.sm4ks.i64(i64 %a, i64 %b, i32 0)
-  ret i64 %val
+  %val = call i32 @llvm.riscv.sm4ks(i32 %a, i32 %b, i32 2)
+  ret i32 %val
 }
 

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Update ReleaseNotes?


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[PATCH] D155220: [IRGen] Remove 'Sve' from the name of some IR names that are shared with RISC-V now.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe8dc9dcd7df7: [IRGen] Remove Sve from the name 
of some IR names that are shared with RISC-V… (authored by craig.topper).

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Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGExprScalar.cpp


Index: clang/lib/CodeGen/CGExprScalar.cpp
===
--- clang/lib/CodeGen/CGExprScalar.cpp
+++ clang/lib/CodeGen/CGExprScalar.cpp
@@ -2152,7 +2152,7 @@
   llvm::Value *UndefVec = llvm::UndefValue::get(DstTy);
   llvm::Value *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
   llvm::Value *Result = Builder.CreateInsertVector(
-  DstTy, UndefVec, Src, Zero, "castScalableSve");
+  DstTy, UndefVec, Src, Zero, "cast.scalable");
   if (NeedsBitCast)
 Result = Builder.CreateBitCast(Result, OrigType);
   return Result;
@@ -2176,7 +2176,7 @@
 }
 if (ScalableSrc->getElementType() == FixedDst->getElementType()) {
   llvm::Value *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
-  return Builder.CreateExtractVector(DstTy, Src, Zero, "castFixedSve");
+  return Builder.CreateExtractVector(DstTy, Src, Zero, "cast.fixed");
 }
   }
 }
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -1311,7 +1311,7 @@
 auto *UndefVec = llvm::UndefValue::get(ScalableDst);
 auto *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
 llvm::Value *Result = CGF.Builder.CreateInsertVector(
-ScalableDst, UndefVec, Load, Zero, "castScalableSve");
+ScalableDst, UndefVec, Load, Zero, "cast.scalable");
 if (NeedsBitcast)
   Result = CGF.Builder.CreateBitCast(Result, OrigType);
 return Result;
@@ -3146,7 +3146,7 @@
 assert(NumIRArgs == 1);
 Coerced->setName(Arg->getName() + ".coerce");
 
ArgVals.push_back(ParamValue::forDirect(Builder.CreateExtractVector(
-VecTyTo, Coerced, Zero, "castFixedSve")));
+VecTyTo, Coerced, Zero, "cast.fixed")));
 break;
   }
 }


Index: clang/lib/CodeGen/CGExprScalar.cpp
===
--- clang/lib/CodeGen/CGExprScalar.cpp
+++ clang/lib/CodeGen/CGExprScalar.cpp
@@ -2152,7 +2152,7 @@
   llvm::Value *UndefVec = llvm::UndefValue::get(DstTy);
   llvm::Value *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
   llvm::Value *Result = Builder.CreateInsertVector(
-  DstTy, UndefVec, Src, Zero, "castScalableSve");
+  DstTy, UndefVec, Src, Zero, "cast.scalable");
   if (NeedsBitCast)
 Result = Builder.CreateBitCast(Result, OrigType);
   return Result;
@@ -2176,7 +2176,7 @@
 }
 if (ScalableSrc->getElementType() == FixedDst->getElementType()) {
   llvm::Value *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
-  return Builder.CreateExtractVector(DstTy, Src, Zero, "castFixedSve");
+  return Builder.CreateExtractVector(DstTy, Src, Zero, "cast.fixed");
 }
   }
 }
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -1311,7 +1311,7 @@
 auto *UndefVec = llvm::UndefValue::get(ScalableDst);
 auto *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
 llvm::Value *Result = CGF.Builder.CreateInsertVector(
-ScalableDst, UndefVec, Load, Zero, "castScalableSve");
+ScalableDst, UndefVec, Load, Zero, "cast.scalable");
 if (NeedsBitcast)
   Result = CGF.Builder.CreateBitCast(Result, OrigType);
 return Result;
@@ -3146,7 +3146,7 @@
 assert(NumIRArgs == 1);
 Coerced->setName(Arg->getName() + ".coerce");
 ArgVals.push_back(ParamValue::forDirect(Builder.CreateExtractVector(
-VecTyTo, Coerced, Zero, "castFixedSve")));
+VecTyTo, Coerced, Zero, "cast.fixed")));
 break;
   }
 }
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