[PATCH] D97187: [Clang][Sema] Warn when function argument is less aligned than parameter

2021-03-02 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM . Just a few coding style nits to fix. But please wait a couple of days to see if someone else has anything else to say. Comment at:

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-07-30 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Ping ... ping... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-07-24 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-07-17 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked 6 inline comments as done. dnsampaio added a comment. Indeed not all of them. Fixed this time. Comment at: clang/include/clang/Basic/CodeGenOptions.def:396 +/// according to the field declaring type width. +CODEGENOPT(ForceNoAAPCSBitfieldWidth, 1, 0) +

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-07-15 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Herald added a subscriber: dang. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 ___ cfe-commits mailing list

[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

2020-06-12 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Perhaps we could move to making half a valid type for the arm back-end as follow up patches. Allowing half as argument through the IR is already a step to that direction. IMO this patch is already quite big and it excels in fixing the bugs it proposed. Repository:

[PATCH] D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz.

2020-05-27 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Hi @rsmith, are you still looking into this? cheers Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79378/new/ https://reviews.llvm.org/D79378 ___ cfe-commits mailing list

[PATCH] D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz.

2020-05-14 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM, as far @rjmccall 's concern about documentation is addressed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79378/new/

[PATCH] D75169: [ARM] Enforcing calling convention for half-precision FP arguments and returns for big-endian AArch32

2020-05-14 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. In D75169#1952159 , @pratlucas wrote: > > Why not just make half as an argument do the right thing for that case? > > That would be the ideal approach, but currently there's a limitation on the > backend's calling convention

[PATCH] D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz.

2020-05-11 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. From my point it does LGTM. Comment at: clang/lib/CodeGen/CGExprCXX.cpp:2042-2049 // Null check the pointer. llvm::BasicBlock *DeleteNotNull = createBasicBlock("delete.notnull"); llvm::BasicBlock *DeleteEnd = createBasicBlock("delete.end");

[PATCH] D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz.

2020-05-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. I believe we can avoid creating some blocks for latter removing them, no? Comment at: clang/lib/CodeGen/CGExprCXX.cpp:2042-2049 // Null check the pointer. llvm::BasicBlock *DeleteNotNull = createBasicBlock("delete.notnull"); llvm::BasicBlock

[PATCH] D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement

2020-04-09 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM, not forgetting to remove the exit comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77074/new/ https://reviews.llvm.org/D77074

[PATCH] D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement

2020-04-02 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:8486-8492 + return Builder.CreateConstrainedFPCall( + F, + {EmitScalarExpr(E->getArg(1)), EmitScalarExpr(E->getArg(2)), Ops[0]}); +} else { + Function *F =

[PATCH] D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement

2020-04-01 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:8486-8492 + return Builder.CreateConstrainedFPCall( + F, + {EmitScalarExpr(E->getArg(1)), EmitScalarExpr(E->getArg(2)), Ops[0]}); +} else { + Function *F =

[PATCH] D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement

2020-03-31 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/test/CodeGen/aarch64-neon-intrinsics-constrained.c:288 + +// XXX FIXME do we need to check for both w and x registers? +// COMMON-LABEL: test_vceq_f64 kpn wrote: > Anyone? I'm not an ARM expert. The is variants

[PATCH] D74766: [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrdmulhq_lane intrinsics

2020-03-19 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74766/new/ https://reviews.llvm.org/D74766

[PATCH] D74619: [ARM] Enabling range checks on Neon intrinsics' lane arguments

2020-03-18 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Hi, thanks for looking into this. The patch LGTM, but regarding the indentation, I don't know what would be the best practice here. We tend to like to preserve the line-git-history, but if we start ignoring the formater check, then it has no sense in they being

[PATCH] D73638: [AST] Move dependence computations into a separate file

2020-03-17 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/lib/AST/ComputeDependence.cpp:607 + auto D = toExprDependence(E->getType()->getDependence()); + for (auto *E : E->arguments()) +D |= E->getDependence() & ~ExprDependence::Type; I'm impressed this even

[PATCH] D74618: [ARM] Creating 'call_mangled' for Neon intrinsics definitions

2020-03-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM, after a nit inline. Comment at: clang/include/clang/Basic/arm_neon_incl.td:66 +//that has the variation and takes the given types, an error +//

[PATCH] D74766: [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrdmulhq_lane intrinsics

2020-03-09 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/test/CodeGen/arm-neon-range-checks.c:284-285 +void test_vqdmulhq_lane(int32x4_t a, int32x2_t b) { + vqdmulhq_lane_s32(a, b, -1); // expected-error {{argument value -1 is outside the valid range}} + vqdmulhq_lane_s32(a, b, 2);

[PATCH] D74619: [ARM] Enabling range checks on Neon intrinsics' lane arguments

2020-03-09 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/test/CodeGen/arm-neon-range-checks.c:7 +void test_vdot_lane(int32x2_t r, int8x8_t a, int8x8_t b) { + vdot_lane_s32(r, a, b, -1); // expected-error {{argument value -1 is outside the valid range}} + vdot_lane_s32(r, a, b, 2);

[PATCH] D74618: [ARM] Creating 'call_mangled' for Neon intrinsics definitions

2020-03-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/utils/TableGen/NeonEmitter.cpp:1890-1891 } +if (MangledName) + Good &= I.getMangledName(true) == MangledName; + Can we move this above the loop just before? Perhaps, if false, can we just continue

[PATCH] D74617: [ARM] Keeping sign information on bitcasts for Neon vdot_lane intrinsics

2020-03-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Is this missing a test? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D74617/new/ https://reviews.llvm.org/D74617 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D74616: [ARM] Setting missing isLaneQ attribute on Neon Intrisics definitions

2020-03-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM with a nit: we can save some space using sintax like this: let isLaneQ = 1 in def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<; or concatenating those that are just one after

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-02-11 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Hi @ostannard, thanks for your review. I updated the patch so it won't act when the computed volatile bit-field access will overlap a zero length bit-field, avoiding the conflict. We can update it accordingly to future versions of the AAPCS if required. Repository:

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-02-07 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 243197. dnsampaio added a comment. Added opt-out flag Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 Files: clang/include/clang/Basic/CodeGenOptions.def

[PATCH] D67399: [ARM] Follow AACPS for preserving number of loads/stores of volatile bit-fields

2020-02-07 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rG9d869180c4ad: [ARM] Follow AACPS for preserving number of loads/stores of volatile bit-fields (authored by dnsampaio). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D67399: [ARM] Follow AACPS for preserving number of loads/stores of volatile bit-fields

2020-02-07 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 243102. dnsampaio added a comment. Revordered some tests adding and definition of the "isAAPCS" function from patch D72932 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-02-06 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio planned changes to this revision. dnsampaio added a comment. Updated wrong patch here. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 ___

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-02-06 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 242823. dnsampaio added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. - Removed test - Added clear at the end of run as well, to clear waste - Moved clearing to a more sensible position Repository: rG LLVM

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-02-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-02-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Ping :-) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D67399: [ARM] Follow AACPS for preserving number of loads/stores of volatile bit-fields

2020-01-30 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 241486. dnsampaio added a comment. - Added flag to allow user to opt-in Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67399/new/ https://reviews.llvm.org/D67399 Files:

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-30 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 241477. dnsampaio added a comment. - Do not generate special volatile access if the record alignment is smaller than the bit-field declared type Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-30 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 241421. dnsampaio added a comment. Herald added a subscriber: jfb. - Moved computation of volatile accesses to the record layout builder Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. In D72932#1829716 , @ostannard wrote: > Why are you doing this in CodeGen, rather than adjusting the existing layout > code in CGRecordLowering? Doing it this way will result in > AdjustAAPCSBitfieldLValue being called for

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. In D72932#1829716 , @ostannard wrote: > Why are you doing this in CodeGen, rather than adjusting the existing layout > code in CGRecordLowering? Doing it this way will result in > AdjustAAPCSBitfieldLValue being called for

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-21 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio reopened this revision. dnsampaio added a comment. Sorry, submitted using ide by mistake. Already reverted it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72932/new/ https://reviews.llvm.org/D72932

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-21 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was not accepted when it landed; it landed in state "Needs Review". This revision was automatically updated to reflect the committed changes. Closed by commit rG6a24339a4524: [ARM] Follow AACPS standard for volatile bit-fields access width (authored by dnsampaio). Repository: rG

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-20 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. In D72932#1829716 , @ostannard wrote: > Why are you doing this in CodeGen, rather than adjusting the existing layout > code in CGRecordLowering? Doing it this way will result in > AdjustAAPCSBitfieldLValue being called for

[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

2020-01-17 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added reviewers: rsmith, rjmccall. Herald added subscribers: cfe-commits, kristof.beyls. Herald added a project: clang. This patch resumes the work of D16586 . According to the AAPCS, volatile bit-fields should be

[PATCH] D70183: Detect source location overflow due includes

2019-11-29 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Just wondering, I don't fully understand why is that important from the point I do a `return FileID();`. The critical error has already been inserted to the error list. clang shall either die due an assert in debug, or with a nice message in release. Unless clang is

[PATCH] D70183: Detect source location overflow due includes

2019-11-19 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Git diff 979ae80af7ec49624b932954d22cb91900f17121 did not send a test as well. Feel free to send me a reasonable sized reproducer, the one I have is about 36MB. Don't think it will be that well received. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D70183: Detect source location overflow due includes

2019-11-19 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked an inline comment as done. dnsampaio added inline comments. Comment at: clang/lib/Basic/SourceManager.cpp:587 +Diag.Report(IncludePos, diag::err_include_too_large); +exit(1); + } miyuki wrote: > dnsampaio wrote: > > miyuki wrote: > > >

[PATCH] D70183: Detect source location overflow due includes

2019-11-19 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked 2 inline comments as done. dnsampaio added a comment. Yes. It does return a non-valid FileID, and in builds without assert you get the expected error message. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70183/new/

[PATCH] D70183: Detect source location overflow due includes

2019-11-19 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked an inline comment as done. dnsampaio added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70183/new/ https://reviews.llvm.org/D70183 ___ cfe-commits mailing list

[PATCH] D70183: Detect source location overflow due includes

2019-11-14 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked an inline comment as done. dnsampaio added inline comments. Comment at: clang/lib/Basic/SourceManager.cpp:587 +Diag.Report(IncludePos, diag::err_include_too_large); +exit(1); + } miyuki wrote: > dnsampaio wrote: > > miyuki wrote: > > >

[PATCH] D70183: Detect source location overflow due includes

2019-11-14 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 229254. dnsampaio marked an inline comment as done. dnsampaio added a comment. - Return an invalid FileID instead of exiting. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70183/new/

[PATCH] D70183: Detect source location overflow due includes

2019-11-13 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: clang/lib/Basic/SourceManager.cpp:587 +Diag.Report(IncludePos, diag::err_include_too_large); +exit(1); + } miyuki wrote: > dnsampaio wrote: > > For debug builds, I could not find any other way to not reach an

[PATCH] D70183: Detect source location overflow due includes

2019-11-13 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 229113. dnsampaio marked 2 inline comments as done. dnsampaio added a comment. - Add ", DefaultFatal"; Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70183/new/ https://reviews.llvm.org/D70183 Files:

[PATCH] D70183: Detect source location overflow due includes

2019-11-13 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added reviewers: rsmith, thakis, miyuki. Herald added a project: clang. Herald added a subscriber: cfe-commits. dnsampaio marked an inline comment as done. dnsampaio added inline comments. Comment at:

[PATCH] D70183: Detect source location overflow due includes

2019-11-13 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked an inline comment as done. dnsampaio added inline comments. Comment at: clang/lib/Basic/SourceManager.cpp:587 +Diag.Report(IncludePos, diag::err_include_too_large); +exit(1); + } For debug builds, I could not find any other way to not

[PATCH] D67608: [ARM] Preserve fpu behaviour for '-crypto'

2019-10-14 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rG2cb43b45713d: [ARM] Preserve fpu behaviour for -crypto (authored by dnsampaio). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67608/new/

[PATCH] D67608: [ARM] Preserve fpu behaviour for '-crypto'

2019-10-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 224323. dnsampaio added a comment. Attending review request: - Fixed to only add '-crypto' when not passing -fno-integrated-as - Fixed test to use arm-none-none-eabi - Changed comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D67608: [ARM] Preserve fpu behaviour for '-crypto'

2019-09-16 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added reviewers: peter.smith, labrinea. Herald added subscribers: cfe-commits, dmgreen, kristof.beyls. Herald added a project: clang. This patch restores the behaviour that -fpu overwrites the architecture obtained from -march or -mcpu flags, not

[PATCH] D67399: [ARM] Follow AACPS standard for volatile bitfields

2019-09-13 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Indeed our main concern is regarding the access widths of loads. As mentioned by @rjmccall, most volatile bitfields are used to perform memory mapped I/O, and some hardware only support them with a specific access width. The spurious load I am more than glad to leave

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-09-11 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL371597: [ARM] Take into account -mcpu and -mfpu options while handling crypto feature (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits.

[PATCH] D67399: [ARM] Follow AACPS standard for volatile bitfields

2019-09-11 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked 4 inline comments as done. dnsampaio added a comment. Hi @jfb. In a example such as: struct { int a : 1; int b : 16; } S; extern int expensive_computaion(int v); void foo(volatile S* s){ s->b = expensive_computation(s->b); } There is no guarantee that `s->a` is not

[PATCH] D67399: [ARM] Follow AACPS standard for volatile bitfields

2019-09-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. @ostannard might prove me wrong, but according to the AACPS: When a volatile bit-field is written, and its container does not overlap with any non-bit-field member, its container must be read exactly once and written exactly once using the access width

[PATCH] D67399: [ARM] Follow AACPS standard for volatile bitfields

2019-09-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. This patch could hack clang to generate an extra load. However, my knowledge in the clang code base is not extensive. How could we ensure that the width of loads and stores are the size of the container, and that they don't overlap non-bitfields? Repository: rG

[PATCH] D67399: [ARM] Follow AACPS standard for volatile bitfields

2019-09-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added reviewers: lebedev.ri, ostannard. Herald added subscribers: cfe-commits, jfb, kristof.beyls. Herald added a project: clang. Bug 43264 This is a first draft to understand what has to be done to fix volatale bitfield access, as to conform to the

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-09-03 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Will commit for you as requested soon. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66018/new/ https://reviews.llvm.org/D66018

[PATCH] D66588: [ARM NEON] Avoid duplicated decarations

2019-09-03 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL370716: [ARM NEON] Avoid duplicated decarations (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit:

[PATCH] D66588: [ARM NEON] Avoid duplicated decarations

2019-09-03 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 218412. dnsampaio added a comment. - Fix comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66588/new/ https://reviews.llvm.org/D66588 Files: clang/utils/TableGen/NeonEmitter.cpp Index:

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-09-02 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Hi, I do agree that giving the user a warning that the argument is ignored is the best solution. If you wouldn't mind adding it to this patch, that would be great. Thanks. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66018/new/

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-08-30 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio requested changes to this revision. dnsampaio added a comment. This revision now requires changes to proceed. `clang -### -target arm-arm-none-eabit -march=armv8-m.main+crypto` did not show +sha2 or +aes. After the patch it does. I believe that is not expected, as in ARM.td `crypto` is

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-08-29 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio accepted this revision. dnsampaio added a comment. This revision is now accepted and ready to land. LGTM. One optional nit as it is not related with this patch anymore. Comment at: lib/Driver/ToolChains/Arch/ARM.cpp:659 llvm::ARM::ArchKind ArchKind; - if (CPU ==

[PATCH] D66588: [ARM NEON] Avoid duplicated decarations

2019-08-28 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 217594. dnsampaio added a comment. Fix / Update / Rebase - Avoid appending __noswap_ to intrinsics that are BigEndianSafe - Moved to monorepo Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66588/new/

[PATCH] D66588: [ARM NEON] Avoid duplicated decarations

2019-08-27 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio planned changes to this revision. dnsampaio added a comment. Breaks the header. Needs to avoid generating calls to functions with predicated __noswap when it is BigEndianSafe. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66588/new/

[PATCH] D66588: [ARM NEON] Avoid duplicated decarations

2019-08-23 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 216801. dnsampaio added a comment. - Consider BigEndianSafe intrinsics that all inputs and outputs are scalar or single element vectors Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66588/new/

[PATCH] D66588: [ARM NEON] Avoid duplicated decarations

2019-08-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added reviewers: t.p.northover, ostannard. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. The declaration of arm neon intrinsics that are "big endian safe" print the same code for big and small endian

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-08-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. Hi @krisb, thanks for looking into this, and sorry for the delay, was out for a week. Comment at: lib/Driver/ToolChains/Arch/ARM.cpp:486-490 + if (ArchKind == llvm::ARM::ArchKind::ARMV8A || + ArchKind == llvm::ARM::ArchKind::ARMV8_1A || +

[PATCH] D66018: [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature

2019-08-14 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added inline comments. Comment at: lib/Driver/ToolChains/Arch/ARM.cpp:482-486 + llvm::ARM::ArchKind ArchKind = + !ArchName.empty() + ? llvm::ARM::parseArch(arm::getARMArch(ArchName, Triple)) + : llvm::ARM::parseCPUArch( +

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-08-08 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL368288: [ARM] Set default alignment to 64bits (authored by dnsampaio, committed by ). Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-08-06 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. I have tested this in our MacOS and linux environments. @thakis @thegameg @phosek, would it be possible for you to check if this works for you? Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/ https://reviews.llvm.org/D65000

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-08-06 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 213540. dnsampaio added a comment. Fix test Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/ https://reviews.llvm.org/D65000 Files: lib/Basic/Targets/ARM.cpp test/CodeGenCXX/ARM/exception-alignment.cpp

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-08-06 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio reopened this revision. dnsampaio added a comment. This revision is now accepted and ready to land. Hi, first thanks for those that looked into this and sorry for the delay. We have investigated the errors and seems that the test was, first in the wrong folder, inside CodeGen where it

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-07-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked an inline comment as done. dnsampaio added a comment. True. Thx again. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/ https://reviews.llvm.org/D65000 ___ cfe-commits mailing list

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-07-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 211132. dnsampaio added a comment. - Joined assignments for default alignments and neon_vector alignment - Added missing align 8 test Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/ https://reviews.llvm.org/D65000

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-07-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 211103. dnsampaio added a comment. - Joined assignments for default alignments and neon_vector alignment Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/ https://reviews.llvm.org/D65000 Files:

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-07-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio marked 2 inline comments as done. dnsampaio added a comment. Set android-abi default to 128. Added tests for android and not-android. Comment at: lib/Basic/Targets/ARM.cpp:311 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) if (IsAAPCS

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-07-22 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 211034. dnsampaio added a comment. - Set androideabi alignment to 128 bits Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65000/new/ https://reviews.llvm.org/D65000 Files: lib/Basic/Targets/ARM.cpp

[PATCH] D65000: [ARM] Set default alignment to 64bits

2019-07-19 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added reviewers: ostannard, dmgreen. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. The maximum alignment used by ARM arch is 64bits, not 128. This could cause overaligned memory access for 128 bit neon

[PATCH] D64211: [AArch64] Fix vector vuqadd intrinsics operands

2019-07-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL365609: [AArch64] Fix vector vuqadd intrinsics operands (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Repository: rL LLVM CHANGES SINCE

[PATCH] D64210: [NFC][AArch64] Fix vector vsqadd intrinsics operands

2019-07-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL365608: [NFC][AArch64] Fix vector vsqadd intrinsics operands (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Repository: rL LLVM CHANGES

[PATCH] D64243: [NFC][AArch64] Fix vector vqtb[lx][1-4]_s8 operand

2019-07-10 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL365598: [NFC][AArch64] Fix vector vqtb[lx][1-4]_s8 operand (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Repository: rL LLVM CHANGES

[PATCH] D64242: [AArch64] Fix scalar vuqadd intrinsics operands

2019-07-08 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL365300: [AArch64] Fix scalar vuqadd intrinsics operands (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit:

[PATCH] D64239: [AArch64] Fix vsqadd scalar intrinsics operands

2019-07-08 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL365298: [AArch64] Fix vsqadd scalar intrinsics operands (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit:

[PATCH] D64243: [NFC][AArch64] Fix vector vqtb[lx][1-4]_s8 operand

2019-07-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added a reviewer: LukeCheeseman. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. Change the vqtb[lx][1-4]_s8 instrinsics to have the last argument as vector of unsigned valuse, not signed, accordingly to

[PATCH] D64242: [AArch64] Fix scalar vuqadd intrinsics operands

2019-07-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 208144. dnsampaio added a comment. - Fix previously existing tests Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64242/new/ https://reviews.llvm.org/D64242 Files: include/clang/Basic/arm_neon.td

[PATCH] D64242: [AArch64] Fix scalar vuqadd intrinsics operands

2019-07-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added a reviewer: LukeCheeseman. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. Change the vuqadd scalar instrinsics to have the second argument as unsigned values, not signed, accordingly to

[PATCH] D64239: [AArch64] Fix vsqadd scalar intrinsics operands

2019-07-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added a reviewer: LukeCheeseman. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. Change the vsqadd scalar instrinsics to have the second argument as signed values, not unsigned, accordingly to

[PATCH] D64211: [ARM] Fix vector vuqadd intrinsics operands

2019-07-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio updated this revision to Diff 208127. dnsampaio added a comment. - Added tests Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64211/new/ https://reviews.llvm.org/D64211 Files: include/clang/Basic/arm_neon.td test/CodeGen/aarch64-neon-intrinsics.c

[PATCH] D64210: [NFC][ARM] Fix vector vsqadd intrinsics operands

2019-07-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio added a comment. In D64210#1570515 , @LukeCheeseman wrote: > Are there some changes/addition to tests attached to this? Hi, I can see no difference in the CodeGen test in tools/clang/test/CodeGen/aarch64-neon-intrinsics.c, which already

[PATCH] D64211: [ARM] Fix vector vuqadd intrinsics operands

2019-07-04 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added a reviewer: LukeCheeseman. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. Change the vuqadd vector instrinsics to have the second argument as unsigned values, not signed, accordingly to

[PATCH] D64210: [ARM] Fix vector vsqadd intrinsics operands

2019-07-04 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. dnsampaio added a reviewer: LukeCheeseman. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. Change the vsqadd vector instrinsics to have the second argument as signed values, not unsigned, accordingly to

[PATCH] D60828: [ARM] Fix armv8 features tree and add fp16fml

2019-06-05 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio abandoned this revision. dnsampaio added a comment. Fixed. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60828/new/ https://reviews.llvm.org/D60828 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D61668: [ARM] Fix the extensions implied by a cpu name

2019-05-09 Thread Diogo N. Sampaio via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL360324: [ARM] Fix the extensions implied by a cpu name (authored by dnsampaio, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Repository: rL LLVM CHANGES SINCE

[PATCH] D61668: [ARM] Fix the extensions implied by a cpu name

2019-05-08 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio created this revision. Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. Herald added a project: clang. dnsampaio added reviewers: keith.walker.arm, DavidSpickett, carwil. When using `clang -mcpu=CPUNAME+FEATURELIST`, the intrinsic features defined by CPUNAME are not

[PATCH] D60828: [ARM] Fix armv8 features tree and add fp16fml

2019-04-18 Thread Diogo N. Sampaio via Phabricator via cfe-commits
dnsampaio planned changes to this revision. dnsampaio added a comment. Waiting for the outcome of D60691 . Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60828/new/ https://reviews.llvm.org/D60828

  1   2   >