[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1f057e365f1f: [X86] AMD Zen 4 Initial enablement (authored by GGanesh). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

GGanesh updated this revision to Diff 483141. GGanesh added a comment. Fixed the tests tools/llvm-mca/X86/cpus.s tools/llvm-mca/X86/read-after-ld-1.s tools/llvm-mca/X86/register-file-statistics.s tools/llvm-mca/X86/scheduler-queue-usage.s Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

GGanesh added a comment. In D139073#3997418 , @RKSimon wrote: > Thanks @GGanesh - LGTM with one minor - the orphan ZNVER4 checks from the > llvm-mca tests need removing Thank you! I left them intentionally as this is a stop-gap patch. Agreed! Will

[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

GGanesh updated this revision to Diff 483092. GGanesh added a comment. Update to use 'no' processor model. Fixed the below tests tools/llvm-mca/X86/cpus.s tools/llvm-mca/X86/read-after-ld-1.s tools/llvm-mca/X86/register-file-statistics.s tools/llvm-mca/X86/scheduler-queue-usage.s Addressed

[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

GGanesh added a comment. In D139073#3995741 , @RKSimon wrote: > @GGanesh reverse-ping @RKSimon Thanks a lot! We were trying to get the libpfm patch posted and subsequently enabling the zen4 scheduler model. Probably a week or two from there. The intel

[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

GGanesh created this revision. GGanesh added reviewers: RKSimon, craig.topper, andreadb. Herald added subscribers: Enna1, StephenFan, pengfei, gbedwell, javed.absar, hiraditya. Herald added a project: All. GGanesh requested review of this revision. Herald added projects: clang, Sanitizers, LLVM.

[PATCH] D92812: [X86] Update tests for znver3

This revision was automatically updated to reflect the committed changes. Closed by commit rGdbfc1ac4d86c: [X86] Update tests for znver3 (authored by GGanesh). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92812/new/ https://reviews.llvm.org/D92812

[PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement

GGanesh updated this revision to Diff 314703. GGanesh edited the summary of this revision. GGanesh added a comment. Updaing the patch so that the simplified patch adds only few missing znver3 tests. The subsequent patches will comprehensively enable other znver3 features. Repository: rG LLVM

[PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement

GGanesh added a comment. In D92812#2439324 , @RKSimon wrote: > it looks like a very bad merge imo. Yep, Thank you! I will post smaller incremental patches. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement

GGanesh created this revision. GGanesh added reviewers: RKSimon, craig.topper, lebedev.ri, courbet. GGanesh added projects: LLVM, clang. Herald added subscribers: mstojanovic, pengfei, jfb, gbedwell, hiraditya. Herald added a reviewer: andreadb. GGanesh requested review of this revision. Herald

[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch

GGanesh updated this revision to Diff 187389. Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 Files: include/llvm/Support/X86TargetParser.def lib/Support/Host.cpp lib/Target/X86/X86.td test/CodeGen/X86/cpus-amd.ll

[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch

GGanesh updated this revision to Diff 187386. Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 Files: include/llvm/Support/X86TargetParser.def lib/Support/Host.cpp lib/Target/X86/X86.td test/CodeGen/X86/cpus-amd.ll

[PATCH] D58344: Enablement for AMD znver2 architecture - skeleton

GGanesh updated this revision to Diff 187387. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58344/new/ https://reviews.llvm.org/D58344 Files: include/clang/Basic/X86Target.def lib/Basic/Targets/X86.cpp test/CodeGen/target-builtin-noerror.c

[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch

GGanesh updated this revision to Diff 187340. GGanesh added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Addressed the comments from Craig Topper Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/

[PATCH] D58344: Enablement for AMD znver2 architecture - skeleton

GGanesh created this revision. GGanesh added reviewers: RKSimon, craig.topper. GGanesh created this object with visibility "All Users". GGanesh added a project: clang. Herald added a subscriber: cfe-commits. This patch enables the following 1. AMD family 17h "znver2" tune flag (-march, -mcpu).

[PATCH] D29386: Clzero flag addition and inclusion under znver1

GGanesh added a comment. Thank you @craig.topper. Just want to check if the patch can be commited to 4.0 release branch as well. I understand that the trunk is in blocker bug-fix stage but just want to get it confirmed. Repository: rL LLVM https://reviews.llvm.org/D29386

[PATCH] D29386: Clzero flag addition and inclusion under znver1

GGanesh updated this revision to Diff 87437. GGanesh added a comment. Updated the builtins test for "__builtin_ia32_clzero" Repository: rL LLVM https://reviews.llvm.org/D29386 Files: include/clang/Basic/BuiltinsX86.def include/clang/Driver/Options.td lib/Basic/Targets.cpp

[PATCH] D29386: Clzero flag addition and inclusion under znver1

GGanesh updated this revision to Diff 87386. GGanesh added a comment. Updated for review comments. Repository: rL LLVM https://reviews.llvm.org/D29386 Files: include/clang/Basic/BuiltinsX86.def include/clang/Driver/Options.td lib/Basic/Targets.cpp lib/Headers/CMakeLists.txt

[PATCH] D28018: AMD family 17h (znver1) enablement

GGanesh added a comment. If Okay, can you please commit these on my behalf. I don't have write access. https://reviews.llvm.org/D28018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D28018: AMD family 17h (znver1) enablement

GGanesh added a comment. Yes. True I mentioned that for the grouping or the order of the features enabled. These initFeatureMap are done based on the intrinsics and the CodeGen part. https://reviews.llvm.org/D28018 ___ cfe-commits mailing list

[PATCH] D28018: AMD family 17h (znver1) enablement

GGanesh updated this revision to Diff 83626. GGanesh added a comment. Fallback to CK_BTVER1 is ok but not to CK_BTVER2. This is not possible because of the partial YMM writes. They have different behavior for znver1 with AVX and their legacy SIMD counterparts. So, as of now leaving them to

[PATCH] D28018: AMD family 17h (znver1) enablement

GGanesh added inline comments. Comment at: lib/Basic/Targets.cpp:3189 break; + case CK_ZNVER1: +setFeatureEnabledImpl(Features, "adx", true); RKSimon wrote: > Same as what I asked on D28017 - is there an accepted order that we should be > using here?

[PATCH] D28018: AMD family 17h (znver1) enablement

GGanesh removed rL LLVM as the repository for this revision. GGanesh updated this revision to Diff 83566. GGanesh added a comment. The clzero builtins and feature addition will be handled separately in another patch. SSE4a and movbe are added to the ISA list. https://reviews.llvm.org/D28018