[PATCH] D78129: Add Marvell ThunderX3T110 support

[Joel Jones via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG382d3a85e2a9: [AARch64] Add Marvell ThunderX3T110 support 
(authored by wxz2020, committed by joelkevinjones).

Changed prior to commit:
  https://reviews.llvm.org/D78129?vs=263582=263896#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129

Files:
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -943,6 +943,13 @@
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
   EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RAND |
+  AArch64::AEK_RCPC,
+  "8.3-A"));
+  EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
   AArch64::AEK_FP | AArch64::AEK_PROFILE,
@@ -983,7 +990,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 38;
+static constexpr unsigned NumAArch64CPUArchs = 39;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown 

[PATCH] D78129: Add Marvell ThunderX3T110 support

[Joel Jones via Phabricator via cfe-commits]

joelkevinjones added a comment.

I don't think it makes sense to combine two unrelated things SVE and PA support 
into a combined thing. Since we already have UnsupportedFeatures in every 
sub-target .td file, I think it would be better to instead have:

  def PAUnsupported : AArch64Unsupported {
let F = [HasPA];
  }

and modify each .td file to have

  list UnsupportedFeatures = !listconcat(SVEUnsupported.F, 
PAUnsupported.F);


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[PATCH] D78129: Add Marvell ThunderX3T110 support

[Joel Jones via Phabricator via cfe-commits]

joelkevinjones added a comment.

> It is okay'ish to set `CompleteModel = 0` if you're not interested in 
> describing all instructions. The other way is of course to add the missing 
> instruction to the model.

We are trying to describe all instructions. The issue Wei is having is that the 
pointer auth instructions are being called out in the error message, but their 
timing information is defined—see the very end of AArch64SchedThunderX3T110.td 
for AUTDZA.

> But first things first. @chill commented earlier about predicates. I also 
> don't think you need to add `HasV8_3a` for the reason Momchill described, and 
> there is still one left AArch64InstrInfo.td.
> 
> And while I am still looking into this, let me ask the question what I am 
> wondering: why do you need to change the other scheduling models? These 
> instructions are always supported, as a NOP, or otherwise.

The changes to UnsupportedFeatures that was in every model has been taken out. 
I'm not sure why UnsupportedFeatures exists at all, but it isn't just AArch64 
that has this.

Should the latest version be put up even if it fails on table-gen?  That would 
make things easier to review.


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[PATCH] D78129: Add Marvell ThunderX3T110 support

[Joel Jones via Phabricator via cfe-commits]

joelkevinjones added a comment.

In email Wei asked for help about he following error message:

  error message from tblgen
  Included from 
/home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64.td:439:
  
/home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.td:961:5:
 error: 'CycloneModel' lacks information for 'AUTDZA'
  
  def DZA  : SignAuthZero;
  ^
  In the end:
  Incomplete schedule models found.
  
  · Consider setting 'CompleteModel = 0' while developing new models.
  · Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.
  · Instructions should usually have Sched<[...]> as a superclass, you 
may temporarily use an empty list.
  · Instructions related to unsupported features can be excluded with 
list UnsupportedFeatures = [HasA,..,HasY]; in the processor model.
  error: Incomplete schedule model

And the comment from the person on the email was to define the instruction. The 
instruction is defined, as evidenced when table gen is run to produce the 
record-list. The error message can be suppressed by defining CompleteModele = 
0, but that isn't correct, as there are models for those instructions.

However, I now note that at least In the output that Wei captured, it isn't 
complaining about the ThunderX3T110 model, but about Cyclone.


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