[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Thanks for the update @asb. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142327/new/ https://reviews.llvm.org/D142327 ___ cfe-c

[PATCH] D156438: [Docs] Fix code-blocks missing colon

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG31747668: [Docs] Fix code-blocks missing a colon and a newline (authored by rogfer01). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D156438: [Docs] Fix code-blocks missing colon

rogfer01 created this revision. Herald added a reviewer: aaron.ballman. Herald added subscribers: PiotrZSL, carlosgalvezp. Herald added a reviewer: njames93. Herald added a project: All. rogfer01 requested review of this revision. Herald added projects: clang, LLVM, clang-tools-extra. Herald added

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

rogfer01 added a comment. I didn't have libcxx handy but @SixWeining testcase also fails with libstdcxx so I expanded what C++ does and removed the templates. With the new patch this does not fail anymore. typedef decltype((int *)2 - (int *)1) my_ptrdiff_t; struct my_lambda { bool op

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

rogfer01 added a comment. I didn't have libcxx handy but @SixWeining testcase also failed with libstdcxx so I made a slightly smaller standalone testcase based on what libstdcxx does and I manually replaced all the template stuff. typedef decltype((int *)2 - (int *)1) my_ptrdiff_t; struc

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

rogfer01 added inline comments. Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:178 return false; -if (isEmptyRecord(getContext(), Ty, true)) +if (isEmptyRecord(getContext(), Ty, true, true)) return true; I've observed (based on manually add

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGfa45f81ff7ea: [clang][Serialization][RISCV] Increase the number of reserved predefined type… (authored by rogfer01). Repository: rG LLVM Github Mo

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

rogfer01 updated this revision to Diff 532546. rogfer01 added a comment. ChangeLog: - Update clang tests that now, on RISC-V only, observe a larger precompiled module file CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153111/new/ https://reviews.llvm.org/D153111 Files: clang/includ

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

rogfer01 added a comment. Thanks @eopXD. Not sure why you didn't observe the failure. I understand your build has `-DLLVM_ENABLE_ASSERTIONS=ON`. I investigated a bit the libcxx errors flagged by the precommit CI. I can get similar (but not exactly the same errors) if the build before this chang

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

rogfer01 updated this revision to Diff 532061. rogfer01 added a comment. ChangeLog: - Add a sentinel and a `static_assert` CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153111/new/ https://reviews.llvm.org/D153111 Files: clang/include/clang/Serialization/ASTBitCodes.h clang/lib/Se

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

rogfer01 added a comment. Let me check if I can add a `static_assert` to get a compile-time failure. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153111/new/ https://reviews.llvm.org/D153111 ___ cfe-com

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

rogfer01 added a comment. It looks like we need to increase `NUM_PREDEF_TYPE_IDS`. Let's continue the discussion on D153111 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152070/new/ https://reviews.llvm.org/D1520

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

rogfer01 created this revision. rogfer01 added reviewers: eopXD, Eugene.Zelenko, craig.topper. Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, shiva0217, kito-cheng, simoncook, arichardson. Herald added a project: All. rogfe

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

rogfer01 added a comment. >> Can you check if clang crashes for you? > > I am seeing messages related to builtin type, but they do not seem related to > RVV builtin types. > > $ touch t.c > $ clang -cc1 -triple riscv64 -w -emit-pch -o test.pch t.c > $ clang -cc1 -triple riscv64 -w -x c -inc

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

rogfer01 added a comment. In D152070#4425358 , @eopXD wrote: > In D152070#4425318 , @rogfer01 > wrote: > >> In D152070#4421004 , >> @DavidSpickett wrote: >> >>> FYI afte

[PATCH] D152137: [4/6][Clang][RISCV] Replace strided segment store with tuple type interfaces

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Herald added a subscriber: wangpc. LGTM. Thanks @eopXD Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152137/new/ https://reviews.llvm.org/D1

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

rogfer01 added a comment. Herald added a subscriber: wangpc. In D152070#4421004 , @DavidSpickett wrote: > FYI after this change: > > Building CXX object > tools/lldb/sou...luginTypeSystemClang.dir/TypeSystemClang.cpp.o > > /home/david.spickett/llvm

[PATCH] D152139: [6/6][Clang][RISCV] Replace indexed segment store with tuple type interfaces

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Herald added a subscriber: wangpc. LGTM. Thanks @eopXD Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152139/new/ https://reviews.llvm.org/D1

[PATCH] D152138: [5/6][Clang][RISCV] Replace indexed segment load with tuple type interfaces

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Herald added a subscriber: wangpc. LGTM. Thanks @eopXD Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152138/new/ https://reviews.llvm.org/D1

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

rogfer01 added a comment. Hi @abel-bernabeu, I did a quick experiment replacing all the calls to `getLexer().Lex()` with `getParser().Lex()` and now your testcase is accepted and looks like this in the output f2: addisp, sp, -32 sd ra, 24(sp) sd s0, 16(sp

[PATCH] D152135: [2/6][Clang][RISCV] Replace unit-stride segment store with tuple type interfaces

rogfer01 added a comment. Just to confirm, though: seeing those `COERCE`, I assume the underlying calling convention (which unfortunately it not 100% transparent to `clang` at this point) is the same as passing in order the components of the tuple, right? (Apologies if this was already discusse

[PATCH] D152136: [3/6][Clang][RISCV] Replace strided segment load with tuple type interfaces

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @eopXD Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152136/new/ https://reviews.llvm.org/D152136

[PATCH] D152135: [2/6][Clang][RISCV] Replace unit-stride segment store with tuple type interfaces

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @eopXD Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152135/new/ https://reviews.llvm.org/D152135

[PATCH] D152134: [1/6][Clang][RISCV] Replace unit-stride (fault-first) segment load with tuple type interfaces

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @eopXD Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152134/new/ https://reviews.llvm.org/D152134

[PATCH] D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC)

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. This is a huge number of test changes so I have checked a subset of files but the changes seems reasonable, as I imagine they're generated mechanically. We seem to be internally consistent

[PATCH] D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC)

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126741/new/ https://reviews.llvm.org/D126741 _

[PATCH] D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC)

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen ! (I was a bit confused by the refactoring of `computeBuiltinTypes` but it is definitely better this way) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST A

[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124186/new/ https://reviews.llvm.org/D124186 _

[PATCH] D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Thanks for the cleanup @khchen ! LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120870/new/ https://reviews.llvm.org/D120870

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120228/new/ https://reviews.llvm.org/D120228 _

[PATCH] D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120227/new/ https://reviews.llvm.org/D120227 _

[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119686/new/ https://reviews.llvm.org/D119686 __

[PATCH] D119688: [RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. LGTM. Thanks @khchen ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119688/new/ https://reviews.llvm.org/D119688 _

[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

rogfer01 added inline comments. Comment at: clang/test/Driver/riscv-default-features.c:4 +// RV32: "target-features"="+a,+c,+m,+relax,-save-restore" +// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore" + I think we may be missing are missing a `RUN`

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

rogfer01 accepted this revision. rogfer01 added a comment. This revision is now accepted and ready to land. Looks reasonable to me. Thans @khchen! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 _

[PATCH] D112398: [RISCV] Add ABI testing for Float16.

rogfer01 added a comment. I'm curious about how we handle `_Float16` here. My understanding from the psabi and the Zfh draft

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

rogfer01 added a comment. Looks good to me too. Thanks a lot @craig.topper ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 ___ cfe-commits mailing list cfe-co

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

rogfer01 added a comment. In D111617#3060377 , @HsiangKai wrote: > Although it reduces the header size, this patch will increase the binary size > of clang. Options we can consider to mitigate this: - See if we can be more economical reprenting the tab

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

rogfer01 added inline comments. Comment at: clang/lib/Sema/SemaLookup.cpp:923 + + const RVVIntrinsicInfo *Intrinsic = std::find_if( + std::begin(RVVIntrinsicInfos), std::end(RVVIntrinsicInfos), Not for this patch: I think this table may be a bit large so al

[PATCH] D107666: [OpenMP] Fix accidental reuse of VLA size

This revision was automatically updated to reflect the committed changes. Closed by commit rGbfb77364d0be: [OpenMP] Fix accidental reuse of VLA size (authored by rogfer01). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107666/new/ https://reviews.ll

[PATCH] D107666: [OpenMP] Fix accidental reuse of VLA size

rogfer01 added a comment. Thanks for the prompt review @ABataev! I'll push this shortly. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107666/new/ https://reviews.llvm.org/D107666 ___ cfe-commits mailing

[PATCH] D107666: [OpenMP] Fix accidental reuse of VLA size

rogfer01 created this revision. rogfer01 added a reviewer: ABataev. Herald added subscribers: guansong, yaxunl. rogfer01 requested review of this revision. Herald added a reviewer: jdoerfert. Herald added subscribers: cfe-commits, sstefan1. Herald added a project: clang. We were using an `OpaqueVa

[PATCH] D106044: [RISCV] Update to vcpop.m, vlm.v and vsm.v according to v1.0-rc1.

rogfer01 added a comment. I'm confused because the PDF at https://github.com/riscv/riscv-v-spec/releases/tag/v1.0-rc1 doesn't seem to describe `vcpop.m`. I can see this has changed in the ToT https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#changes-from-v1-0-rc1 Perhaps this wi

[PATCH] D103527: [Clang][RISCV] Implement vlseg and vlsegff.

rogfer01 added a comment. Do you think you can split `vlseg` and `vlseg_ff` tests in two different files? So we (potentially) reduce the test latency by half in multicore systems. Other than this, LGTM. We're a bit split in https://github.com/riscv/rvv-intrinsic-doc/issues/95 However there are

[PATCH] D100821: [RISCV] Implement the vmmv.m/vmnot.m builtin.

rogfer01 added a comment. In D100821#2710998 , @HsiangKai wrote: > Rebase. Thanks, I had missed that and my comment above was wrong. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100821/new/ https://revie

[PATCH] D100821: [RISCV] Implement the vmmv.m/vmnot.m builtin.

rogfer01 added a comment. I can reproduce the crash above in my computer, so something is definitely off. Looks like we emit this case RISCV::BI__builtin_rvv_vmmv_m_b8: case RISCV::BI__builtin_rvv_vmmv_m_b4: case RISCV::BI__builtin_rvv_vmmv_m_b2:

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

rogfer01 added a comment. I've left a PoC of my approach here https://reviews.llvm.org/D100529 in case we can use that Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99741/new/ https://reviews.llvm.org/D99741 __

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

rogfer01 added a comment. In D99741#2690156 , @craig.topper wrote: > In D99741#2690124 , @thakis wrote: > >> One of the ten commits that landed here >> (https://github.com/llvm/llvm-project/compare/a3bfddbb6a27...

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

rogfer01 added inline comments. Comment at: clang/lib/AST/ASTContext.cpp:1486 + BuiltinType::Kind K, unsigned NF) { + auto TypeIter = llvm::find_if(Types, [&K](Type *Ty) { + if (Ty->isBuiltinType()) { -

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

rogfer01 added a comment. I was under the impression we didn't want to use class-member access syntax for vector tuples (see https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) so we don't need a record type, do we? Perhaps it is possible to model them like opaque ent

[PATCH] D99593: [Clang][RISCV] Implement vlseg builtins.

rogfer01 added a comment. This is just a suggestion, feel free to ignore: a sequence of `T`s was easy to parse for the prototype but may be want to consider something like `T3v` rather than `TTTv`. I think it would simplify the `TString` tblgen class and those `std::string(N, 'T')`.

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

rogfer01 added a comment. Overall LGTM. Thanks @khchen! Comment at: clang/include/clang/Basic/riscv_vector.td:175 + // builtin to C/C++. It is parameter of the unmasked version without VL + // operand. + list PermuteOperands = []; Not sure if we want to clar

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

rogfer01 added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:796 } return ""; } Minor nit that we missed in the patch of 0.8: can you replace this return with ```lang=cpp llvm_unreachable(); ``` as recommended in t

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

rogfer01 added a comment. The patch as it stands now LGTM and I think it can be committed. Is there any objection remaining? Any further comments @simoncook @asb? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

rogfer01 added a comment. @HsiangKai: just to confirm and to avoid confusion for other reviewers. > Assemble/disassemble RISC-V V extension instructions according to version > 0.8-draft-20191004 in https://github.com/riscv/riscv-v-spec/. Is the patch against the spec published in https://githu

[PATCH] D70799: [OpenMP] Lower taskyield using OpenMP IR Builder

rogfer01 updated this revision to Diff 244611. rogfer01 added a comment. ChangeLog: - Rebase CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70799/new/ https://reviews.llvm.org/D70799 Files: clang/lib/CodeGen/CGOpenMPRuntime.cpp clang/test/OpenMP/taskyield_codegen.cpp llvm/include

[PATCH] D70799: [OpenMP] Lower taskyield using OpenMP IR Builder

This revision was automatically updated to reflect the committed changes. Closed by commit rG2bef1c0e5645: [OpenMP] Lower taskyield using OpenMP IR Builder (authored by rogfer01). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70799/new/ https://revi

[PATCH] D69828: [OpenMP] Lower taskwait using OpenMP IR Builder

This revision was automatically updated to reflect the committed changes. Closed by commit rGa82f35e17621: [OpenMP] Lower taskwait using OpenMP IR Builder (authored by rogfer01). Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D74372: [OpenMP][IRBuilder] Perform finalization (incl. outlining) late

rogfer01 added inline comments. Comment at: llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp:114 + +// Add some known attributes to the outlined function. +Function *OutlinedFn = Extractor.extractCodeRegion(CEAC); This comment seems misplaced now.

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

rogfer01 added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:50 +static bool isExperimentalExtension(StringRef Ext) { + // Currently 'b' is the only supported experimental extension Suggestion: I think we can avoid these two functions

[PATCH] D70799: [OpenMP] Lower taskyield using OpenMP IR Builder

rogfer01 updated this revision to Diff 233524. rogfer01 added a comment. ChangeLog: - Rebase CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70799/new/ https://reviews.llvm.org/D70799 Files: clang/lib/CodeGen/CGOpenMPRuntime.cpp clang/test/OpenMP/taskyield_codegen.cpp llvm/include

[PATCH] D69785: [OpenMP] Introduce the OpenMP-IR-Builder

rogfer01 added inline comments. Comment at: llvm/include/llvm/Frontend/OpenMPKinds.def:165 + +__OMP_RTL(__kmpc_barrier, false, Void, IdentPtr, Int32) +__OMP_RTL(__kmpc_cancel_barrier, false, Int32, IdentPtr, Int32) jdoerfert wrote: > rogfer01 wrote: > > As we mig

[PATCH] D70799: [OpenMP] Lower taskyield using OpenMP IR Builder

rogfer01 created this revision. rogfer01 added reviewers: jdoerfert, kiranchandramohan. Herald added subscribers: llvm-commits, cfe-commits, guansong, hiraditya. Herald added projects: clang, LLVM. rogfer01 added a parent revision: D69922: [OpenMP] Use the OpenMP-IR-Builder. This is similar to D69

[PATCH] D69785: [OpenMP] Introduce the OpenMP-IR-Builder

rogfer01 added inline comments. Comment at: llvm/include/llvm/Frontend/OpenMPKinds.def:165 + +__OMP_RTL(__kmpc_barrier, false, Void, IdentPtr, Int32) +__OMP_RTL(__kmpc_cancel_barrier, false, Int32, IdentPtr, Int32) As we migrate, we will end with a significant nu

[PATCH] D69785: [OpenMP] Introduce the OpenMP-IR-Builder

rogfer01 added a comment. In D69785#1733233 , @jdoerfert wrote: > In D69785#1732951 , @rogfer01 wrote: > > > I made a small experiment lowering a `taskwait` (which is even simpler than > > `barrier` in "lowering" c

[PATCH] D69785: [OpenMP] Introduce the OpenMP-IR-Builder

rogfer01 added a comment. Hi @jdoerfert, thanks a lot for putting this up this initial skeleton and providing an example with `barrier`. I made a small experiment lowering a `taskwait` (which is even simpler than `barrier` in "lowering" complexity). It was pretty straightforward after all. I h

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

rogfer01 added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:475 + +if (MArch.startswith_lower("rv32")) { + if (MArch.substr(4).contains_lower("d") || lenary wrote: > rogfer01 wrote: > > `llvm::StringSwitch` has a method `Starts

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

rogfer01 added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:475 + +if (MArch.startswith_lower("rv32")) { + if (MArch.substr(4).contains_lower("d") || `llvm::StringSwitch` has a method `StartsWithLower` which might help make the

[PATCH] D20561: Warn when taking address of packed member

This revision was automatically updated to reflect the committed changes. Closed by commit rGf7b9f3149b76: Add missing tests (authored by rogfer01). Herald added a project: clang. Changed prior to commit: https://reviews.llvm.org/D20561?vs=67807&id=223564#toc Repository: rG LLVM Github Monore

[PATCH] D66003: [RISCV] Make -march=rv{32, 64}gc the default in RISC-V Linux

This revision was automatically updated to reflect the committed changes. Closed by commit rL371496: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux (authored by rogfer01, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit:

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

This revision was automatically updated to reflect the committed changes. Closed by commit rL371494: [RISCV] Default to ilp32d/lp64d in RISC-V Linux (authored by rogfer01, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://rev

[PATCH] D66003: [RISCV] Make -march=rv{32, 64}gc the default in RISC-V Linux

rogfer01 added a comment. Herald added a subscriber: pzheng. Thanks for the review @luismarques I plan to commit this shortly. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66003/new/ https://reviews.llvm.org/D66003

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

rogfer01 added a comment. Thanks for the review @lenary @luismarques We can indeed look at what defaults we want for baremetal in a later change. I plan to commit this shortly. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65634/new/ https://reviews.llvm.org/D65634

[PATCH] D66002: [RISCV] Move architecture parsing code into its own function

This revision was automatically updated to reflect the committed changes. Closed by commit rL371492: [RISCV] Move architecture parsing code into its own function (authored by rogfer01, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit:

[PATCH] D66002: [RISCV] Move architecture parsing code into its own function

rogfer01 added a comment. Herald added a subscriber: pzheng. Thanks for the review @luismarques I plan to commit this shortly. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66002/new/ https://reviews.llvm.org/D66002

[PATCH] D66003: [RISCV] Make -march=rv{32, 64}gc the default in RISC-V Linux

rogfer01 created this revision. rogfer01 added reviewers: asb, lenary. Herald added subscribers: cfe-commits, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook,

[PATCH] D66002: [RISCV] Move architecture parsing code into its own function

rogfer01 created this revision. rogfer01 added reviewers: asb, lenary. Herald added subscribers: cfe-commits, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook,

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

rogfer01 added a comment. Thanks for the clarification @asb. I've posted D66003 (depending on D66002 ) for that. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65634/new/ https://reviews.llvm.org/D65634 _

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

rogfer01 updated this revision to Diff 213812. rogfer01 retitled this revision from "[RISCV] Default to lp64d in 64-bit RISC-V Linux" to "[RISCV] Default to ilp32d/lp64d in RISC-V Linux". rogfer01 edited the summary of this revision. rogfer01 added a comment. ChangeLog: - Make `ilp32d` also the

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

rogfer01 added a comment. Thanks @asb @lenary for the review! I understand that, after this change, we will also want to make `-march=rv{32,64}gc` the default in Linux as well. Otherwise there will be an ABI mismatch with the default `-march=rv{32.64}i` in a default invocation. Does this make

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

This revision was automatically updated to reflect the committed changes. Closed by commit rL368128: [RISCV] Remove duplicated logic when determining the target ABI (authored by rogfer01, committed by ). Herald added subscribers: llvm-commits, jrtc27. Herald added a project: LLVM. Changed prior t

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

rogfer01 added a comment. Thanks @lenary ! I will commit this shortly. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D48357/new/ https://reviews.llvm.org/D48357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[PATCH] D65635: Sidestep false positive due to a matching git repository name

rogfer01 added a comment. Thanks @efriedma. I will commit this shortly. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65635/new/ https://reviews.llvm.org/D65635 ___ cfe-commits mailing list cfe-commits

[PATCH] D65635: Sidestep false positive due to a matching git repository name

This revision was automatically updated to reflect the committed changes. Closed by commit rL367826: Sidestep false positive due to a matching git repository name (authored by rogfer01, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit:

[PATCH] D65634: [RISCV] Default to lp64d in 64-bit RISC-V Linux

rogfer01 created this revision. rogfer01 added reviewers: asb, lenary. Herald added subscribers: cfe-commits, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook,

[PATCH] D65635: Sidestep false positive due to a matching git repository name

rogfer01 created this revision. rogfer01 added reviewers: eli.friedman, ddunbar. Herald added a project: clang. Herald added a subscriber: cfe-commits. rogfer01 edited reviewers, added: efriedma; removed: eli.friedman. I have failures in this test because the `grep @b` gets confused by the `clang

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

rogfer01 updated this revision to Diff 212970. rogfer01 added a comment. ChangeLog - Rebase change CHANGES SINCE LAST ACTION https://reviews.llvm.org/D48357/new/ https://reviews.llvm.org/D48357 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/lib/Driver/ToolChains/Clang.cpp Ind

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

rogfer01 added a comment. Hi @lenary, sure I can rebase this. However, I think it may be better to do the `lp64d` change in another phab so we can keep this one NFC. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D48357/new/ https://reviews.llvm.org/D48357 ___

[PATCH] D60456: [RISCV] Hard float ABI support

rogfer01 added a comment. > As noted in another comment, it's not entirely clear what zero-width bitfield > behaviour to match (see here > ) > as GCC seems buggy and the ABI is under-specified. Ideally I'd like to la

[PATCH] D60456: [RISCV] Hard float ABI support

rogfer01 added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9352 +return false; + // As a quirk of the ABI, zero-width bitfields aren't ignored for fp+fp + // or int+fp structs, but are ignored for a struct with an fp field and

[PATCH] D59298: [RISCV] Pass -target-abi to -cc1as

This revision was automatically updated to reflect the committed changes. Closed by commit rL356981: [RISCV] Pass -target-abi to -cc1as (authored by rogfer01, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org

[PATCH] D59298: [RISCV] Pass -target-abi to -cc1as

rogfer01 added a comment. Thanks Alex. I will commit it shortly. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59298/new/ https://reviews.llvm.org/D59298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:

[PATCH] D48357: [RISCV] Remove duplicated logic when determining the target ABI

rogfer01 added a comment. Herald added subscribers: jocewei, PkmX, rkruppe. @asb in D59298 I call `riscv::getRISCVABI` for `ClangAs`, does it make sense to make the same change for `Clang` here? Thank you. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D59298: [RISCV] Pass -target-abi to -cc1as

rogfer01 created this revision. rogfer01 added a reviewer: asb. Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar. Herald added a project: clang

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

rogfer01 added a comment. Looks sensible to me. I'm just curious why we want to prevent emission of atomic LLVM instructions at this point. Won't LLVM's AtomicExpand perform a similar lowering already? Perhaps the goal is to save that pass some work? Repository: rC Clang CHANGES SINCE LAST

[PATCH] D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand

rogfer01 abandoned this revision. rogfer01 added a comment. Upstream recently amended the ABI spec so it looks to me this is not going to be needed. CHANGES SINCE LAST ACTION https://reviews.llvm.o

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

This revision was automatically updated to reflect the committed changes. Closed by commit rC342060: [RISCV] Explicitly set an empty --sysroot in the test (authored by rogfer01, committed by ). Herald added a subscriber: jrtc27. Repository: rC Clang https://reviews.llvm.org/D51972 Files: te

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

rogfer01 added a comment. Thanks I will do it shortly. https://reviews.llvm.org/D51972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

rogfer01 added a comment. I can commit it. https://reviews.llvm.org/D51972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

rogfer01 added a comment. Thanks for the review! https://reviews.llvm.org/D51972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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