from:"Simon Cook via Phabricator via cfe\-commits"

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-25 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG666815d61bc2: [RISCV] Implement new architecture extension 
macros (authored by simoncook).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94403/new/

https://reviews.llvm.org/D94403

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -12,12 +12,27 @@
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_zba
+// CHECK-NOT: __riscv_zbb
+// CHECK-NOT: __riscv_zbc
+// CHECK-NOT: __riscv_zbe
+// CHECK-NOT: __riscv_zbf
+// CHECK-NOT: __riscv_zbm
+// CHECK-NOT: __riscv_zbp
+// CHECK-NOT: __riscv_zbproposedc
+// CHECK-NOT: __riscv_zbr
+// CHECK-NOT: __riscv_zbs
+// CHECK-NOT: __riscv_zbt
+// CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_zvamo
+// CHECK-NOT: __riscv_zvlsseg
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_m 200
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -25,12 +40,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_a 200
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_f 200
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -39,6 +56,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_d 200
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -47,13 +65,25 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 93000
 // CHECK-B-EXT: __riscv_bitmanip 1
+// CHECK-B-EXT: __riscv_zba 93000
+// CHECK-B-EXT: __riscv_zbb 93000
+// CHECK-B-EXT: __riscv_zbc 93000
+// CHECK-B-EXT: __riscv_zbe 93000
+// CHECK-B-EXT: __riscv_zbf 93000
+// CHECK-B-EXT: __riscv_zbm 93000
+// CHECK-B-EXT: __riscv_zbp 93000
+// CHECK-B-EXT: __riscv_zbr 93000
+// CHECK-B-EXT: __riscv_zbs 93000
+// CHECK-B-EXT: __riscv_zbt 93000
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
@@ -85,10 +115,98 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv64iv0p9 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_v 9000
 // CHECK-V-EXT: __riscv_vector 1
-//
+// CHECK-V-EXT: __riscv_zvamo 9000
+// CHECK-V-EXT: __riscv_zvlsseg 9000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-24 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 318869.
simoncook added a comment.

- Update to bitmanip 0.93
- Expand and support vector as per workaround in D95146 

- Add negative testing (check __riscv_b not defined for just subextension)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94403/new/

https://reviews.llvm.org/D94403

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -12,12 +12,27 @@
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_zba
+// CHECK-NOT: __riscv_zbb
+// CHECK-NOT: __riscv_zbc
+// CHECK-NOT: __riscv_zbe
+// CHECK-NOT: __riscv_zbf
+// CHECK-NOT: __riscv_zbm
+// CHECK-NOT: __riscv_zbp
+// CHECK-NOT: __riscv_zbproposedc
+// CHECK-NOT: __riscv_zbr
+// CHECK-NOT: __riscv_zbs
+// CHECK-NOT: __riscv_zbt
+// CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_zvamo
+// CHECK-NOT: __riscv_zvlsseg
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_m 200
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -25,12 +40,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_a 200
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_f 200
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -39,6 +56,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_d 200
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -47,13 +65,25 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 93000
 // CHECK-B-EXT: __riscv_bitmanip 1
+// CHECK-B-EXT: __riscv_zba 93000
+// CHECK-B-EXT: __riscv_zbb 93000
+// CHECK-B-EXT: __riscv_zbc 93000
+// CHECK-B-EXT: __riscv_zbe 93000
+// CHECK-B-EXT: __riscv_zbf 93000
+// CHECK-B-EXT: __riscv_zbm 93000
+// CHECK-B-EXT: __riscv_zbp 93000
+// CHECK-B-EXT: __riscv_zbr 93000
+// CHECK-B-EXT: __riscv_zbs 93000
+// CHECK-B-EXT: __riscv_zbt 93000
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
@@ -85,10 +115,98 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv64iv0p9 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_v 9000
 // CHECK-V-EXT: __riscv_vector 1
-//
+// CHECK-V-EXT: __riscv_zvamo 9000
+//

[PATCH] D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver

2021-01-24 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGafd483e57d16: [RISCV] Add support for Zvamo/Zvlsseg to 
driver (authored by simoncook).

Changed prior to commit:
  https://reviews.llvm.org/D94930?vs=317408=318868#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94930/new/

https://reviews.llvm.org/D94930

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -396,3 +396,41 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
 // RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 | 
\
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires 
'-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 
'rv32izvlsseg0p1'
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" 
"+experimental-zvlsseg"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,7 +62,7 @@
   Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
   Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "93"};
-  if (Ext == "v")
+  if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
 return RISCVExtensionVersion{"0", "9"};
   if (Ext == "zfh")
 return RISCVExtensionVersion{"0", "1"};


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -396,3 +396,41 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
 // RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-19 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 317591.
simoncook added a comment.

Have 'b'/'v' features imply subfeatures


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94403/new/

https://reviews.llvm.org/D94403

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -12,12 +12,26 @@
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_zbb
+// CHECK-NOT: __riscv_zbc
+// CHECK-NOT: __riscv_zbe
+// CHECK-NOT: __riscv_zbf
+// CHECK-NOT: __riscv_zbm
+// CHECK-NOT: __riscv_zbp
+// CHECK-NOT: __riscv_zbproposedc
+// CHECK-NOT: __riscv_zbr
+// CHECK-NOT: __riscv_zbs
+// CHECK-NOT: __riscv_zbt
+// CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_zvamo
+// CHECK-NOT: __riscv_zvlsseg
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_m 200
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -25,12 +39,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_a 200
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_f 200
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -39,6 +55,8 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_d 200
+// CHECK-D-EXT: __riscv_f 200
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -47,13 +65,24 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 92000
 // CHECK-B-EXT: __riscv_bitmanip 1
+// CHECK-B-EXT: __riscv_zbb 92000
+// CHECK-B-EXT: __riscv_zbc 92000
+// CHECK-B-EXT: __riscv_zbe 92000
+// CHECK-B-EXT: __riscv_zbf 92000
+// CHECK-B-EXT: __riscv_zbm 92000
+// CHECK-B-EXT: __riscv_zbp 92000
+// CHECK-B-EXT: __riscv_zbr 92000
+// CHECK-B-EXT: __riscv_zbs 92000
+// CHECK-B-EXT: __riscv_zbt 92000
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
@@ -85,10 +114,85 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv64iv0p9 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_v 9000
 // CHECK-V-EXT: __riscv_vector 1
-//
+// CHECK-V-EXT: __riscv_zvamo 9000
+// CHECK-V-EXT: __riscv_zvlsseg 9000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izbb0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izbb0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
+// CHECK-ZBB-EXT: __riscv_zbb 92000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izbc0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izbc0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
+// CHECK-ZBC-EXT: __riscv_zbc 92000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-18 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 317409.
simoncook added a comment.

Rebase on D94930  to show updated version


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94403/new/

https://reviews.llvm.org/D94403

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -12,12 +12,26 @@
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_zbb
+// CHECK-NOT: __riscv_zbc
+// CHECK-NOT: __riscv_zbe
+// CHECK-NOT: __riscv_zbf
+// CHECK-NOT: __riscv_zbm
+// CHECK-NOT: __riscv_zbp
+// CHECK-NOT: __riscv_zbproposedc
+// CHECK-NOT: __riscv_zbr
+// CHECK-NOT: __riscv_zbs
+// CHECK-NOT: __riscv_zbt
+// CHECK-NOT: __riscv_zfh
+// CHECK-NOT: __riscv_zvamo
+// CHECK-NOT: __riscv_zvlsseg
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_m 200
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -25,12 +39,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_a 200
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_f 200
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -39,6 +55,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_d 200
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -47,12 +64,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 92000
 // CHECK-B-EXT: __riscv_bitmanip 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
@@ -85,10 +104,83 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv64iv0p9 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_v 9000
 // CHECK-V-EXT: __riscv_vector 1
-//
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izbb0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izbb0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
+// CHECK-ZBB-EXT: __riscv_zbb 92000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izbc0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izbc0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
+// CHECK-ZBC-EXT: __riscv_zbc 92000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izbe0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izbe0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
+// CHECK-ZBE-EXT: __riscv_zbe 92000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izbf0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck

[PATCH] D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver

2021-01-18 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added reviewers: asb, luismarques, kito-cheng.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
niosHD, sabuasal, johnrusso, rbar.
simoncook requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94930

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,3 +392,41 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
 // RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 | 
\
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires 
'-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 
'rv32izvlsseg0p1'
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" 
"+experimental-zvlsseg"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,7 +62,7 @@
   Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
-  if (Ext == "v")
+  if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
 return RISCVExtensionVersion{"0", "9"};
   if (Ext == "zfh")
 return RISCVExtensionVersion{"0", "1"};


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,3 +392,41 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
 // RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
+//

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-18 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

In D94403#2504046 , @kito-cheng wrote:

> Thanks you implement that on clang, I think it's really great to included 
> that in LLVM 12 release.
>
> I would like to define marco for sub-extension too, I know that's my fault, I 
> didn't specify the behavior of sub-extension clearly on the spec, but I think 
> it would be great if we also define sub-extension marcos, since it would be 
> easier to check when some core only implement sub-extension, and the code can 
> just check the sub-extensio rather than check both.

That's no problem, I'll extend to cover sub-extensions before landing. I notice 
the zvamo/zvlsseg extensions aren't yet accepted by the -march flag, so I will 
put a patch together for those and likely land those together.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94403/new/

https://reviews.llvm.org/D94403

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[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-11 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 315805.
simoncook added a comment.

Correct constant used in macros, 2.0 should be 200 not 2000


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94403/new/

https://reviews.llvm.org/D94403

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -18,6 +18,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_m 200
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -25,12 +26,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_a 200
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_f 200
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -39,6 +42,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_d 200
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -47,12 +51,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 200
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 92000
 // CHECK-B-EXT: __riscv_bitmanip 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
@@ -85,10 +91,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv64iv0p9 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_v 9000
 // CHECK-V-EXT: __riscv_vector 1
 //
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
-// CHECK-ZFH-EXT: __riscv_zfh 1
+// CHECK-ZFH-EXT: __riscv_zfh 1000
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -109,13 +109,18 @@
   if (ABIName == "ilp32e")
 Builder.defineMacro("__riscv_abi_rve");
 
+  Builder.defineMacro("__riscv_arch_test");
+  Builder.defineMacro("__riscv_i", "200");
+
   if (HasM) {
+Builder.defineMacro("__riscv_m", "200");
 Builder.defineMacro("__riscv_mul");
 Builder.defineMacro("__riscv_div");
 Builder.defineMacro("__riscv_muldiv");
   }
 
   if (HasA) {
+Builder.defineMacro("__riscv_a", "200");
 Builder.defineMacro("__riscv_atomic");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
@@ -125,22 +130,32 @@
   }
 
   if (HasF || HasD) {
+Builder.defineMacro("__riscv_f", "200");
 Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
 Builder.defineMacro("__riscv_fdiv");
 Builder.defineMacro("__riscv_fsqrt");
   }
 
-  if (HasC)
+  if (HasD)
+Builder.defineMacro("__riscv_d", "200");
+
+  if (HasC) {
+Builder.defineMacro("__riscv_c", "200");
 Builder.defineMacro("__riscv_compressed");
+  }
 
-  if (HasB)
+  if (HasB) {
+Builder.defineMacro("__riscv_b", "92000");
 Builder.defineMacro("__riscv_bitmanip");
+  }
 
-  if (HasV)
+  if (HasV) {
+Builder.defineMacro("__riscv_v", "9000");
 Builder.defineMacro("__riscv_vector");
+  }
 
   if (HasZfh)
-

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-11 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added reviewers: asb, luismarques, kito-cheng.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, johnrusso, rbar.
simoncook requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

This adds support for the new architecture extension test macros as
defined in the C-API Document:
https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md

Extension versions have been taken from what are used in
RISCVTargetStreamer for ratified extensions, and the -march parser
for experimental extensions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94403

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -18,6 +18,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_m 2000
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -25,12 +26,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_a 2000
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_f 2000
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -39,6 +42,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_d 2000
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -47,12 +51,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_c 2000
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 92000
 // CHECK-B-EXT: __riscv_bitmanip 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
@@ -85,10 +91,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv64iv0p9 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
+// CHECK-V-EXT: __riscv_v 9000
 // CHECK-V-EXT: __riscv_vector 1
 //
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
-// CHECK-ZFH-EXT: __riscv_zfh 1
+// CHECK-ZFH-EXT: __riscv_zfh 1000
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -109,13 +109,18 @@
   if (ABIName == "ilp32e")
 Builder.defineMacro("__riscv_abi_rve");
 
+  Builder.defineMacro("__riscv_arch_test");
+  Builder.defineMacro("__riscv_i", "2000");
+
   if (HasM) {
+Builder.defineMacro("__riscv_m", "2000");
 Builder.defineMacro("__riscv_mul");
 Builder.defineMacro("__riscv_div");
 Builder.defineMacro("__riscv_muldiv");
   }
 
   if (HasA) {
+Builder.defineMacro("__riscv_a", "2000");
 Builder.defineMacro("__riscv_atomic");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
@@ -125,22 +130,32 @@
   }
 
   if (HasF || HasD) {
+Builder.defineMacro("__riscv_f", "2000");
 Builder.defineMacro("__riscv_flen", HasD ?

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

2020-07-16 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

In D80802#2156221 , @HsiangKai wrote:

> The modification is put in D81213 .


Ah ok, missed that, thanks for pointing it out


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[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

2020-07-16 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

Since this patch replaces 0.8 support with 0.9, it should include an update to 
the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match.


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[PATCH] D83819: [RISCV] Add error checking for extensions missing separating underscores

2020-07-15 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGde7bf722c23a: [RISCV] Add error checking for extensions 
missing separating underscores (authored by simoncook).

Repository:
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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -361,6 +361,10 @@
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92zbp0p92 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb0p92zbp0p92', multi-character extensions must be separated by 
underscores
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -89,7 +89,7 @@
 
   if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
-In = In.substr(Major.size());
+In = In.substr(Major.size() + 1);
 
 // Expected 'p' to be followed by minor version number.
 if (Minor.empty()) {
@@ -101,6 +101,16 @@
 }
   }
 
+  // Expected multi-character extension with version number to have no
+  // subsequent characters (i.e. must either end string or be followed by
+  // an underscore).
+  if (Ext.size() > 1 && In.size()) {
+std::string Error =
+"multi-character extensions must be separated by underscores";
+D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) << MArch << Error << In;
+return false;
+  }
+
   // If experimental extension, require use of current version number number
   if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
 if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -361,6 +361,10 @@
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92zbp0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb0p92zbp0p92', multi-character extensions must be separated by underscores
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -89,7 +89,7 @@
 
   if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
-In = In.substr(Major.size());
+In = In.substr(Major.size() + 1);
 
 // Expected 'p' to be followed by minor version number.
 if (Minor.empty()) {
@@ -101,6 +101,16 @@
 }
   }
 
+  // Expected multi-character extension with version number to have no
+  // subsequent characters (i.e. must either end string or be followed by
+  // an underscore).
+  if (Ext.size() > 1 && In.size()) {
+std::string Error =
+"multi-character extensions must be separated by underscores";
+D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) << MArch << Error << In;
+return false;
+  }
+
   // If experimental extension, require use of current version number number
   if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
 if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {
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[PATCH] D83819: [RISCV] Add error checking for extensions missing separating underscores

2020-07-14 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added reviewers: asb, lenary, edward-jones, lewis-revill.
Herald added subscribers: cfe-commits, evandro, luismarques, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, 
the_o, brucehoult, MartinMosbeck, rogfer01, zzheng, MaskRay, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, johnrusso, rbar.
Herald added a project: clang.

Currently if two multi-letter extensions are provided in a -march=
string, the verification code checks the version of the first and
consumes the second, resulting in that part of the architecture
string being ignored. This adds a test that when a version number has
been parsed for an extension, there are no subsequent characters.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83819

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -361,6 +361,10 @@
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92zbp0p92 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb0p92zbp0p92', multi-character extensions must be separated by 
underscores
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -89,7 +89,7 @@
 
   if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
-In = In.substr(Major.size());
+In = In.substr(Major.size() + 1);
 
 // Expected 'p' to be followed by minor version number.
 if (Minor.empty()) {
@@ -101,6 +101,16 @@
 }
   }
 
+  // Expected multi-character extension with version number to have no
+  // subsequent characters (i.e. must either end string or be followed by
+  // an underscore).
+  if (Ext.size() > 1 && In.size()) {
+std::string Error =
+"multi-character extensions must be separated by underscores";
+D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) << MArch << Error << In;
+return false;
+  }
+
   // If experimental extension, require use of current version number number
   if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
 if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -361,6 +361,10 @@
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92zbp0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb0p92zbp0p92', multi-character extensions must be separated by underscores
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -89,7 +89,7 @@
 
   if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
-In = In.substr(Major.size());
+In = In.substr(Major.size() + 1);
 
 // Expected 'p' to be followed by minor version number.
 if (Minor.empty()) {
@@ -101,6 +101,16 @@
 }
   }
 
+  // Expected multi-character extension with version number to have no
+  // subsequent characters (i.e. must either end string or be followed by
+  // an underscore).
+  if (Ext.size() > 1 && In.size()) {
+std::string Error =
+"multi-character extensions must be separated by underscores";
+D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) << MArch << Error << In;
+return false;
+  }
+
   // If experimental extension, require use of current version number number
   if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
 if

[PATCH] D81946: [WIP][RISCV] Enable multilib support even without a detected GCC install

2020-06-18 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

Thanks for this Ed. I've tried building a toolchain with it and noticed a 
couple of things:

1. Printing the set of multilibs doesn't provide a default, I think that should 
still be defined and printed with `-print-multi-libs`
2. There's a slight path finding issue if I build compiler-rt with an option 
like `-DCMAKE_INSTALL_PREFIX=$(clang -print-resource-dir)/${CRT_MULTILIB_DIR}` 
(the latter being the multilib dir printed by `-print-multi-libs`).

The build system installs crtbegin/crtend/clang_rt into 
`${CMAKE_INSTALL_PREFIX}/lib` (if I set the OS to ""), but clang searches for 
the multilib variants in a folder without `/lib` at the end.

Looking at compiler-rt's CMake that seems to be down to:

  if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE)
set(COMPILER_RT_LIBRARY_OUTPUT_DIR
  ${COMPILER_RT_OUTPUT_DIR})
set(COMPILER_RT_LIBRARY_INSTALL_DIR
  ${COMPILER_RT_INSTALL_PATH})
  else(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR)
set(COMPILER_RT_LIBRARY_OUTPUT_DIR
  ${COMPILER_RT_OUTPUT_DIR}/lib/${COMPILER_RT_OS_DIR})
set(COMPILER_RT_LIBRARY_INSTALL_DIR
  ${COMPILER_RT_INSTALL_PATH}/lib/${COMPILER_RT_OS_DIR})
  endif()

I can work around this by setting `COMPILER_RT_OS_DIR` to "..", but I'm 
wondering whether it makes more sense to allow "lib" to be replaced with a 
multilib directory name, preserving "lib" for the default multilib?

Other than that, a first bit of testing this is working great, it's nice having 
native bare metal RISC-V multilibs for Clang.


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[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

2020-04-21 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a reviewer: simoncook.
simoncook added a comment.

This is looking good, overall the patch is nicely laid out which has made it 
easy to compare against the spec.

I've made a few comments, mostly about ordering of instructions so that they 
are identical to the spec.

One question, I appreciate the Zvediv/Zvqmac sections say they are not planned 
to be part of the base V extension, but is it worth having them too behind 
separate flags so they can be used/evaluated. (I'm thinking like the 
Zbproposedc extension we added for bitmanip, which is not part of the proposed 
finalized 'B', but is included for comparisons).

The other thing I've noticed looking through the spec, there are references to 
psuedoinstructions, but these aren't covered by this patch. It would be good 
for `InstAlias`es to be defined for these and land in the same patch.




Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:160
+
+  Register Reg = RISCV::V0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));

If you are going to rely on the register names being contiguous, extend the 
static_asserts in RISCVRegisterInfo.cpp to validate this at compile time.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:449
+}
+}
+

Add comment noting end of earlyclobber/constraint scope



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:532
+// Vector Integer Move Instructions
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs1

I'm not sure if this will read better if you move the common `let vs2=0, vm=1` 
up here?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:551
+}
+}
+

Add `// hasSideEffects = 0, mayLoad = 0, mayStore = 0`



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:578
+
+// Vector Single-Width Integer Reduction Instructions
+defm VREDSUM : VALU_MV_V<"vredsum", 0b00>;

Following through the 0.8 spec I would have expected the `defm VFADD_V : 
VALU_FV_V_F` result here, since the previous instruction was defined in section 
13.5, and VFADD.V[VF] is the next thing defined in 14.2.

The chapter 14 instructions look like they are defined in the order the spec 
says (with the exception of VFREDOSUM, etc at the bottom of this file). Could 
you move chapter 13 instructions here so the order matches, to make it easier 
to validate as the spec advances.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:648
+
+}
+

The vfmv definition from line 814 should move here? (17.2?)



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:651
+foreach nf = [1, 2, 4, 8] in {
+  def VMV#nf#R_V  : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
+(ins VRegOp:$vs2), "vmv" # nf # "r.v",

This should be below vcompress?


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[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

2020-04-09 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG61ff29637501: [RISCV] Add Clang frontend support for 
Bitmanip extension (authored by s.egerton, committed by simoncook).

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x 
c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x 
c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,9 @@
 
   if (HasC)
 Builder.defineMacro("__riscv_compressed");
+
+  if (HasB)
+Builder.defineMacro("__riscv_bitmanip");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -139,6 +142,7 @@
   .Case("f", HasF)
   .Case("d", HasD)
   .Case("c", HasC)
+  .Case("experimental-b", HasB)
   .Default(false);
 }
 
@@ -156,6 +160,8 @@
   HasD = true;
 else if (Feature == "+c")
   HasC = true;
+else if (Feature == "+experimental-b")
+  HasB = true;
   }
 
   return true;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,9

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-04-09 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGdd1ee6dc076f: [RISCV] Support experimental/unratified 
extensions (authored by simoncook).

Changed prior to commit:
  https://reviews.llvm.org/D73891?vs=250770=256369#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -264,20 +264,20 @@
 // RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
 // RV32-IMINOR1: version number 2.1 for extension 'i'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix2p -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ixt2p -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s
-// RV32-XMINOR-MISS: error: invalid arch name 'rv32ix2p',
-// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'x2p'
+// RV32-XMINOR-MISS: error: invalid arch name 'rv32ixt2p',
+// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'xt'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32is2p0 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ist2p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
-// RV32-SMINOR0: error: invalid arch name 'rv32is2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 's2p0'
+// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
+// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32isx2p1 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32isxt2p1 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SXMINOR1 %s
-// RV32-SXMINOR1: error: invalid arch name 'rv32isx2p1', unsupported
-// RV32-SXMINOR1: version number 2.1 for extension 'sx2p1'
+// RV32-SXMINOR1: error: invalid arch name 'rv32isxt2p1', unsupported
+// RV32-SXMINOR1: version number 2.1 for extension 'sxt'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_ -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -327,3 +327,36 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s
+// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92_zbp0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
+// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
+// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -22,6

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

2020-03-17 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 250871.
simoncook added a comment.

Address feedback


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71553/new/

https://reviews.llvm.org/D71553

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x 
c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x 
c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,9 @@
 
   if (HasC)
 Builder.defineMacro("__riscv_compressed");
+
+  if (HasB)
+Builder.defineMacro("__riscv_bitmanip");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -139,6 +142,7 @@
   .Case("f", HasF)
   .Case("d", HasD)
   .Case("c", HasC)
+  .Case("experimental-b", HasB)
   .Default(false);
 }
 
@@ -156,6 +160,8 @@
   HasD = true;
 else if (Feature == "+c")
   HasC = true;
+else if (Feature == "+experimental-b")
+  HasB = true;
   }
 
   return true;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,9 @@
 
   if (HasC)
 Builder.defineMacro("__riscv_compressed");
+
+  if (HasB)
+

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

2020-03-17 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 250771.
simoncook added a comment.
Herald added a subscriber: evandro.

Rebase on new dependencies


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71553/new/

https://reviews.llvm.org/D71553

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x 
c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x 
c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,10 @@
 
   if (HasC)
 Builder.defineMacro("__riscv_compressed");
+
+  if (HasB) {
+Builder.defineMacro("__riscv_bitmanip");
+  }
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -139,6 +143,7 @@
   .Case("f", HasF)
   .Case("d", HasD)
   .Case("c", HasC)
+  .Case("experimental-b", HasB)
   .Default(false);
 }
 
@@ -156,6 +161,8 @@
   HasD = true;
 else if (Feature == "+c")
   HasC = true;
+else if (Feature == "+experimental-b")
+  HasB = true;
   }
 
   return true;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,10 @@
 
   if (HasC)
 Builder.defineMacro("__riscv_compressed");
+

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-03-17 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 250770.
simoncook added a comment.

- Update to match latest dependencies
- Handle adding "experimental-" to SubtargetFeatures for experimental features


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -264,20 +264,20 @@
 // RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
 // RV32-IMINOR1: version number 2.1 for extension 'i'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix2p -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ixt2p -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s
-// RV32-XMINOR-MISS: error: invalid arch name 'rv32ix2p',
-// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'x2p'
+// RV32-XMINOR-MISS: error: invalid arch name 'rv32ixt2p',
+// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'xt'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32is2p0 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ist2p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
-// RV32-SMINOR0: error: invalid arch name 'rv32is2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 's2p0'
+// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
+// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32isx2p1 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32isxt2p1 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SXMINOR1 %s
-// RV32-SXMINOR1: error: invalid arch name 'rv32isx2p1', unsupported
-// RV32-SXMINOR1: version number 2.1 for extension 'sx2p1'
+// RV32-SXMINOR1: error: invalid arch name 'rv32isxt2p1', unsupported
+// RV32-SXMINOR1: version number 2.1 for extension 'sxt'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_ -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -327,3 +327,36 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s
+// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92_zbp0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
+// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
+// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -22,6 +22,14 @@
 using namespace clang;
 using namespace llvm::opt;
 
+namespace {

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-10 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 243502.
simoncook added a comment.

Rebase, incorporate changes suggested by Lewis


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -264,20 +264,20 @@
 // RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
 // RV32-IMINOR1: version number 2.1 for extension 'i'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix2p -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ixt2p -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s
-// RV32-XMINOR-MISS: error: invalid arch name 'rv32ix2p',
-// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'x2p'
+// RV32-XMINOR-MISS: error: invalid arch name 'rv32ixt2p',
+// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'xt'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32is2p0 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ist2p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
-// RV32-SMINOR0: error: invalid arch name 'rv32is2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 's2p0'
+// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
+// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32isx2p1 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32isxt2p1 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SXMINOR1 %s
-// RV32-SXMINOR1: error: invalid arch name 'rv32isx2p1', unsupported
-// RV32-SXMINOR1: version number 2.1 for extension 'sx2p1'
+// RV32-SXMINOR1: error: invalid arch name 'rv32isxt2p1', unsupported
+// RV32-SXMINOR1: version number 2.1 for extension 'sxt'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_ -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -327,3 +327,36 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s
+// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+zbb"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92_zbp0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
+// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+zbb"
+// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+zbp"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -22,6 +22,14 @@
 using namespace clang;
 using namespace llvm::opt;
 
+namespace {
+// Represents the major and version number components of a RISC-V extension
+struct RISCVExtensionVersion {
+  StringRef

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-07 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 243325.
simoncook added a comment.

Add support for Z extensions also under this scheme.

In order to support these I've had to tweak the multi-letter extension parsing 
a little. The net result is that error messages printed regarding version 
numbers are now consistent between single letter standard extensions and any 
multi-letter extension.

This also makes a change to the feature names used for multi-letter extensions, 
previously an architecture like `rv32isxx1_sxx2` would be accepted with the 
TargetFeatures `sxx1` and `sxx2` being added. Now an error indicating that 
`sxx` has been used multiple times in the string, with just the feature `sxx` 
being added.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -264,20 +264,20 @@
 // RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
 // RV32-IMINOR1: version number 2.1 for extension 'i'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix2p -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ixt2p -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s
-// RV32-XMINOR-MISS: error: invalid arch name 'rv32ix2p',
-// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'x2p'
+// RV32-XMINOR-MISS: error: invalid arch name 'rv32ixt2p',
+// RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'xt'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32is2p0 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ist2p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
-// RV32-SMINOR0: error: invalid arch name 'rv32is2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 's2p0'
+// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
+// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32isx2p1 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32isxt2p1 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SXMINOR1 %s
-// RV32-SXMINOR1: error: invalid arch name 'rv32isx2p1', unsupported
-// RV32-SXMINOR1: version number 2.1 for extension 'sx2p1'
+// RV32-SXMINOR1: error: invalid arch name 'rv32isxt2p1', unsupported
+// RV32-SXMINOR1: version number 2.1 for extension 'sxt'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_ -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -327,3 +327,36 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
+// RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s
+// RV32-EXPERIMENTAL-ZBB: "-target-feature" "+zbb"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92_zbp0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-07 Thread Simon Cook via Phabricator via cfe-commits

simoncook planned changes to this revision.
simoncook added a comment.

With the update to D69987  adding the `Zvqmac` 
predicate, it seems both the `b` and `v` extensions have Z extensions that also 
need supporting using this method, I'll update this to also support Z shortly, 
but don't expect the general method to change, just adding the same version 
check elsewhere.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891



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[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-04 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 242286.
simoncook added a comment.

Switch to using `Optional` for returning version numbers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -327,3 +327,22 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+b"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -22,6 +22,14 @@
 using namespace clang;
 using namespace llvm::opt;
 
+namespace {
+// Represents the major and version number components of a RISC-V extension
+struct RISCVExtensionVersion {
+  StringRef Major;
+  StringRef Minor;
+};
+} // end anonymous namespace
+
 static StringRef getExtensionTypeDesc(StringRef Ext) {
   if (Ext.startswith("sx"))
 return "non-standard supervisor-level extension";
@@ -47,20 +55,27 @@
   return false;
 }
 
+// If the extension is supported as experimental, return the version of that
+// extension that the compiler currently supports.
+static Optional
+isExperimentalExtension(StringRef Ext) {
+  if (Ext == "b")
+return RISCVExtensionVersion{"0", "92"};
+  return None;
+}
+
 // Extensions may have a version number, and may be separated by
 // an underscore '_' e.g.: rv32i2_m2.
 // Version number is divided into major and minor version numbers,
 // separated by a 'p'. If the minor version is 0 then 'p0' can be
 // omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1.
-static bool getExtensionVersion(const Driver , StringRef MArch,
-StringRef Ext, StringRef In,
+static bool getExtensionVersion(const Driver , const ArgList ,
+StringRef MArch, StringRef Ext, StringRef In,
 std::string , std::string ) {
   Major = std::string(In.take_while(isDigit));
   In = In.substr(Major.size());
-  if (Major.empty())
-return true;
 
-  if (In.consume_front("p")) {
+  if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
 In = In.substr(Major.size());
 
@@ -74,7 +89,43 @@
 }
   }
 
-  // TODO: Handle extensions with version number.
+  // If experimental extension, require use of current version number number
+  if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
+if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {
+  std::string Error =
+  "requires '-menable-experimental-extensions' for experimental extension";
+  D.Diag(diag::err_drv_invalid_riscv_ext_arch_name)
+  << MArch << Error << Ext;
+  return false;
+} else if (Major.empty() && Minor.empty()) {
+  std::string Error =
+  "experimental extension requires explicit version number";
+  D.Diag(diag::err_drv_invalid_riscv_ext_arch_name)
+  << MArch << Error << Ext;
+  return false;
+}
+auto SupportedVers = *ExperimentalExtension;
+if (Major != SupportedVers.Major || Minor != SupportedVers.Minor) {
+  std::string Error =
+  "unsupported version number " + Major;
+  if (!Minor.empty())
+Error += "." + Minor;
+  Error += " for experimental extension (this compiler

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-04 Thread Simon Cook via Phabricator via cfe-commits

simoncook marked 2 inline comments as done.
simoncook added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:50
 
+static bool isExperimentalExtension(StringRef Ext) {
+  // Currently 'b' is the only supported experimental extension

rogfer01 wrote:
> Suggestion: I think we can avoid these two functions 
> (`isExperimentalExtension` and `getExperimentalExtensionVersion`) going out 
> of sync if we have only one of them and make it return an `llvm::Optional` of 
> the pair of versions.
> 
> Thent it can be used like this
> 
> ```lang=cpp
> if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
>std::pair SupportedVers = *ExperimentalVersion;
>...
> }
> ```
> 
> I'd also add a comment that the pair's `first` is the major version and 
> `second` is the minor version (or alternative use a struct with two public 
> fields `Major` and `Minor`)
That's a good idea, I'll update this to use this pattern.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:396
+  I += Minor.size() + 1 /*'p'*/;
+if (*I == '_')
+  ++I;

rogfer01 wrote:
> There is no test for that case but I'm afraid we can't test it yet, can we?
We can test for e.g. `rv32i_m` which is now accepted (GCC also accepts this 
option we didn't before), but the version number code I don't think there is 
until we support versions on more than one extension.


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[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

2020-02-03 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 242082.
simoncook added a comment.

Rebase changes on top of experimental feature support (D73891 
)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71553/new/

https://reviews.llvm.org/D71553

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x 
c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x 
c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,10 @@
 
   if (HasC)
 Builder.defineMacro("__riscv_compressed");
+
+  if (HasB) {
+Builder.defineMacro("__riscv_bitmanip");
+  }
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -139,6 +143,7 @@
   .Case("f", HasF)
   .Case("d", HasD)
   .Case("c", HasC)
+  .Case("b", HasB)
   .Default(false);
 }
 
@@ -156,6 +161,8 @@
   HasD = true;
 else if (Feature == "+c")
   HasC = true;
+else if (Feature == "+b")
+  HasB = true;
   }
 
   return true;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
 // CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_compressed 1
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@
   bool HasF;
   bool HasD;
   bool HasC;
+  bool HasB;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,10 @@
 
   if (HasC)

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-03 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 242080.
simoncook added a comment.

Don't put option in m_riscv_Features_Group, we don't want it being handled like 
a feature.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -327,3 +327,22 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+b"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -47,20 +47,32 @@
   return false;
 }
 
+static bool isExperimentalExtension(StringRef Ext) {
+  // Currently 'b' is the only supported experimental extension
+  if (Ext == "b")
+return true;
+  return false;
+}
+
+static std::pair
+getExperimentalExtensionVersion(StringRef Ext) {
+  if (Ext == "b")
+return {"0", "92"};
+  return {"", ""};
+}
+
 // Extensions may have a version number, and may be separated by
 // an underscore '_' e.g.: rv32i2_m2.
 // Version number is divided into major and minor version numbers,
 // separated by a 'p'. If the minor version is 0 then 'p0' can be
 // omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1.
-static bool getExtensionVersion(const Driver , StringRef MArch,
-StringRef Ext, StringRef In,
+static bool getExtensionVersion(const Driver , const ArgList ,
+StringRef MArch, StringRef Ext, StringRef In,
 std::string , std::string ) {
   Major = std::string(In.take_while(isDigit));
   In = In.substr(Major.size());
-  if (Major.empty())
-return true;
 
-  if (In.consume_front("p")) {
+  if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
 In = In.substr(Major.size());
 
@@ -74,7 +86,43 @@
 }
   }
 
-  // TODO: Handle extensions with version number.
+  // If experimental extension, require use of current version number number
+  if (isExperimentalExtension(Ext)) {
+if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {
+  std::string Error =
+  "requires '-menable-experimental-extensions' for experimental extension";
+  D.Diag(diag::err_drv_invalid_riscv_ext_arch_name)
+  << MArch << Error << Ext;
+  return false;
+} else if (Major.empty() && Minor.empty()) {
+  std::string Error =
+  "experimental extension requires explicit version number";
+  D.Diag(diag::err_drv_invalid_riscv_ext_arch_name)
+  << MArch << Error << Ext;
+  return false;
+}
+auto SupportedVers = getExperimentalExtensionVersion(Ext);
+if (Major != SupportedVers.first || Minor != SupportedVers.second) {
+  std::string Error =
+  "unsupported version number " + Major;
+  if (!Minor.empty())
+Error += "." + Minor;
+  Error += " for experimental extension (this compiler supports "
++ SupportedVers.first.str() + "."
++ SupportedVers.second.str() + ")";
+
+  D.Diag(diag::err_drv_invalid_riscv_ext_arch_name)
+  << MArch << Error << Ext;
+  return false;
+}
+return true;
+  }
+
+  // Allow extensions to declare no version number
+  if (Major.empty() && Minor.empty())
+return true;
+
+  // TODO: Handle

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

2020-02-03 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added reviewers: asb, lenary, PaoloS, s.egerton.
Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, 
pzheng, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, johnrusso, rbar.
Herald added a project: clang.
simoncook added a parent revision: D65649: [RISCV] Add MC encodings and tests 
of the Bit Manipulation extension.

This adds support for enabling experimental/unratified RISC-V ISA
extensions in the -march string in the case where an explicit version
number has been declared, and the -menable-experimental-extensions flag
has been provided.

This follows the design as discussed on the mailing lists in the
following RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Since the RISCV ToolChain definition currently rejects any extension
with an explicit version number, the parsing logic has been tweaked to
support this, and to allow standard extensions to have their versions
checked in future patches.

Support for the bitmanip 'b' extension has been added as a first example,
it should be clear how to extend this should vector 'v' land first.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73891

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -327,3 +327,22 @@
 // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+b"
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -47,20 +47,32 @@
   return false;
 }
 
+static bool isExperimentalExtension(StringRef Ext) {
+  // Currently 'b' is the only supported experimental extension
+  if (Ext == "b")
+return true;
+  return false;
+}
+
+static std::pair
+getExperimentalExtensionVersion(StringRef Ext) {
+  if (Ext == "b")
+return {"0", "92"};
+  return {"", ""};
+}
+
 // Extensions may have a version number, and may be separated by
 // an underscore '_' e.g.: rv32i2_m2.
 // Version number is divided into major and minor version numbers,
 // separated by a 'p'. If the minor version is 0 then 'p0' can be
 // omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1.
-static bool getExtensionVersion(const Driver , StringRef MArch,
-StringRef Ext, StringRef In,
+static bool getExtensionVersion(const Driver , const ArgList ,
+StringRef MArch, StringRef Ext, StringRef In,
 std::string , std::string ) {
   Major = std::string(In.take_while(isDigit));
   In = In.substr(Major.size());
-  if (Major.empty())
-return true;
 
-  if (In.consume_front("p")) {
+  if (Major.size() && In.consume_front("p")) {
 Minor = std::string(In.take_while(isDigit));
 In = In.substr(Major.size());
 
@@ -74,7 +86,43 @@
 }
   }
 
-  // TODO: Handle extensions with version number.
+  // If experimental extension, require use of current version number number
+  if (isExperimentalExtension(Ext)) {
+if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {
+  std::string Error =
+  "requires '-menable-experimental-extensions' for experimental extension";
+

[PATCH] D54214: [RISCV] Set triple based on -march flag

2019-11-18 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc00e5cf29d49: [RISCV] Set triple based on -march flag 
(authored by simoncook).

Changed prior to commit:
  https://reviews.llvm.org/D54214?vs=228261=229784#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54214/new/

https://reviews.llvm.org/D54214

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -541,6 +541,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -112,7 +112,8 @@
 Modified Compiler Flags
 ---
 
-- ...
+- RISC-V now sets the architecture (riscv32/riscv64) based on the value 
provided
+  to the ``-march`` flag, overriding the target provided by ``-triple``.
 
 New Pragmas in Clang
 


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -541,6 +541,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -112,7 +112,8 @@
 Modified Compiler Flags
 ---
 
-- ...
+- RISC-V now sets the architecture (riscv32/riscv64) based on the value provided
+  to the ``-march`` flag, overriding the target provided by ``-triple``.
 
 New Pragmas in Clang
 
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[PATCH] D54214: [RISCV] Set triple based on -march flag

2019-11-07 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 228261.
simoncook added a comment.

Rebase.

@lenary Following the discussion regarding D69383 
, I think it's best for now to keep the logic 
just keeping `-march` directly, rather than using `getRISCVArch`. I think in 
the case of `-target risc32-. -mabi=lp64` I think it would confuse users if 
the tools suddenly changed to doing an rv64 compile. If we disable that, all 
that function would provide me is the same StringRef I'm already evaluating. I 
think adding any extra flag to indicate whether a rv32<->rv64 switch is 
acceptable would just make the code unnecessarily more messy. I think in the 
future if `getRISCVArch` evaluates more flags, then it might make sense to 
reconsider this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54214/new/

https://reviews.llvm.org/D54214

Files:
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -541,6 +541,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -541,6 +541,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 
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[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

2019-10-25 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

I have a question about backwards compatibility with this patch. Clang 9 has 
shipped with rvXXg/etc defaulting to ilp32/lp64 ABI, and no march meaning 
rvXXi, with users having built objects with those defaults. When Clang 10 
ships, users they now need to always use a mabi/march flag to keep the same 
compatibility with their Clang 9 flows, the enabled extensions and ABI will be 
changed under their feet without warning (or at least until they either hit a 
linker error in the ABI case, or potentially an invalid instruction trap in the 
march case).

If we're going to change the defaults, this patch should at least contain an 
update to the release notes file, this way this change would be documented for 
users.




Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:476
+if (MArch.startswith_lower("rv32")) {
+  if (MArch.substr(4).contains_lower("d") ||
+  MArch.startswith_lower("rv32g"))

Won’t this break if the user specifies a X/Z extension that has a d in the 
name, so eg rv32iXd will try to use the ilp32d abi by default? For future 
proofing, I think we may need to do a full parse of the isa string to verify 
that d does actually mean the standard D-extension


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-10-23 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

In D67185#1718459 , @luismarques wrote:

> @simoncook: your commit doesn't include handling the case of TLS lowering 
> when `-ffixed-x4` is used.

I looked at this, and did start writing the patch that covers the use of TP/X4 
for TLS lowering, but didn't push it because it doesn't match the rest of the 
the cases I error on here. As it stands, what landed produces errors whenever a 
reserved register is //modified//, but not when they are read (so in for 
example the argument case you can use incoming arguments, but not lower calls 
to functions that need arguments.

For TLS I believe we would only be consuming X4, so erroring here would be 
inconsistent. I don't necessarily think producing an error whenever the 
compiler wishes to read a particular register is useful, for inlineasm there's 
no way to verify the validity of reading a particular register, but I don't 
think we can express that to the backend well anyway. I can work on a follow-up 
error/warn on all the reads case if we think that's of value, but as far as the 
intended purpose of stopping the compiler clobbering reserved registers, I 
don't think there's anything needed in that case.

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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-10-22 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGaed9d6d64a38: [RISCV] Add support for -ffixed-xX flags 
(authored by simoncook).

Changed prior to commit:
  https://reviews.llvm.org/D67185?vs=223005=226081#toc

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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-fixed-x-register.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -0,0 +1,130 @@
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x20 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X20
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x20

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-10-22 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

In D67185#1708177 , @asb wrote:

> In D67185#1707849 , @lenary wrote:
>
> > Note, D68862  is in-progress at the 
> > moment, which is related to this patch.
>
>
> Indeed - Simon, could you please go through that patch and ensure that the 
> implementation here is aligned to it (or indeed, feed back on that patch if 
> you feel they should be doing something differently). Thanks!

It looks like that patch is following the same route we are, using target 
features to implement this, both inspired by AArch64. There were some questions 
about using SubtargetFeatures for these kind of purposes and should these be 
function attributes instead. Given we’re already using features for things like 
relaxation, I’m inclined to stick with target features rather than split these 
between two different methodologies, especially since we have the AArch64 
precedence in this case.

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[PATCH] D54214: [RISCV] Set triple based on -march flag

2019-10-22 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.
Herald added a subscriber: pzheng.

Ping, before I rebased this did anyone have any other thoughts on flag 
precedence?


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-10-14 Thread Simon Cook via Phabricator via cfe-commits

simoncook marked 2 inline comments as done.
simoncook added inline comments.



Comment at: clang/include/clang/Driver/Options.td:2224
   HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
-foreach i = {1-7,9-15,18,20-28} in
-  def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
-HelpText<"Reserve the "#i#" register (AArch64 only)">;
+foreach i = {1-31} in
+  def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,

luismarques wrote:
> Given the expansion of the flags here, the AArch64 driver should probably 
> detect and reject the flags `-ffixed-x[8,16-17,19,29-31]`, to preserve the 
> old behavior where passing those flags  would be an error and to ensure that 
> erroneous flags are not silently accepted.
With this patch, for AArch64 using -ffixed-x8 for example will produce a 
warning that the flag is unused, similar to any other architecture trying to 
use these flags; I'll look at a follow-up patch that explicitly produces errors.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:53
 : RISCVGenSubtargetInfo(TT, CPU, FS),
+  UserReservedRegister(RISCV::NUM_TARGET_REGS),
   FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),

luismarques wrote:
> This includes more than the x0 - x31 registers. If the intent is to only 
> allow reserving the GPRs then this should be tightened.
For now this only covers GPRs, but going forward I was going to follow up with 
one for floating point, since these should also be reservable if we match all 
of GCCs behaviour, where every register should be marked as reserved.


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-10-03 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 223005.
simoncook added a reviewer: luismarques.
simoncook added a comment.

Rebase on top of tree, add @luismarques as reviewer


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-fixed-x-register.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -0,0 +1,130 @@
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x20 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X20
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x20 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X20
+; RUN: llc

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-09-19 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 220876.
simoncook added a comment.

Update to reflect comments about the fact registers are explicitly reserved. In 
addition to @lenary 's suggested change, I renamed `isReservedReg` to note the 
check that we are checking if its a user provided reservation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-fixed-x-register.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -0,0 +1,130 @@
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x20 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X20
+;

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-09-06 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 219068.
simoncook edited the summary of this revision.
simoncook added a comment.

Update based on initial feedback/going down the providing error route.

Unlike AArch64, which provides an error if a function tries to call a function 
with arguments and any of the argument passing registers are used, I've gone 
down a more detailed route. I've added tests for any place where any ABI 
register will be modified, and produce an error indicating what part of the ABI 
requires this register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D67185

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-fixed-x-register.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -0,0 +1,130 @@
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-09-05 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

For added context, I have gone and double-checked with GCC's implementation 
both for AArch64 and RISC-V and for registers used by the calling convention 
the compiler will still use them for argument passing and return values, but 
otherwise won't use it for any temporaries/register allocation purposes, which 
does have the side effect of confusing behaviour unless carefully documented.

I can implement errors for using calling convention registers when there are 
functions that take arguments, but this would be an explicit deviation in 
behaviour between the two compilers. I presume we would want to do that anyway 
because it's safer/more clear?


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-09-05 Thread Simon Cook via Phabricator via cfe-commits

simoncook planned changes to this revision.
simoncook added a comment.

Thanks for the feedback. I will improve the test so it more reliably tests what 
it intends to.

With regards to behaviour surrounding things such as argument registers, before 
submitting I checked what the riscv port of GCC does, and it matches this 
behaviour. If a register is used for arg passing/return values then the option 
is accepted but silently ignored (at least the register is still used for 
passing arguments, I haven't confirmed for other regalloc purposes).

I agree that this has the opportunity for allowing users to think they've 
reserved a register but it is still used. I will look at something more to what 
you've described AArch64 does in LLVM, and also check that there isn't also a 
bug on the GCC side, if so I'll get that fixed too.


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

2019-09-04 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, cfe-commits, pzheng, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, apazos, johnrusso, rbar, hiraditya, kristof.beyls, javed.absar.
Herald added projects: clang, LLVM.

This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. It is possible to reserve registers that the compiler
later ignores (such as x2/sp); this matches GCC's behavior.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67185

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-fixed-x-register.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -0,0 +1,135 @@
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x1 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X1
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x1 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X1
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X2
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X2
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
+;

[PATCH] D54214: [RISCV] Set triple based on -march flag

2019-08-01 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

In D54214#1609967 , @lenary wrote:

> What happens if I pass `clang -march=rv32i -target riscv64-unknown-elf`? 
> Should we care about the ordering of `-march` vs `-target`?

Currently this patch makes the output be generated for rv32i. I think that 
`-march` should override `-target` since it is more fine grained, is used as 
the default way of controlling extensions, and may be less confusing than last 
XLEN wins.

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[PATCH] D54214: [RISCV] Set triple based on -march flag

2019-08-01 Thread Simon Cook via Phabricator via cfe-commits

simoncook updated this revision to Diff 212772.
simoncook added a comment.
Herald added subscribers: s.egerton, lenary, Jim, benna, psnobl.
Herald added a project: clang.

Rebase on top of tree.

I've noticed that without this flag calling riscv32-unknown-elf-clang 
-march=rv64i will still produce a rv32 binary, which is unlike GCC's behavior


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Files:
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -537,6 +537,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -537,6 +537,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 
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[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

2019-07-31 Thread Simon Cook via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL367399: [RISCV] Add support for floating point registers in 
inlineasm (authored by simoncook, committed by ).
Herald added subscribers: llvm-commits, s.egerton.
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D64737?vs=209839=212540#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64737/new/

https://reviews.llvm.org/D64737

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.cpp
  cfe/trunk/test/Sema/riscv-asm.c


Index: cfe/trunk/test/Sema/riscv-asm.c
===
--- cfe/trunk/test/Sema/riscv-asm.c
+++ cfe/trunk/test/Sema/riscv-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 %s -triple riscv32 -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple riscv64 -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+void i (void) {
+  asm volatile ("" ::: "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7");
+  asm volatile ("" ::: "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15");
+  asm volatile ("" ::: "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23");
+  asm volatile ("" ::: "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31");
+
+  asm volatile ("" ::: "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2");
+  asm volatile ("" ::: "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5");
+  asm volatile ("" ::: "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7");
+  asm volatile ("" ::: "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6");
+}
+
+void f (void) {
+  asm volatile ("" ::: "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7");
+  asm volatile ("" ::: "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15");
+  asm volatile ("" ::: "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23");
+  asm volatile ("" ::: "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+
+  asm volatile ("" ::: "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  
"ft7");
+  asm volatile ("" ::: "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  
"fa5");
+  asm volatile ("" ::: "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  
"fs7");
+  asm volatile ("" ::: "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", 
"ft11");
+}
Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -19,23 +19,38 @@
 
 ArrayRef RISCVTargetInfo::getGCCRegNames() const {
   static const char *const GCCRegNames[] = {
+  // Integer registers
   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
-  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"};
+  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
+
+  // Floating point registers
+  "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+  "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
   return llvm::makeArrayRef(GCCRegNames);
 }
 
 ArrayRef RISCVTargetInfo::getGCCRegAliases() const {
   static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
-  {{"zero"}, "x0"}, {{"ra"}, "x1"},  {{"sp"}, "x2"},   {{"gp"}, "x3"},
-  {{"tp"}, "x4"},   {{"t0"}, "x5"},  {{"t1"}, "x6"},   {{"t2"}, "x7"},
-  {{"s0"}, "x8"},   {{"s1"}, "x9"},  {{"a0"}, "x10"},  {{"a1"}, "x11"},
-  {{"a2"}, "x12"},  {{"a3"}, "x13"}, {{"a4"}, "x14"},  {{"a5"}, "x15"},
-  {{"a6"}, "x16"},  {{"a7"}, "x17"}, {{"s2"}, "x18"},  {{"s3"}, "x19"},
-  {{"s4"}, "x20"},  {{"s5"}, "x21"}, {{"s6"}, "x22"},  {{"s7"}, "x23"},
-  {{"s8"}, "x24"},  {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
-  {{"t3"}, "x28"},  {{"t4"}, "x29"}, {{"t5"}, "x30"},  {{"t6"}, "x31"}};
+  {{"zero"}, "x0"}, {{"ra"}, "x1"},   {{"sp"}, "x2"},{{"gp"}, "x3"},
+  {{"tp"}, "x4"},   {{"t0"}, "x5"},   {{"t1"}, "x6"},{{"t2"}, "x7"},
+  {{"s0"}, "x8"},   {{"s1"}, "x9"},   {{"a0"}, "x10"},   {{"a1"}, "x11"},
+  {{"a2"}, "x12"},  {{"a3"}, "x13"},  {{"a4"}, "x14"},   {{"a5"}, "x15"},
+  {{"a6"}, "x16"},  {{"a7"}, "x17"},  {{"s2"}, "x18"},   {{"s3"}, "x19"},
+  {{"s4"}, "x20"},  {{"s5"}, "x21"},  {{"s6"}, "x22"},   {{"s7"}, "x23"},
+  {{"s8"}, "x24"},  {{"s9"}, "x25"},  {{"s10"}, "x26"},  {{"s11"}, "x27"},
+  {{"t3"}, "x28"},  {{"t4"}, "x29"},  {{"t5"}, "x30"},   {{"t6"}, "x31"},
+  {{"ft0"}, "f0"},  {{"ft1"}, "f1"},  {{"ft2"}, "f2"},   {{"ft3"}, "f3"},
+  {{"ft4"}, "f4"},  {{"ft5"}, "f5"},  {{"ft6"}, "f6"},   {{"ft7"}, "f7"},
+  {{"fs0"}, "f8"},  {{"fs1"}, "f9"},  {{"fa0"}, "f10"},  {{"fa1"}, "f11"},
+  {{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"},  {{"fa5"}, "f15"},
+  {{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"},

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

2019-07-15 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

As an aside, I've noticed a codegen issue when using floating point clobber 
lists, resulting in the implicit-defs not being added to INLINEASM 
instructions. I'm working on a fix for that now and will submit a second patch 
shortly.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D64737/new/

https://reviews.llvm.org/D64737



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[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

2019-07-15 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added a reviewer: asb.
Herald added subscribers: cfe-commits, lenary, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso, 
rbar.
Herald added a project: clang.
simoncook retitled this revision from "[PATCH] RISCV: Add support for floating 
point registers in inlineasm" to "RISCV: Add support for floating point 
registers in inlineasm".

This adds support for parsing/emitting in IR the floating-point RISC-V
registers in inline assembly clobber lists.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64737

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Sema/riscv-asm.c


Index: clang/test/Sema/riscv-asm.c
===
--- /dev/null
+++ clang/test/Sema/riscv-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 %s -triple riscv32 -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple riscv64 -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+void i (void) {
+  asm volatile ("" ::: "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7");
+  asm volatile ("" ::: "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15");
+  asm volatile ("" ::: "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23");
+  asm volatile ("" ::: "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31");
+
+  asm volatile ("" ::: "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2");
+  asm volatile ("" ::: "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5");
+  asm volatile ("" ::: "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7");
+  asm volatile ("" ::: "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6");
+}
+
+void f (void) {
+  asm volatile ("" ::: "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7");
+  asm volatile ("" ::: "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15");
+  asm volatile ("" ::: "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23");
+  asm volatile ("" ::: "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+
+  asm volatile ("" ::: "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  
"ft7");
+  asm volatile ("" ::: "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  
"fa5");
+  asm volatile ("" ::: "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  
"fs7");
+  asm volatile ("" ::: "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", 
"ft11");
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -19,23 +19,38 @@
 
 ArrayRef RISCVTargetInfo::getGCCRegNames() const {
   static const char *const GCCRegNames[] = {
+  // Integer registers
   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
-  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"};
+  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
+
+  // Floating point registers
+  "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+  "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
   return llvm::makeArrayRef(GCCRegNames);
 }
 
 ArrayRef RISCVTargetInfo::getGCCRegAliases() const {
   static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
-  {{"zero"}, "x0"}, {{"ra"}, "x1"},  {{"sp"}, "x2"},   {{"gp"}, "x3"},
-  {{"tp"}, "x4"},   {{"t0"}, "x5"},  {{"t1"}, "x6"},   {{"t2"}, "x7"},
-  {{"s0"}, "x8"},   {{"s1"}, "x9"},  {{"a0"}, "x10"},  {{"a1"}, "x11"},
-  {{"a2"}, "x12"},  {{"a3"}, "x13"}, {{"a4"}, "x14"},  {{"a5"}, "x15"},
-  {{"a6"}, "x16"},  {{"a7"}, "x17"}, {{"s2"}, "x18"},  {{"s3"}, "x19"},
-  {{"s4"}, "x20"},  {{"s5"}, "x21"}, {{"s6"}, "x22"},  {{"s7"}, "x23"},
-  {{"s8"}, "x24"},  {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
-  {{"t3"}, "x28"},  {{"t4"}, "x29"}, {{"t5"}, "x30"},  {{"t6"}, "x31"}};
+  {{"zero"}, "x0"}, {{"ra"}, "x1"},   {{"sp"}, "x2"},{{"gp"}, "x3"},
+  {{"tp"}, "x4"},   {{"t0"}, "x5"},   {{"t1"}, "x6"},{{"t2"}, "x7"},
+  {{"s0"}, "x8"},   {{"s1"}, "x9"},   {{"a0"}, "x10"},   {{"a1"}, "x11"},
+  {{"a2"}, "x12"},  {{"a3"}, "x13"},  {{"a4"}, "x14"},   {{"a5"}, "x15"},
+  {{"a6"}, "x16"},  {{"a7"}, "x17"},  {{"s2"}, "x18"},   {{"s3"}, "x19"},
+  {{"s4"}, "x20"},  {{"s5"}, "x21"},  {{"s6"}, "x22"},   {{"s7"}, "x23"},
+  {{"s8"}, "x24"},  {{"s9"}, "x25"},  {{"s10"}, "x26"},  {{"s11"}, "x27"},
+  {{"t3"}, "x28"},  {{"t4"}, "x29"},  {{"t5"}, "x30"},   {{"t6"}, "x31"},
+  {{"ft0"}, "f0"},  {{"ft1"}, "f1"},  {{"ft2"}, "f2"},   {{"ft3"}, "f3"},
+  {{"ft4"}, "f4"},  {{"ft5"}, "f5"},  {{"ft6"}, "f6"},   {{"ft7"}, "f7"},
+  {{"fs0"}, "f8"},  {{"fs1"}, "f9"},  {{"fa0"},

[PATCH] D57497: [RISCV] Passing -G value to RISCV backend

2019-01-31 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

As this mllvm option only affects the creation of ELF objects, do we also need 
to add a similar option for the LTO case, as the -G value would have no effect 
otherwise?


Repository:
  rC Clang

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[PATCH] D54214: [RISCV] Set triple based on -march flag

2018-11-07 Thread Simon Cook via Phabricator via cfe-commits

simoncook created this revision.
simoncook added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso, rbar.

For RISC-V the value provided to -march should determine whether to compile for 
32- or 64-bit RISC-V irrespective of the target provided to the Clang driver. 
This adds a test for this flag for RISC-V and sets the Target architecture 
correctly in these cases.


Repository:
  rC Clang

https://reviews.llvm.org/D54214

Files:
  lib/Driver/Driver.cpp
  test/Driver/riscv-arch.c


Index: test/Driver/riscv-arch.c
===
--- test/Driver/riscv-arch.c
+++ test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: lib/Driver/Driver.cpp
===
--- lib/Driver/Driver.cpp
+++ lib/Driver/Driver.cpp
@@ -506,6 +506,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 


Index: test/Driver/riscv-arch.c
===
--- test/Driver/riscv-arch.c
+++ test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
 // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
 // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
Index: lib/Driver/Driver.cpp
===
--- lib/Driver/Driver.cpp
+++ lib/Driver/Driver.cpp
@@ -506,6 +506,17 @@
 }
   }
 
+  // If target is RISC-V adjust the target triple according to
+  // provided architecture name
+  A = Args.getLastArg(options::OPT_march_EQ);
+  if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+  Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+  Target.setArch(llvm::Triple::riscv64);
+  }
+
   return Target;
 }
 
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[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

2018-08-15 Thread Simon Cook via Phabricator via cfe-commits

simoncook accepted this revision.
simoncook added a comment.
This revision is now accepted and ready to land.

My tests now look better, there are a couple of failures, but this seems to be 
a bug in newlib, rather than with clang/this patch (the bug was masked before 
as we would have been pulling in system headers). So this patch looks good to 
me.

@asb  Does this look good to you/are you able to commit this?


Repository:
  rC Clang

https://reviews.llvm.org/D50246



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[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

2018-08-14 Thread Simon Cook via Phabricator via cfe-commits

simoncook requested changes to this revision.
simoncook added a comment.
This revision now requires changes to proceed.
Herald added a subscriber: PkmX.

I've tested this, regression tests involving linking now mostly pass as crt0
can now be found, but it seems that system headers are still being pulled in
causing a couple of tests to fail. In particular using `limits.h` is causing
build failures for me.

Compiling with `-v`, I see for `riscv32-unknown-elf-clang`

#include "..." search starts here:
#include <...> search starts here:

/data/jenkins/workspace/riscv32-llvm-gcc-branches/install/bin/../lib/gcc/riscv32-unknown-elf/8.2.0/../../../../riscv32-unknown-elf/include
/usr/local/include

/data/jenkins/workspace/riscv32-llvm-gcc-branches/install/lib/clang/8.0.0/include
/usr/include
End of search list.

whereas for `riscv32-unknown-elf-gcc`:

#include "..." search starts here:
#include <...> search starts here:

/data/jenkins/workspace/riscv32-llvm-gcc-branches/install/lib/gcc/riscv32-unknown-elf/8.2.0/include

/data/jenkins/workspace/riscv32-llvm-gcc-branches/install/lib/gcc/riscv32-unknown-elf/8.2.0/include-fixed

/data/jenkins/workspace/riscv32-llvm-gcc-branches/install/lib/gcc/riscv32-unknown-elf/8.2.0/../../../../riscv32-unknown-elf/include
End of search list.

Can you see why system headers are still being pulled in unless `--sysroot` is
specified?

Repository:
rC Clang

https://reviews.llvm.org/D50246

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[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

2018-08-02 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

It seems the ability to link objects has been broken by this change. As an 
example from our nightly tests:

  Executing on host: riscv32-unknown-elf-clang 
/data/jenkins/workspace/riscv32-llvm-gcc/gcc-tests/gcc/testsuite/gcc.c-torture/execute/20080502-1.c
  -march=rv32gc -mabi=ilp32  -O1  -w  -lm  -o ./20080502-1.exe
(timeout = 600)
  spawn -ignore SIGHUP riscv32-unknown-elf-clang 
/data/jenkins/workspace/riscv32-llvm-gcc/gcc-tests/gcc/testsuite/gcc.c-torture/execute/20080502-1.c
 -march=rv32gc -mabi=ilp32 -O1 -w -lm -o ./20080502-1.exe
  /data/jenkins/workspace/riscv32-llvm-gcc/install/bin/riscv32-unknown-elf-ld: 
cannot find crt0.o: No such file or directory
  clang-8: error: ld command failed with exit code 1 (use -v to see invocation)
  compiler exited with status 1
  FAIL: gcc.c-torture/execute/20080502-1.c   -O1  (test for excess errors)

Running with `-v` shows the link command as:

  "/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/riscv32-unknown-elf-ld" 
crt0.o 
/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/../lib/gcc/riscv32-unknown-elf/8.1.0/crtbegin.o
 -L/lib 
-L/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/../lib/gcc/riscv32-unknown-elf/8.1.0
 /tmp/20080502-1-2b0022.o -lm --start-group -lc -lgloss --end-group -lgcc 
/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/../lib/gcc/riscv32-unknown-elf/8.1.0/crtend.o
 -o ./20080502-1.exe

What's noticeable is `crt0.o` is specified just as a file, and we're trying to 
link in my host `/lib/` (`-L/lib`)? If I manually specify a sysroot (via 
`--sysroot=$INSTALLDIR/riscv32-unknown-elf`), then my link succeeds, adding the 
path to `crt0.o`, and the correct `/lib`:

  "/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/riscv32-unknown-elf-ld" 
--sysroot=/data/jenkins/workspace/riscv32-llvm-gcc/install/riscv32-unknown-elf 
/data/jenkins/workspace/riscv32-llvm-gcc/install/riscv32-unknown-elf/lib/crt0.o 
/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/../lib/gcc/riscv32-unknown-elf/8.1.0/crtbegin.o
 -L/data/jenkins/workspace/riscv32-llvm-gcc/install/riscv32-unknown-elf/lib 
-L/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/../lib/gcc/riscv32-unknown-elf/8.1.0
 /tmp/20080502-1-d53be0.o -lm --start-group -lc -lgloss --end-group -lgcc 
/data/jenkins/workspace/riscv32-llvm-gcc/install/bin/../lib/gcc/riscv32-unknown-elf/8.1.0/crtend.o
 -o ./20080502-1.exe

I think there's some missing calculate the correct sysroot directory logic 
missing, unless linking `clang` to `riscv32-unknown-elf-clang` is no longer 
sufficient for everything to work now?


Repository:
  rC Clang

https://reviews.llvm.org/D46822



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[PATCH] D48412: [RISCV] Support for attribute((interrupt))

2018-06-21 Thread Simon Cook via Phabricator via cfe-commits

simoncook added a comment.

I think this should also cover mismatched arguments if the attribute appears 
several times, and reject/warn about the attribute combination in these cases.

For example, `__attribute__((interrupt("machine"))) 
__attribute__((interrupt("user"))) void foo() {}` is accepted, and adds the 
attribute `"interrupt"="user"`. It seems whichever is first used appears on the 
function.

I don't have an up to date GCC to compare to see what it does in this case, nor 
am sure whether repeating the same interrupt type should be accepted.


https://reviews.llvm.org/D48412



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