[PATCH] D157479: [Clang][DebugInfo] Emit narrower base types for structured binding declarations that bind to struct bitfields

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM with a few cosmetic suggestions.




Comment at: clang/lib/CodeGen/CGDebugInfo.cpp:4772
+QualType FinalTy = Context.getQualifiedType(IntTy, Quals);
+Ty = getOrCreateType(FinalTy, Unit);
+  }

Can Ty be null? If not then it might be more understandable to return Ty here. 
If it can be null, does it make sense to fall back to `BD->getType()` below?



Comment at: clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp:1
+// RUN: %clang_cc1 -emit-llvm -debug-info-kind=standalone -triple 
aarch64-arm-none-eabi %s -o - | FileCheck %s
+

This test looks suitable for update_cc1_checks, maybe with a --filter argument 
and each object in it's own function so that the relevant output is next to the 
code that it relates to.



Comment at: clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp:6
+  unsigned int y : 16;
+};
+

This would be easier to check if the structs had meaningful names, e.g. S_16_16


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[PATCH] D154915: [ARM][AArch64] Add ARM specific builtin for clz that is not undefined for 0 in ubsan.

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tmatheson added a comment.

Also thanks for fixing this!


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[PATCH] D154915: [ARM][AArch64] Add ARM specific builtin for clz that is not undefined for 0 in ubsan.

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tmatheson added a comment.

I would prefer the simplicity of adding a check in the intrinsic itself, rather 
than adding the target-specific builtins. Slightly worse codegen at -O0 doesn't 
matter imho. However I don't feel very strongly about it, so if others are 
happy with this then LGTM.


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[PATCH] D154910: [ARM][AArch64] Make ACLE __clzl/__clzll return unsigned int instead of unsigned long/uint64_t.

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tmatheson accepted this revision.
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This revision is now accepted and ready to land.

LGTM, thanks. Seems odd that the ACLE mixes `uint32_t` and `unsigned int`.


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[PATCH] D153130: [Clang][AArch64] Implement ACLE feature macro for FEAT_LRCPC3

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/lib/Basic/Targets/AArch64.cpp:420
+Builder.defineMacro("__ARM_FEATURE_RCPC", "3");
+  else if (HasRCPC)
 Builder.defineMacro("__ARM_FEATURE_RCPC", "1");

I didn't realise we hadn't implemented RPCP2 here. If we aren't aware of anyone 


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[PATCH] D153128: [AArch64][RCPC3] Add Neon intrinsics for LDAP1 and STL2

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM. ACLE PR here: https://github.com/ARM-software/acle/pull/265




Comment at: clang/lib/CodeGen/CGBuiltin.cpp:6769
+  // and vstl1(q)_lane, but codegen is equivalent for all of them. Choose an
+  // arbitrary one to be handled as tha canonical variation.
+  { NEON::BI__builtin_neon_vldap1_lane_u64, 
NEON::BI__builtin_neon_vldap1_lane_s64 },




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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs passed as function arguments

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tmatheson added a comment.

The description/commit message should reflect the final reasoning behind the 
change.


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs passed as function arguments

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tmatheson accepted this revision.
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This revision now requires review to proceed.

In D146242#4428051 , @chill wrote:

> But there isn't any other power of two between 8 and 16.

Ok, I see where I was going wrong, misreading C4 (it's the stack address which 
is "next multiple of N", which applies an alignment of N).

In that case I don't have any more objections.


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs passed as function arguments

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

In D146242#4427707 , @chill wrote:

> I was just thinking to LGTM it :)
>
> IMHO, the alignment adjustment  happens because of C.4 (B.3 indeed leave the 
> HFA/HVA unmodified).
>
>> C.4  If the argument is an HFA, an HVA, a Quad-precision Floating-point or 
>> short vector type then the NSAA is rounded up to the next multiple of 8 if 
>> its natural alignment is ≤ 8 or the next multiple of 16 if its natural 
>> alignment is ≥ 16.

I think that C2 would be hit first, suggesting it should be allocated a SIMD 
register and alignment should be irrelevant, assuming sufficient registers:

> C.2 If the argument is an HFA or an HVA and there are sufficient unallocated 
> SIMD and Floating-point registers (NSRN + number of members ≤ 8), then the 
> argument is allocated to SIMD and Floating-point registers (with one register 
> per member of the HFA or HVA). The NSRN is incremented by the number of 
> registers used. The argument has now been allocated.

If not enough registers, the size also needs rounded up:

> C.3 If the argument is an HFA or an HVA then the NSRN is set to 8 and the 
> size of the argument is rounded up to the nearest multiple of 8 bytes.

After that C4 would indeed be hit. However C4 differs from B6 
, in that C4 rounds up to the nearest multiple of 
8 or 16 (which is not what the patch currently does) whereas B6 
 restricts it to either 6 or 16 (which this what 
this patch does, but shouldn't apply to HVAs).

The final rule that actually does the allocation is C6:

> C.6 If the argument is an HFA, an HVA, a Half-, Single-, Double- or Quad- 
> precision Floating-point or short vector type, then the argument is copied to 
> memory at the adjusted NSAA. The NSAA is incremented by the size of the 
> argument. The argument has now been allocated.

(This is all in reference to HVA types like `struct { uint8x16_t m; };`)


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs passed as function arguments

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson requested changes to this revision.
tmatheson added a comment.
This revision now requires changes to proceed.

I think the current patch is wrong for a couple of reasons.

Firstly the data types being tested, e.g. `struct S { int8x16_t m; }` etc, are 
not just composite types, but HVAs:
https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#homogeneous-aggregates

> A Homogeneous Aggregate is a composite type where all of the Fundamental Data 
> Types of the members that compose the type are the same. The test for 
> homogeneity is applied after data layout is completed and without regard to 
> access control or other source language restrictions. Note that for 
> short-vector types the fundamental types are 64-bit vector and 128-bit 
> vector; the type of the elements in the short vector does not form part of 
> the test for homogeneity.

So these are HVAs with Fundamental Data Type of 128-bit vector. This explains 
why the alignment changes get applied, because they are scoped to 
`if(isHomogeneousAggregate)` which we would not expect to apply for normal 
composite types.

Since these are HVAs the relevant AAPCS64 rules are different. Specifically 
https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#parameter-passing

> B.3 If the argument type is an HFA or an HVA, then the argument is used 
> unmodified.

would be the "first matching rule" and B6  (the 
"alignment of the copy is either 8 or 16" rule) would not be applied.

If anyone can confirm or correct my reading of the above that would be 
appreciated. The rules are so spread out it's hard to be confident that I've 
taken everything into account.

I haven't checked if the current alignment for these HVA types is correct yet.


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs passed as function arguments

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/test/CodeGen/aarch64-ABI-align-packed.cpp:6
+// These tests check the ABI alignment of packed structs and packed fields
+// are consistent with the AAPCS64 document.
+extern "C" {

tmatheson wrote:
> The filename and description do not reflect what this file is actually doing, 
> which is specifically testing the alignment of the structs used for variable 
> argument lists.
Sorry out of date comment, ignore.


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs passed as function arguments

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a reviewer: stuij.
tmatheson added inline comments.



Comment at: clang/test/CodeGen/aarch64-ABI-align-packed.cpp:6
+// These tests check the ABI alignment of packed structs and packed fields
+// are consistent with the AAPCS64 document.
+extern "C" {

The filename and description do not reflect what this file is actually doing, 
which is specifically testing the alignment of the structs used for variable 
argument lists.


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[PATCH] D152023: [UBSan] Consider zero input to __builtin_clz/ctz to be undefined independent of the target.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

I think this breaks the ACLE header, see 
https://github.com/llvm/llvm-project/issues/63113


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs and fields

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

Reverse-ping  @JiruiWu


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[PATCH] D149119: [CMake] Use LLVM own tools in extract_symbols.py

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
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This revision is now accepted and ready to land.

LGTM, thank you for doing this. Please give it a couple of days in case others 
have comments.


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[PATCH] D149119: [CMake] Use llvm-nm to extract symbols for staged LTO builds on Windows

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tmatheson added a comment.

In D149119#4297540 , @ikudrin wrote:

> If I understand it right, we might not be able to build `llvm-nm` in cases 
> like cross-platform building, right?

LLVM has a way to build tools that need to run on the build machine as part of 
the build (`tablegen` for example), `llvm-nm` could be added to that system and 
then it would be available when `extract_symbols.py` is run. It would be an 
issue if `llvm-nm` ever had to depend on `extract_symbols.py` but that is not 
currently the case afaik.


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[PATCH] D149119: [CMake] Use llvm-nm to extract symbols for staged LTO builds on Windows

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

This looks like a nice addition. Would it make sense to use llvm-nm always, not 
restricted to bootstrap builds? And would that work on Windows and allow us to 
simplify this script substantially by using one tool for all platforms?


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs and fields

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

LGTM, but I'm not that familiar with the code that selects the alignment so it 
would be good to get a second opinion.




Comment at: clang/lib/CodeGen/TargetInfo.cpp:5806
   if (!IsWinVariadic && isHomogeneousAggregate(Ty, Base, Members)) {
 if (Kind != AArch64ABIInfo::AAPCS)
   return ABIArgInfo::getDirect(

Should this change cover AAPCS_VFP too?


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[PATCH] D146242: [ARM] Fixing ABI mismatch for packed structs and fields

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

Looks sensible but I don't fully understand the context of the change. Please 
could you explain more what is wrong with the current behaviour, and which 
parts of the AAPCS you are referring to.




Comment at: clang/lib/CodeGen/TargetInfo.cpp:5811
+// For alignment adjusted HFAs, cap the argument alignment to 16, otherwise
+// set it to 8 according to the AAPCS64 document.
 unsigned Align =

Does the similar code added in D100853 need updated too?



Comment at: clang/lib/CodeGen/TargetInfo.cpp:5814
 getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
-unsigned BaseAlign = getContext().getTypeAlignInChars(Base).getQuantity();
-Align = (Align > BaseAlign && Align >= 16) ? 16 : 0;
+Align = (Align >= 16) ? 16 : 8;
 return ABIArgInfo::getDirect(

Does this code definitely only apply when the ABI is AAPCS64, or should there 
be a check for that somewhere here? I can't tell whether the `if` on line 5806 
is sufficient.



Comment at: clang/test/CodeGen/aarch64-ABI-align-packed.cpp:1
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi \
+// RUN:   -target-feature +v8a \

Does this need the `arm` vendor in the triple?



Comment at: clang/test/CodeGen/aarch64-ABI-align-packed.cpp:1
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi \
+// RUN:   -target-feature +v8a \

tmatheson wrote:
> Does this need the `arm` vendor in the triple?
Please add a brief comment explaining what this is testing.


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[PATCH] D145781: [AArch64] Don't #define __ARM_FP when there's no FPU.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.

LGTM




Comment at: clang/lib/Basic/Targets/AArch64.h:29
 
-  enum FPUModeEnum { FPUMode, NeonMode = (1 << 0), SveMode = (1 << 1) };
+  enum FPUModeEnum { FPUMode = (1 << 0), NeonMode = (1 << 1), SveMode = (1 << 
2) };
 

clang-format please


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[PATCH] D145538: [NFC][AArch64] Document and improve FMV code.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for making these changes.




Comment at: llvm/include/llvm/TargetParser/AArch64TargetParser.h:567-568
+
+// For given features returns a mask to check if CPU support them. The mask is
+// used in Function Multi Versioning resolver conditions code generation.
 uint64_t getCpuSupportsMask(ArrayRef FeatureStrs);

`CPUFeatures` has 60 entries, which means the return value here will overflow 
if we add a few more entries. We should probably have a `static_assert(FEAT_MAX 
<= 64)` in the implementation. Or should the `CPUFeatures` values actually be 
bitmasks, like ArchExtKind?


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[PATCH] D142963: [AArch64] Handle negative architecture features

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

In D142963#4094545 , @andrewrk wrote:

> Speaking as the one who filed the motivating bug report, all of the above 
> behaviors are fine. The motivating use case is explicitly specifying a //full 
> set// of enabled/disabled features, leaving nothing changed by LLVM's own 
> dependency resolution. In this use case, LLVM would never see any of these 
> three scenarios as input.

This is not something that I would recommend that you do, at least until we 
have a coherent model for what enabling/disabling features via 
`-target-features` means with respect to backend features. Currently:

- Architecture features are treated specially in some cases,
- it's not clear what negative features mean with respect to dependent features,
- the order in which you specify the `-target-features` changes the results,
- etc.

We don't test any combinations that we don't expect out of the clang driver 
(these are the first clang tests ever added for negative architecture 
features). You might have more reliable results if you stick to only using 
negative features where they are needed to disable features that were 
implicitly enabled.


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[PATCH] D127812: [AArch64] FMV support and necessary target features dependencies.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

This patch has made it considerably harder to understand what is going on in 
the TargetParser. If you get a chance, please could you add some clarifying 
comments and tidy-ups. I appreciate that a lot of this is following the lead of 
the pre-existing TargetParser code, but lets try to improve it as we go.




Comment at: clang/include/clang/Basic/TargetInfo.h:1345
+  /// generation and get its dependent options in second argument.
+  virtual bool getFeatureDepOptions(StringRef Feature,
+std::string ) const {

Is this really useful for any other targets? It seems very specific to AArch64 
anf FMV, and at the only 2 call sites you are guaranteed to have an 
AArch64TargetInfo. Seems like an unnecessary extension to the interface.



Comment at: clang/include/clang/Basic/TargetInfo.h:1311
+  /// generation.
+  virtual bool isCodeImpactFeatureName(StringRef Feature) const { return true; 
}
+

samtebbs wrote:
> Similarly to the warning string, I think a name like 
> `featureAffectsCodeGen(...)` would be more clear in its use.
I agree that the function name doesn't suggest what the doc comment says this 
function does. Also, the meaning of the return value (does this affect 
codegen?) seems unrelated to the other output value (list of dependent options) 
so I don't understand why this is one function rather than two.



Comment at: clang/lib/AST/ASTContext.cpp:13302
+if (Target->validateCpuSupports(Feature.str()))
+  ResFeats.push_back("?" + Feature.str());
+  return ResFeats;

Is the meaning of this question mark explained anywhere? Could a more 
meaningful type be used rather than passing around strings?



Comment at: clang/lib/Basic/Targets/AArch64.cpp:664
+bool AArch64TargetInfo::getFeatureDepOptions(StringRef Name,
+ std::string ) const {
+  FeatureVec = llvm::StringSwitch(Name)

FeatureVec is not a vector.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:671
+   .Default("");
+  return FeatureVec != "";
+}

If I'm reading this right, this is saying that the extension "does not affect 
codegen" (from the docstring) if the extension's dependent features 
DEP_FEATURES //happens to be the empty string// (or an invalid extension name 
is passed in). IIUC, this is not a reasonable way to indicate that it does not 
affect codegen; an extra macro parameter/struct field would be more appropriate.



Comment at: llvm/include/llvm/TargetParser/AArch64TargetParser.def:108
 // FIXME: This would be nicer were it tablegen
-AARCH64_ARCH_EXT_NAME("invalid",  AArch64::AEK_INVALID, {},
  {})
-AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE,{},
  {})
-AARCH64_ARCH_EXT_NAME("crc",  AArch64::AEK_CRC, "+crc",
  "-crc")
-AARCH64_ARCH_EXT_NAME("lse",  AArch64::AEK_LSE, "+lse",
  "-lse")
-AARCH64_ARCH_EXT_NAME("rdm",  AArch64::AEK_RDM, "+rdm",
  "-rdm")
-AARCH64_ARCH_EXT_NAME("crypto",   AArch64::AEK_CRYPTO,  "+crypto", 
  "-crypto")
-AARCH64_ARCH_EXT_NAME("sm4",  AArch64::AEK_SM4, "+sm4",
  "-sm4")
-AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3,"+sha3",   
  "-sha3")
-AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2,"+sha2",   
  "-sha2")
-AARCH64_ARCH_EXT_NAME("aes",  AArch64::AEK_AES, "+aes",
  "-aes")
-AARCH64_ARCH_EXT_NAME("dotprod",  AArch64::AEK_DOTPROD, "+dotprod",
  "-dotprod")
-AARCH64_ARCH_EXT_NAME("fp",   AArch64::AEK_FP,  "+fp-armv8",   
  "-fp-armv8")
-AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD,"+neon",   
  "-neon")
-AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16,"+fullfp16",   
  "-fullfp16")
-AARCH64_ARCH_EXT_NAME("fp16fml",  AArch64::AEK_FP16FML, "+fp16fml",
  "-fp16fml")
-AARCH64_ARCH_EXT_NAME("profile",  AArch64::AEK_PROFILE, "+spe",
  "-spe")
-AARCH64_ARCH_EXT_NAME("ras",  AArch64::AEK_RAS, "+ras",
  "-ras")
-AARCH64_ARCH_EXT_NAME("rasv2",AArch64::AEK_RASv2,   "+rasv2",  
  "-rasv2")
-AARCH64_ARCH_EXT_NAME("sve",  AArch64::AEK_SVE, "+sve",
  "-sve")
-AARCH64_ARCH_EXT_NAME("sve2", AArch64::AEK_SVE2,"+sve2",   
  "-sve2")
-AARCH64_ARCH_EXT_NAME("sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes",   
  "-sve2-aes")
-AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4",   
  "-sve2-sm4")
-AARCH64_ARCH_EXT_NAME("sve2-sha3",AArch64::AEK_SVE2SHA3,"+sve2-sha3",  
  "-sve2-sha3")
-AARCH64_ARCH_EXT_NAME("sve2-bitperm", AArch64::AEK_SVE2BITPERM, 
"+sve2-bitperm", "-sve2-bitperm")

[PATCH] D142540: [NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

Looks great, thanks




Comment at: llvm/include/llvm/TargetParser/AArch64TargetParser.h:338
+
+  uint64_t getDefaultExtensions() const {
+return DefaultExtensions | Arch.DefaultExts;

nit: I would expect `getDefaultExtensions()` to return the value of 
`DefaultExtensions`. Is there a better naming combo we could use?


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[PATCH] D142539: [NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: llvm/unittests/TargetParser/TargetParserTest.cpp:1456
+  std::optional Extension =
+  AArch64::parseArchExtension(ArchExt);
+  if (!Extension)

I think we still need to test getDefaultExtensions, unless we're deleting it.


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[PATCH] D141404: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/test/Driver/aarch64-cssc.c:11
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv9.4-a+cssc   %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi 
-march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
 

Missing -###?


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:532
 getTargetDefinesARMV81A(Opts, Builder);
-break;
-  case llvm::AArch64::ArchKind::ARMV8_2A:
+  if (*ArchInfo == llvm::AArch64::ARMV8_2A)
 getTargetDefinesARMV82A(Opts, Builder);

danielkiss wrote:
> 
I'll fix this when I push



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:172
+   *ArchInfo == llvm::AArch64::ARMV9_1A ||
+   *ArchInfo == llvm::AArch64::ARMV9_2A)) {
 Features.push_back("+sve");

danielkiss wrote:
> Would be nice to add a custom operator to `ArchInfo` to say `*ArchInfo >= 
> llvm::AArch64::ARMV9A`
> because it looks to me here the `llvm::AArch64::ARMV9_3A` and 
> `llvm::AArch64::ARMV9_4A` are missing.
Good catch. This could be written as `if(ArchInfo.implies(ARMV9A))`, but I'll 
leave that for a follow up patch. I opted against a custom operator because 
they generally make things less understandable, except in cases where the 
ordering is very obvious, e.g. numeric types. For example 9.2 does not imply 
8.8. If you want to do an actual numerical comparison of version numbers you 
can compare ArchInfo.Versions directly.


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

Worth noting that this had to be reworked because both D127812 
 and D137838 
 went in since this was reverted.


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

The most recent versions of this patch contains squashed changes from these 
reviews:

- D139278  "[AArch64] Use string comparison 
for ArchInfo equality." This fixes the test failures with shared libraries, 
which were caused by each shared library ending up with it's own copy of the 
ArchInfo instances and hence breaking the equality-by-address.
- D139102  "[AArch64] Inline 
AArch64TargetParser.def"

The `ArchInfo` class is no longer non-copyable to satisfy C++20. The 
alternative of adding a constructor would have resulted in global constructor 
calls, which is not allowed in Support (the same presumably applies to the new 
TargetParser library).

I've tested locally with `LLVM_BUILD_LLVM_DYLIB=ON` + `LLVM_LINK_LLVM_DYLIB=ON` 
+ `CMAKE_CXX_STANDARD=20`.


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[PATCH] D141404: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

I agree the approach in D141518  makes more 
sense


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[PATCH] D140222: [AArch64] Check 128-bit Sysreg Builtins

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

Couple of nits, since you will be updating this anyway after dropping D140221 
, otherwise LGTM.




Comment at: clang/lib/Sema/SemaChecking.cpp:8297
  << Arg->getSourceRange();
   } else if (IsAArch64Builtin && Fields.size() == 1) {
+// If this is a write ...

It might be more readable to outline this whole branch and remove the redundant 
"else".



Comment at: clang/lib/Sema/SemaChecking.cpp:8298
   } else if (IsAArch64Builtin && Fields.size() == 1) {
-// If the register name is one of those that appear in the condition below
-// and the special register builtin being used is one of the write 
builtins,
-// then we require that the argument provided for writing to the register
-// is an integer constant expression. This is because it will be lowered to
-// an MSR (immediate) instruction, so we need to know the immediate at
-// compile time.
+// If this is a write ...
 if (TheCall->getNumArgs() != 2)

This comment style is a bit confusing; the actual code says if(NOT a write) 
return false; imo the code is readable enough without them.



Comment at: clang/lib/Sema/SemaChecking.cpp:8334-8340
+if (MaxLimit)
+  return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxLimit.value());
+
+// Otherwise, no checking is needed as we we lower to some kind of MSR
+// (register) rather than an MSR (immediate).
+return false;
   }

nit: stick to early return pattern



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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

@MaskRay I reverted that commit because it broke important functionality 
(comparison by address) to fix an issue in an unsupported C++ version, it 
wasn't reviewed, and it was not clear from the commit message what it was 
fixing. I explained this in a comment on the original commit but forgot to add 
it to the message for the revert, sorry.

@saugustine I have reverted the patch while I address the issues that you and 
others have raised. In future if would be helpful if you provided some 
information about how to reproduce the error. However it looks like this is 
also related to C++20, and I would like to understand what the policy is there. 
As far as I am aware this is an untested configuration. If you are building 
with C++20 and any otherwise-good patches that break your build must be 
reverted, then there should be a buildbot covering that configuration. Without 
a buildbot, I think the onus should be on you to suggesting a fix, or at least 
give enough details to reproduce the problem and allow time for a fix. 
Apologies if I have misunderstood something.


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: llvm/include/llvm/Support/AArch64TargetParser.h:154-160
+// Create ArchInfo structs named 
+#define AARCH64_ARCH(MAJOR, MINOR, PROFILE, NAME, ID, ARCH_FEATURE,
\
+ ARCH_BASE_EXT)
\
+  inline constexpr ArchInfo ID = {VersionTuple{MAJOR, MINOR}, PROFILE, NAME,   
\
+  ARCH_FEATURE, ARCH_BASE_EXT};
+#include "AArch64TargetParser.def"
+#undef AARCH64_ARCH

Hahnfeld wrote:
> bkramer wrote:
> > Is there a good reason for these to be defined in the header? This was 
> > wrong before and now works because of inline constexpr, but it's still 
> > wasting a bunch of compile time.
> It's also likely that this is the reason for the failures I see with 
> `LLVM_LINK_LLVM_DYLIB`, though I need to investigate more thoroughly what is 
> going wrong in there...
> Is there a good reason for these to be defined in the header? This was wrong 
> before and now works because of inline constexpr, but it's still wasting a 
> bunch of compile time.

I'm not aware of a good reason. Doing something to improve the compile time 
impact is on the list of things I'd like to get to. They need to be declared in 
the header because they are used for comparisons (open to other suggestions) 
but don't have to be defined there.

I expected `inline constexpr` to guarantee the same address across shared 
libraries, but it looks like maybe it doesn't?


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

Yes I will look into it and address the other comments when I have more time 
tomorrow or later this week. However I'm starting to think that the comparison 
by address is too easy to subtly break, and not immediately obvious to debug, 
and is therefore not worth it in this case. The performance of the comparison 
is not especially critical here afaik.


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

@Hahnfeld, @mgorny I was able to reproduce the failures with 
LLVM_LINK_LLVM_DYLIB, and they are failing because the comparison is failing 
because copies are being created. I don't fully understand how but presumably 
we are still ending up with one object per shared library. I tried adding a 
constructor as @bkramer suggested but this did not solve the issue. Please see 
D139278  for a fix.


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

In D138792#3966920 , @Hahnfeld wrote:

> Hi, I bisected this change to lead to a couple of test failures when building 
> with `LLVM_LINK_LLVM_DYLIB`. In the past, this had to do with global variable 
> initialization order, but nothing immediately jumps to my eye in this patch. 
> Is `AARCH64_ARCH` used to define global variables?

Hi, yes this change introduces a bunch of `inline constexpr` global variables 
in `AArch64TargetParser.h`.


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG450de8008bb0: [AArch64] Improve TargetParser API (authored 
by tmatheson).

Changed prior to commit:
  https://reviews.llvm.org/D138792?vs=478617=479249#toc

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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/VersionTuple.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -952,11 +952,11 @@
 TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
   ARMCPUTestParams params = GetParam();
 
-  AArch64::ArchKind AK = AArch64::parseCPUArch(params.CPUName);
-  EXPECT_EQ(params.ExpectedArch, AArch64::getArchName(AK));
+  const AArch64::ArchInfo  = AArch64::parseCpu(params.CPUName).Arch;
+  EXPECT_EQ(params.ExpectedArch, AI.Name);
 
   uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, AK);
+  AArch64::getDefaultExtensions(params.CPUName, AI);
   EXPECT_PRED_FORMAT2(AssertSameExtensionFlags,
   params.ExpectedFlags, default_extensions);
 }
@@ -1402,14 +1402,14 @@
   // valid, and match the expected 'magic' count.
   EXPECT_EQ(List.size(), NumAArch64CPUArchs);
   for(StringRef CPU : List) {
-EXPECT_NE(AArch64::parseCPUArch(CPU), AArch64::ArchKind::INVALID);
+EXPECT_NE(AArch64::parseCpu(CPU).Arch, AArch64::INVALID);
   }
 }
 
 bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
  unsigned ArchAttr) {
-  AArch64::ArchKind AK = AArch64::parseArch(Arch);
-  return AK != AArch64::ArchKind::INVALID;
+  const AArch64::ArchInfo  = AArch64::parseArch(Arch);
+  return AI != AArch64::INVALID;
 }
 
 TEST(TargetParserTest, testAArch64Arch) {
@@ -1445,148 +1445,81 @@
   ARMBuildAttrs::CPUArch::v8_A));
 }
 
-bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
+bool testAArch64Extension(StringRef CPUName, const AArch64::ArchInfo ,
   StringRef ArchExt) {
-  return AArch64::getDefaultExtensions(CPUName, AK) &
+  return AArch64::getDefaultExtensions(CPUName, AI) &
  AArch64::parseArchExt(ArchExt);
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
-  EXPECT_FALSE(testAArch64Extension("cortex-a34",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a35",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a53",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "dotprod"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a57",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a72",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a73",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75",
-AArch64::ArchKind::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a75",
-AArch64::ArchKind::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75",
-   AArch64::ArchKind::INVALID, "dotprod"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "fp16"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "fp16fml"));
-  

[PATCH] D138753: [AArch64TargetParser] getArchFeatures -> getArchFeature

[Tomas Matheson via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf57f086714bc: [AArch64TargetParser] getArchFeatures - 
getArchFeature (authored by tmatheson).

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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1689,14 +1689,23 @@
 }
 
 TEST(TargetParserTest, AArch64ArchFeatures) {
-  std::vector Features;
-
-  for (auto AK : AArch64::ArchKinds) {
-if (AK == AArch64::ArchKind::INVALID)
-  EXPECT_FALSE(AArch64::getArchFeatures(AK, Features));
-else
-  EXPECT_TRUE(AArch64::getArchFeatures(AK, Features));
-  }
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::INVALID), "+");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8A), "+v8a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_1A), "+v8.1a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_2A), "+v8.2a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_3A), "+v8.3a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_4A), "+v8.4a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_5A), "+v8.5a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_6A), "+v8.6a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_7A), "+v8.7a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_8A), "+v8.8a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_9A), "+v8.9a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9A), "+v9a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_1A), "+v9.1a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_2A), "+v9.2a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_3A), "+v9.3a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_4A), "+v9.4a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8R), "+v8r");
 }
 
 TEST(TargetParserTest, AArch64ArchV9toV8Conversion) {
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6889,7 +6889,7 @@
 
   // Get the architecture and extension features.
   std::vector AArch64Features;
-  AArch64::getArchFeatures(ID, AArch64Features);
+  AArch64Features.push_back(AArch64::getArchFeature(ID));
   AArch64::getExtensionFeatures(AArch64::getDefaultExtensions("generic", ID),
 AArch64Features);
 
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -80,12 +80,8 @@
   .Default(CPU);
 }
 
-bool AArch64::getArchFeatures(AArch64::ArchKind AK,
-  std::vector ) {
-  if (AK == ArchKind::INVALID)
-return false;
-  Features.push_back(AArch64ARCHNames[static_cast(AK)].ArchFeature);
-  return true;
+StringRef AArch64::getArchFeature(AArch64::ArchKind AK) {
+  return AArch64ARCHNames[static_cast(AK)].ArchFeature;
 }
 
 StringRef AArch64::getArchName(AArch64::ArchKind AK) {
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -160,7 +160,7 @@
 
 bool getExtensionFeatures(uint64_t Extensions,
   std::vector );
-bool getArchFeatures(ArchKind AK, std::vector );
+StringRef getArchFeature(ArchKind AK);
 
 StringRef getArchName(ArchKind AK);
 StringRef getSubArch(ArchKind AK);
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,8 +135,9 @@
 Features.push_back("+neon");
   } else {
 ArchKind = llvm::AArch64::parseCPUArch(CPU);
-if (!llvm::AArch64::getArchFeatures(ArchKind, Features))
+if (ArchKind == llvm::AArch64::ArchKind::INVALID)
   return false;
+Features.push_back(llvm::AArch64::getArchFeature(ArchKind));
 
 uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, ArchKind);
 if 

[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson marked an inline comment as done.
tmatheson added a comment.

Thanks for the review!


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[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 478617.
tmatheson added a comment.

Rename AI -> ArchInfo and delete move constructor/assignment


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/VersionTuple.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -952,11 +952,11 @@
 TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
   ARMCPUTestParams params = GetParam();
 
-  AArch64::ArchKind AK = AArch64::parseCPUArch(params.CPUName);
-  EXPECT_EQ(params.ExpectedArch, AArch64::getArchName(AK));
+  const AArch64::ArchInfo  = AArch64::parseCpu(params.CPUName).Arch;
+  EXPECT_EQ(params.ExpectedArch, AI.Name);
 
   uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, AK);
+  AArch64::getDefaultExtensions(params.CPUName, AI);
   EXPECT_PRED_FORMAT2(AssertSameExtensionFlags,
   params.ExpectedFlags, default_extensions);
 }
@@ -1402,14 +1402,14 @@
   // valid, and match the expected 'magic' count.
   EXPECT_EQ(List.size(), NumAArch64CPUArchs);
   for(StringRef CPU : List) {
-EXPECT_NE(AArch64::parseCPUArch(CPU), AArch64::ArchKind::INVALID);
+EXPECT_NE(AArch64::parseCpu(CPU).Arch, AArch64::INVALID);
   }
 }
 
 bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
  unsigned ArchAttr) {
-  AArch64::ArchKind AK = AArch64::parseArch(Arch);
-  return AK != AArch64::ArchKind::INVALID;
+  const AArch64::ArchInfo  = AArch64::parseArch(Arch);
+  return AI != AArch64::INVALID;
 }
 
 TEST(TargetParserTest, testAArch64Arch) {
@@ -1445,148 +1445,81 @@
   ARMBuildAttrs::CPUArch::v8_A));
 }
 
-bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
+bool testAArch64Extension(StringRef CPUName, const AArch64::ArchInfo ,
   StringRef ArchExt) {
-  return AArch64::getDefaultExtensions(CPUName, AK) &
+  return AArch64::getDefaultExtensions(CPUName, AI) &
  AArch64::parseArchExt(ArchExt);
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
-  EXPECT_FALSE(testAArch64Extension("cortex-a34",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a35",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a53",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a55",
-AArch64::ArchKind::INVALID, "dotprod"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a57",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a72",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a73",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75",
-AArch64::ArchKind::INVALID, "fp16"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a75",
-AArch64::ArchKind::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-a75",
-   AArch64::ArchKind::INVALID, "dotprod"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "fp16"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "fp16fml"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
-   AArch64::ArchKind::INVALID, "dotprod"));
-  EXPECT_TRUE(testAArch64Extension("cortex-r82",
- 

[PATCH] D138753: [AArch64TargetParser] getArchFeatures -> getArchFeature

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 478540.
tmatheson added a comment.

Reinstate unit test


Repository:
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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1684,14 +1684,23 @@
 }
 
 TEST(TargetParserTest, AArch64ArchFeatures) {
-  std::vector Features;
-
-  for (auto AK : AArch64::ArchKinds) {
-if (AK == AArch64::ArchKind::INVALID)
-  EXPECT_FALSE(AArch64::getArchFeatures(AK, Features));
-else
-  EXPECT_TRUE(AArch64::getArchFeatures(AK, Features));
-  }
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::INVALID), "+");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8A), "+v8a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_1A), "+v8.1a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_2A), "+v8.2a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_3A), "+v8.3a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_4A), "+v8.4a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_5A), "+v8.5a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_6A), "+v8.6a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_7A), "+v8.7a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_8A), "+v8.8a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8_9A), "+v8.9a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9A), "+v9a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_1A), "+v9.1a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_2A), "+v9.2a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_3A), "+v9.3a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV9_4A), "+v9.4a");
+  EXPECT_EQ(AArch64::getArchFeature(AArch64::ArchKind::ARMV8R), "+v8r");
 }
 
 TEST(TargetParserTest, AArch64ArchV9toV8Conversion) {
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6764,7 +6764,7 @@
 
   // Get the architecture and extension features.
   std::vector AArch64Features;
-  AArch64::getArchFeatures(ID, AArch64Features);
+  AArch64Features.push_back(AArch64::getArchFeature(ID));
   AArch64::getExtensionFeatures(AArch64::getDefaultExtensions("generic", ID),
 AArch64Features);
 
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -81,12 +81,8 @@
   .Default(CPU);
 }
 
-bool AArch64::getArchFeatures(AArch64::ArchKind AK,
-  std::vector ) {
-  if (AK == ArchKind::INVALID)
-return false;
-  Features.push_back(AArch64ARCHNames[static_cast(AK)].ArchFeature);
-  return true;
+StringRef AArch64::getArchFeature(AArch64::ArchKind AK) {
+  return AArch64ARCHNames[static_cast(AK)].ArchFeature;
 }
 
 StringRef AArch64::getArchName(AArch64::ArchKind AK) {
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -158,7 +158,7 @@
 
 bool getExtensionFeatures(uint64_t Extensions,
   std::vector );
-bool getArchFeatures(ArchKind AK, std::vector );
+StringRef getArchFeature(ArchKind AK);
 
 StringRef getArchName(ArchKind AK);
 StringRef getSubArch(ArchKind AK);
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,8 +135,9 @@
 Features.push_back("+neon");
   } else {
 ArchKind = llvm::AArch64::parseCPUArch(CPU);
-if (!llvm::AArch64::getArchFeatures(ArchKind, Features))
+if (ArchKind == llvm::AArch64::ArchKind::INVALID)
   return false;
+Features.push_back(llvm::AArch64::getArchFeature(ArchKind));
 
 uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, ArchKind);
 if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
@@ -160,9 +161,9 @@
   llvm::AArch64::ArchKind ArchKind = llvm::AArch64::parseArch(Split.first);
   if (Split.first == 

[PATCH] D138792: [AArch64] Improve TargetParser API

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
tmatheson added reviewers: lenary, pratlucas, dmgreen, tschuett, DavidSpickett, 
danielkiss.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
tmatheson requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.

I tried to split this into smaller commits, but couldn't find a way to do it
without requiring people to review a lot of code that would be deleted in the
next patch.

AArch64 only for now, but if it is accepted I will work on the same for ARM.

Key changes:

- Get rid of Arch enum, which is used to bind fields together. Instead of 
passing around ArchKind, use the named ArchInfo objects directly or via 
references.
- The list of all known ArchInfo becomes an array of pointers.
- ArchKind::operator-- is replaced with ArchInfo::operator< etc, which defines 
which architectures are predecessors to each other. This allows features from 
predecessor architectures to be added in a more intuitive way.
- Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some 
functions become unnecessary and are deleted.
- Version number and profile are added to the ArchInfo. This makes comparison 
of architectures easier and moves a couple of functions out of clang and into 
AArch64TargetParser.
- clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.
- AArch64::ArchProfile which is distinct from ARM::ArchProfile
- Give things sensible names and add some comments.


Repository:
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https://reviews.llvm.org/D138792

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/VersionTuple.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -952,11 +952,11 @@
 TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
   ARMCPUTestParams params = GetParam();
 
-  AArch64::ArchKind AK = AArch64::parseCPUArch(params.CPUName);
-  EXPECT_EQ(params.ExpectedArch, AArch64::getArchName(AK));
+  const AArch64::ArchInfo  = AArch64::parseCpu(params.CPUName).Arch;
+  EXPECT_EQ(params.ExpectedArch, AI.Name);
 
   uint64_t default_extensions =
-  AArch64::getDefaultExtensions(params.CPUName, AK);
+  AArch64::getDefaultExtensions(params.CPUName, AI);
   EXPECT_PRED_FORMAT2(AssertSameExtensionFlags,
   params.ExpectedFlags, default_extensions);
 }
@@ -1402,14 +1402,14 @@
   // valid, and match the expected 'magic' count.
   EXPECT_EQ(List.size(), NumAArch64CPUArchs);
   for(StringRef CPU : List) {
-EXPECT_NE(AArch64::parseCPUArch(CPU), AArch64::ArchKind::INVALID);
+EXPECT_NE(AArch64::parseCpu(CPU).Arch, AArch64::INVALID);
   }
 }
 
 bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
  unsigned ArchAttr) {
-  AArch64::ArchKind AK = AArch64::parseArch(Arch);
-  return AK != AArch64::ArchKind::INVALID;
+  const AArch64::ArchInfo  = AArch64::parseArch(Arch);
+  return AI != AArch64::INVALID;
 }
 
 TEST(TargetParserTest, testAArch64Arch) {
@@ -1445,148 +1445,81 @@
   ARMBuildAttrs::CPUArch::v8_A));
 }
 
-bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
+bool testAArch64Extension(StringRef CPUName, const AArch64::ArchInfo ,
   StringRef ArchExt) {
-  return AArch64::getDefaultExtensions(CPUName, AK) &
+  return AArch64::getDefaultExtensions(CPUName, AI) &
  AArch64::parseArchExt(ArchExt);
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
-  EXPECT_FALSE(testAArch64Extension("cortex-a34",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a35",
-AArch64::ArchKind::INVALID, "ras"));
-  EXPECT_FALSE(testAArch64Extension("cortex-a53",
-AArch64::ArchKind::INVALID, "ras"));
-  

[PATCH] D138753: [AArch64TargetParser] getArchFeatures -> getArchFeature

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: llvm/unittests/Support/TargetParserTest.cpp:1686
 
-TEST(TargetParserTest, AArch64ArchFeatures) {
-  std::vector Features;

pratlucas wrote:
> Can you keep a unit test covering the new version of the function?
The old version had special treatment for INVALID, but the new version is just 
returning the feature as written in AArch64TargetParser.def. A unit test would 
consist of a list of getArchFeature() calls with the same strings as in the 
.def. So I could certainly add it but I'm not sure that it adds any value as a 
unit test?


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[PATCH] D138753: [AArch64TargetParser] getArchFeatures -> getArchFeature

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
tmatheson added reviewers: lenary, pratlucas, dmgreen, tschuett, DavidSpickett.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
tmatheson requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138753

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1683,17 +1683,6 @@
   EXPECT_THAT(Features, ::testing::ContainerEq(AllFeatures));
 }
 
-TEST(TargetParserTest, AArch64ArchFeatures) {
-  std::vector Features;
-
-  for (auto AK : AArch64::ArchKinds) {
-if (AK == AArch64::ArchKind::INVALID)
-  EXPECT_FALSE(AArch64::getArchFeatures(AK, Features));
-else
-  EXPECT_TRUE(AArch64::getArchFeatures(AK, Features));
-  }
-}
-
 TEST(TargetParserTest, AArch64ArchV9toV8Conversion) {
   for (auto AK : AArch64::ArchKinds) {
 if (AK == AArch64::ArchKind::INVALID)
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6764,7 +6764,7 @@
 
   // Get the architecture and extension features.
   std::vector AArch64Features;
-  AArch64::getArchFeatures(ID, AArch64Features);
+  AArch64Features.push_back(AArch64::getArchFeature(ID));
   AArch64::getExtensionFeatures(AArch64::getDefaultExtensions("generic", ID),
 AArch64Features);
 
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -81,12 +81,8 @@
   .Default(CPU);
 }
 
-bool AArch64::getArchFeatures(AArch64::ArchKind AK,
-  std::vector ) {
-  if (AK == ArchKind::INVALID)
-return false;
-  Features.push_back(AArch64ARCHNames[static_cast(AK)].ArchFeature);
-  return true;
+StringRef AArch64::getArchFeature(AArch64::ArchKind AK) {
+  return AArch64ARCHNames[static_cast(AK)].ArchFeature;
 }
 
 StringRef AArch64::getArchName(AArch64::ArchKind AK) {
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -158,7 +158,7 @@
 
 bool getExtensionFeatures(uint64_t Extensions,
   std::vector );
-bool getArchFeatures(ArchKind AK, std::vector );
+StringRef getArchFeature(ArchKind AK);
 
 StringRef getArchName(ArchKind AK);
 StringRef getSubArch(ArchKind AK);
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,8 +135,9 @@
 Features.push_back("+neon");
   } else {
 ArchKind = llvm::AArch64::parseCPUArch(CPU);
-if (!llvm::AArch64::getArchFeatures(ArchKind, Features))
+if (ArchKind == llvm::AArch64::ArchKind::INVALID)
   return false;
+Features.push_back(llvm::AArch64::getArchFeature(ArchKind));
 
 uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, ArchKind);
 if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
@@ -160,9 +161,9 @@
   llvm::AArch64::ArchKind ArchKind = llvm::AArch64::parseArch(Split.first);
   if (Split.first == "native")
 ArchKind = llvm::AArch64::getCPUArchKind(llvm::sys::getHostCPUName().str());
-  if (ArchKind == llvm::AArch64::ArchKind::INVALID ||
-  !llvm::AArch64::getArchFeatures(ArchKind, Features))
+  if (ArchKind == llvm::AArch64::ArchKind::INVALID)
 return false;
+  Features.push_back(llvm::AArch64::getArchFeature(ArchKind));
 
   // Enable SVE2 by default on Armv9-A.
   // It can still be disabled if +nosve2 is present.
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -796,12 +796,9 @@
 
   // Parse the architecture version, adding the required features to
   // Ret.Features.
-  std::vector FeatureStrs;
-  if (ArchKind == llvm::AArch64::ArchKind::INVALID ||
-  !llvm::AArch64::getArchFeatures(ArchKind, FeatureStrs))
+  if (ArchKind == llvm::AArch64::ArchKind::INVALID)
 continue;
-   

[PATCH] D137836: [Support] Move getHostNumPhysicalCores to Threading.h

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.

One thought about returning -1 but otherwise LGTM




Comment at: llvm/lib/Support/Threading.cpp:59
   if (MaxThreadCount <= 0)
 MaxThreadCount = 1;
   if (ThreadsRequested == 0)

It looks like this is the only place `get_physical_cores` is used, and if the 
number is unknown or threading is disabled `MaxThreadCount` is just set to 1. 
Would it not make sense to change `get_physical_cores` to return 1, like 
`compute_thread_count`?


Repository:
  rG LLVM Github Monorepo

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[PATCH] D138579: [AArch64] Assembly support for FEAT_LRCPC3

[Tomas Matheson via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa6aaa969f7ca: [AArch64] Assembly support for FEAT_LRCPC3 
(authored by tmatheson).

Changed prior to commit:
  https://reviews.llvm.org/D138579?vs=478001=478005#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138579/new/

https://reviews.llvm.org/D138579

Files:
  clang/test/Driver/aarch64-lrcpc3.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/arm64-memory.s
  llvm/test/MC/AArch64/armv8.9a-lrcpc3.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,8 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
+  AArch64::AEK_RCPC3};
 
   std::vector Features;
 
@@ -1672,6 +1673,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
   EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+rcpc3"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
@@ -0,0 +1,113 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding   -mattr=+rcpc3 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s
+
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble   < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+
+[0x18,0x0a,0x00,0x99]
+# CHECK:  stilp   w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x18,0x0a,0x00,0x99]
+# CHECK:  stilp   w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x39,0x0a,0x01,0xd9]
+# CHECK:  stilp   x25, x1, [x17, #-16]!// encoding: [0x39,0x0a,0x01,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x39,0x0a,0x01,0xd9]
+# CHECK:  stilp   x25, x1, [x17, #-16]!// encoding: [0x39,0x0a,0x01,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x5a,0x1a,0x02,0x99]
+# CHECK:  stilp   w26, w2, [x18]   // encoding: [0x5a,0x1a,0x02,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xfb,0x1b,0x03,0xd9]
+# CHECK:  stilp   x27, x3, [sp]// encoding: [0xfb,0x1b,0x03,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9c,0x0a,0x44,0x99]
+# CHECK:  ldiapp  w28, w4, [x20], #8   // encoding: [0x9c,0x0a,0x44,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9c,0x0a,0x44,0x99]
+# CHECK:  ldiapp  w28, w4, [x20], #8   // encoding: [0x9c,0x0a,0x44,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xbd,0x0a,0x45,0xd9]
+# CHECK:  ldiapp  x29, x5, [x21], #16  // encoding: [0xbd,0x0a,0x45,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xbd,0x0a,0x45,0xd9]
+# CHECK:  ldiapp  x29, x5, [x21], #16  // encoding: [0xbd,0x0a,0x45,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xfe,0x1b,0x46,0x99]
+# CHECK:  ldiapp  w30, w6, [sp]// encoding: [0xfe,0x1b,0x46,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding

[PATCH] D138579: [AArch64] Assembly support for FEAT_LRCPC3

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 478001.
tmatheson marked 3 inline comments as done.
tmatheson added a comment.

Address comments and change instruction names


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138579/new/

https://reviews.llvm.org/D138579

Files:
  clang/test/Driver/aarch64-lrcpc3.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/arm64-memory.s
  llvm/test/MC/AArch64/armv8.9a-lrcpc3.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,8 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
+  AArch64::AEK_RCPC3};
 
   std::vector Features;
 
@@ -1672,6 +1673,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
   EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+rcpc3"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
@@ -0,0 +1,113 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding   -mattr=+rcpc3 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s
+
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble   < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+
+[0x18,0x0a,0x00,0x99]
+# CHECK:  stilp   w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x18,0x0a,0x00,0x99]
+# CHECK:  stilp   w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x39,0x0a,0x01,0xd9]
+# CHECK:  stilp   x25, x1, [x17, #-16]!// encoding: [0x39,0x0a,0x01,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x39,0x0a,0x01,0xd9]
+# CHECK:  stilp   x25, x1, [x17, #-16]!// encoding: [0x39,0x0a,0x01,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x5a,0x1a,0x02,0x99]
+# CHECK:  stilp   w26, w2, [x18]   // encoding: [0x5a,0x1a,0x02,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xfb,0x1b,0x03,0xd9]
+# CHECK:  stilp   x27, x3, [sp]// encoding: [0xfb,0x1b,0x03,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9c,0x0a,0x44,0x99]
+# CHECK:  ldiapp  w28, w4, [x20], #8   // encoding: [0x9c,0x0a,0x44,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9c,0x0a,0x44,0x99]
+# CHECK:  ldiapp  w28, w4, [x20], #8   // encoding: [0x9c,0x0a,0x44,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xbd,0x0a,0x45,0xd9]
+# CHECK:  ldiapp  x29, x5, [x21], #16  // encoding: [0xbd,0x0a,0x45,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xbd,0x0a,0x45,0xd9]
+# CHECK:  ldiapp  x29, x5, [x21], #16  // encoding: [0xbd,0x0a,0x45,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xfe,0x1b,0x46,0x99]
+# CHECK:  ldiapp  w30, w6, [sp]// encoding: [0xfe,0x1b,0x46,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xff,0x1a,0x47,0xd9]
+# CHECK:  ldiapp  xzr, x7, [x23]   // encoding: [0xff,0x1a,0x47,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid 

[PATCH] D138579: [AArch64] Assembly support for FEAT_LRCPC3

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
tmatheson requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch implements assembly support for the 2022 A-Profile Architecture
extension FEAT_LRCPC3. FEAT_LRCPC3 is AArch64 only and introduces new
variants of load/store instructions with release consistency ordering.

Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

This feature is optionally available from v8.2a and therefore not enabled by
default.

Contributors:

  Lucas Prates
  Sam Elliot
  Son Tuan Vu
  Tomas Matheson


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138579

Files:
  clang/test/Driver/aarch64-lrcpc3.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/arm64-memory.s
  llvm/test/MC/AArch64/armv8.9a-lrcpc3.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,8 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
+  AArch64::AEK_RCPC3};
 
   std::vector Features;
 
@@ -1672,6 +1673,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
   EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+rcpc3"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt
@@ -0,0 +1,113 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding   -mattr=+rcpc3 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s
+
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble   < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s
+
+[0x18,0x0a,0x00,0x99]
+# CHECK:  stilp   w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x18,0x0a,0x00,0x99]
+# CHECK:  stilp   w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x39,0x0a,0x01,0xd9]
+# CHECK:  stilp   x25, x1, [x17, #-16]!// encoding: [0x39,0x0a,0x01,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x39,0x0a,0x01,0xd9]
+# CHECK:  stilp   x25, x1, [x17, #-16]!// encoding: [0x39,0x0a,0x01,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x5a,0x1a,0x02,0x99]
+# CHECK:  stilp   w26, w2, [x18]   // encoding: [0x5a,0x1a,0x02,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xfb,0x1b,0x03,0xd9]
+# CHECK:  stilp   x27, x3, [sp]// encoding: [0xfb,0x1b,0x03,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9c,0x0a,0x44,0x99]
+# CHECK:  ldiapp  w28, w4, [x20], #8   // encoding: [0x9c,0x0a,0x44,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9c,0x0a,0x44,0x99]
+# CHECK:  ldiapp  w28, w4, [x20], #8   // encoding: [0x9c,0x0a,0x44,0x99]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xbd,0x0a,0x45,0xd9]
+# CHECK:  ldiapp  x29, x5, [x21], #16  // encoding: [0xbd,0x0a,0x45,0xd9]
+# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction 

[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138010/new/

https://reviews.llvm.org/D138010

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[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: llvm/include/llvm/Support/ARMTargetParser.def:127
+  ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+  ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
 ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a",

No ARM::AEK_SHA2 | ARM::AEK_AES? Or does 8.8 need updated?


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[PATCH] D137836: [Support] Move getHostNumPhysicalCores to Threading.h

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

Makes sense since it is so similar to `get_cpus()` and is only used in 
Threading.


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[PATCH] D137835: [ARM] Move ARM::parseBranchProtection into ARMTargetParser

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added inline comments.
This revision is now accepted and ready to land.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:47
 #include "llvm/Option/ArgList.h"
+#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/CodeGen.h"

For consistency this could just come via ARM.h


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[PATCH] D137564: [ARM] Move Triple::getARMCPUForArch into ARMTargetParser

[Tomas Matheson via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG103bbddde66f: [ARM] Move Triple::getARMCPUForArch into 
ARMTargetParser (authored by tmatheson).

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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  lldb/source/Utility/ArchSpec.cpp
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/ARMTargetParser.h
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/unittests/ADT/TripleTest.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -6,12 +6,13 @@
 //
 //===--===//
 
+#include "llvm/Support/TargetParser.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/Support/AArch64TargetParser.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/FormatVariadic.h"
-#include "llvm/Support/TargetParser.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 #include 
@@ -871,6 +872,70 @@
   EXPECT_EQ(5u, ARM::parseArchVersion(ARMArch[i]));
 }
 
+TEST(TargetParserTest, getARMCPUForArch) {
+  // Platform specific defaults.
+  {
+llvm::Triple Triple("arm--nacl");
+EXPECT_EQ("cortex-a8", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("arm--openbsd");
+EXPECT_EQ("cortex-a8", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armv6-unknown-freebsd");
+EXPECT_EQ("arm1176jzf-s", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("thumbv6-unknown-freebsd");
+EXPECT_EQ("arm1176jzf-s", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebv6-unknown-freebsd");
+EXPECT_EQ("arm1176jzf-s", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("arm--win32");
+EXPECT_EQ("cortex-a9", ARM::getARMCPUForArch(Triple));
+EXPECT_EQ("generic", ARM::getARMCPUForArch(Triple, "armv8-a"));
+  }
+  // Some alternative architectures
+  {
+llvm::Triple Triple("armv7k-apple-ios9");
+EXPECT_EQ("cortex-a7", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armv7k-apple-watchos3");
+EXPECT_EQ("cortex-a7", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armv7k-apple-tvos9");
+EXPECT_EQ("cortex-a7", ARM::getARMCPUForArch(Triple));
+  }
+  // armeb is permitted, but armebeb is not
+  {
+llvm::Triple Triple("armeb-none-eabi");
+EXPECT_EQ("arm7tdmi", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebeb-none-eabi");
+EXPECT_EQ("", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebv6eb-none-eabi");
+EXPECT_EQ("", ARM::getARMCPUForArch(Triple));
+  }
+  // xscaleeb is permitted, but armebxscale is not
+  {
+llvm::Triple Triple("xscaleeb-none-eabi");
+EXPECT_EQ("xscale", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebxscale-none-eabi");
+EXPECT_EQ("", ARM::getARMCPUForArch(Triple));
+  }
+}
+
 class AArch64CPUTestFixture
 : public ::testing::TestWithParam {};
 
Index: llvm/unittests/ADT/TripleTest.cpp
===
--- llvm/unittests/ADT/TripleTest.cpp
+++ llvm/unittests/ADT/TripleTest.cpp
@@ -1855,70 +1855,6 @@
 Triple::normalize("aarch64-linux-android21"));
 }
 
-TEST(TripleTest, getARMCPUForArch) {
-  // Platform specific defaults.
-  {
-llvm::Triple Triple("arm--nacl");
-EXPECT_EQ("cortex-a8", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("arm--openbsd");
-EXPECT_EQ("cortex-a8", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("armv6-unknown-freebsd");
-EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("thumbv6-unknown-freebsd");
-EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("armebv6-unknown-freebsd");
-EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("arm--win32");
-EXPECT_EQ("cortex-a9", Triple.getARMCPUForArch());
-EXPECT_EQ("generic", Triple.getARMCPUForArch("armv8-a"));
-  }
-  // Some alternative architectures
-  {
-llvm::Triple Triple("armv7k-apple-ios9");
-EXPECT_EQ("cortex-a7", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("armv7k-apple-watchos3");
-EXPECT_EQ("cortex-a7", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("armv7k-apple-tvos9");
-EXPECT_EQ("cortex-a7", Triple.getARMCPUForArch());
-  }
-  // armeb is permitted, but armebeb is not
-  {
-llvm::Triple Triple("armeb-none-eabi");
-

[PATCH] D137564: [ARM] Move Triple::getARMCPUForArch into ARMTargetParser

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
tmatheson added reviewers: lenary, pratlucas, DavidSpickett.
Herald added subscribers: hiraditya, kristof.beyls, dschuff.
Herald added a project: All.
tmatheson requested review of this revision.
Herald added subscribers: llvm-commits, lldb-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLDB, LLVM.

This is very backend specific so either belongs in Toolchains/ARM or in
ARMTargetParser. Since it is used in lldb, ARMTargetParser made more sense.

This is part of an effort to move information about ARM/AArch64 architecture
versions, extensions and CPUs into their respective TargetParsers.


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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  lldb/source/Utility/ArchSpec.cpp
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/ARMTargetParser.h
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/unittests/ADT/TripleTest.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -6,12 +6,13 @@
 //
 //===--===//
 
+#include "llvm/Support/TargetParser.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/Support/AArch64TargetParser.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/FormatVariadic.h"
-#include "llvm/Support/TargetParser.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 #include 
@@ -871,6 +872,70 @@
   EXPECT_EQ(5u, ARM::parseArchVersion(ARMArch[i]));
 }
 
+TEST(TargetParserTest, getARMCPUForArch) {
+  // Platform specific defaults.
+  {
+llvm::Triple Triple("arm--nacl");
+EXPECT_EQ("cortex-a8", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("arm--openbsd");
+EXPECT_EQ("cortex-a8", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armv6-unknown-freebsd");
+EXPECT_EQ("arm1176jzf-s", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("thumbv6-unknown-freebsd");
+EXPECT_EQ("arm1176jzf-s", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebv6-unknown-freebsd");
+EXPECT_EQ("arm1176jzf-s", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("arm--win32");
+EXPECT_EQ("cortex-a9", ARM::getARMCPUForArch(Triple));
+EXPECT_EQ("generic", ARM::getARMCPUForArch(Triple, "armv8-a"));
+  }
+  // Some alternative architectures
+  {
+llvm::Triple Triple("armv7k-apple-ios9");
+EXPECT_EQ("cortex-a7", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armv7k-apple-watchos3");
+EXPECT_EQ("cortex-a7", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armv7k-apple-tvos9");
+EXPECT_EQ("cortex-a7", ARM::getARMCPUForArch(Triple));
+  }
+  // armeb is permitted, but armebeb is not
+  {
+llvm::Triple Triple("armeb-none-eabi");
+EXPECT_EQ("arm7tdmi", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebeb-none-eabi");
+EXPECT_EQ("", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebv6eb-none-eabi");
+EXPECT_EQ("", ARM::getARMCPUForArch(Triple));
+  }
+  // xscaleeb is permitted, but armebxscale is not
+  {
+llvm::Triple Triple("xscaleeb-none-eabi");
+EXPECT_EQ("xscale", ARM::getARMCPUForArch(Triple));
+  }
+  {
+llvm::Triple Triple("armebxscale-none-eabi");
+EXPECT_EQ("", ARM::getARMCPUForArch(Triple));
+  }
+}
+
 class AArch64CPUTestFixture
 : public ::testing::TestWithParam {};
 
Index: llvm/unittests/ADT/TripleTest.cpp
===
--- llvm/unittests/ADT/TripleTest.cpp
+++ llvm/unittests/ADT/TripleTest.cpp
@@ -1855,70 +1855,6 @@
 Triple::normalize("aarch64-linux-android21"));
 }
 
-TEST(TripleTest, getARMCPUForArch) {
-  // Platform specific defaults.
-  {
-llvm::Triple Triple("arm--nacl");
-EXPECT_EQ("cortex-a8", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("arm--openbsd");
-EXPECT_EQ("cortex-a8", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("armv6-unknown-freebsd");
-EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("thumbv6-unknown-freebsd");
-EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("armebv6-unknown-freebsd");
-EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
-  }
-  {
-llvm::Triple Triple("arm--win32");
-EXPECT_EQ("cortex-a9", Triple.getARMCPUForArch());
-EXPECT_EQ("generic", Triple.getARMCPUForArch("armv8-a"));
-  }
-  // Some alternative architectures
-  {
-llvm::Triple Triple("armv7k-apple-ios9");
-

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: llvm/lib/TargetSupport/CMakeLists.txt:2
+
+set(LLVM_TARGET_DEFINITIONS ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
+

Here `RISCVTargetSupportTableGen` depends on files in `lib/Target/RISCV`, 
meaning the folder structure doesn't reflect the dependency graph and it looks 
like a circular dependency. It would be cleaner to keep the `TargetParser` data 
out of `lib/Target` in e.g. `llvm/lib/TargetSupport/RISCVTargetInfo.td`. If it 
is needed in `RISCV.td` it could be included from there.


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[PATCH] D132003: [clang][ARM][NFC] Clean up signed conversion and undefined macros in builtin header

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D132003: [clang][ARM][NFC] Clean up signed conversion and undefined macros in builtin header

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/lib/Headers/arm_acle.h:219
 __revsh(int16_t __t) {
-  return __builtin_bswap16(__t);
+  return (int16_t)__builtin_bswap16((int16_t)__t);
 }

Should the second cast be (uint16_t)__t?


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[PATCH] D123296: [llvm][AArch64] Generate getExtensionFeatures from the list of extensions

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added inline comments.
This revision is now accepted and ready to land.



Comment at: llvm/unittests/Support/TargetParserTest.cpp:1474
   EXPECT_FALSE(AArch64::getExtensionFeatures(AArch64::AEK_INVALID, Features));
   EXPECT_TRUE(!Features.size());
 

Does this need a similar test for NONE?


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[PATCH] D121093: [Driver][AArch64] Split up aarch64-cpus.c test further

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

LGTM


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[PATCH] D121093: [Driver][AArch64] Split up aarch64-cpus.c test further

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

Thanks for picking this up, LGTM




Comment at: clang/test/Driver/aarch64-archs.c:296
-// NO-LS64-NOT: "-target-feature" "+ls64"
-// LS64: "-target-feature" "+ls64"
-

Looks like these were duplicate tests? Besides `armv8.7a` vs `armv8.7-a`



Comment at: clang/test/Driver/aarch64-cpus.c:2
+// Check target CPUs are correctly passed.
+// TODO: The files should be split up by categories, e.g. by architecture 
versions, to avoid excessive test
 // times for large single test files.

tyb0807 wrote:
> simon_tatham wrote:
> > Tiniest nit ever: what files is this comment talking about?
> > 
> > (In the previous version, it followed on from a previous comment that gave 
> > the name of the file containing other half of the tests in question. Now it 
> > doesn't, so the wording is no longer clear.)
> This is for just in case we want to split up this file (aarch64-cpus.c) 
> further, into smaller files such as aarch64-cortex-a53.c, 
> aarch64-cortex-a57.c, etc. Do you think we still need to do this, or this 
> file looks ok to you in its current state?




Comment at: clang/test/Driver/aarch64-ras.c:14
+// RAS is on by default for v8.2a, but can be disabled by +noras
+// FIXME: in the current implementation, RAS is not on by default at all for 
v8.2a (the test says it all...)
+// RUN: %clang -target aarch64 -march=armv8.2a  -### -c %s 2>&1 | FileCheck 
-check-prefix=V82ARAS %s

The RAS test changes are the only functional change to this review, which is 
otherwise moving lines around and changing comments. I would keep the original 
tests even if they're wrong, so that the history remains clearer. Alternatively 
describe the RAS changes in the commit message and description.


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[PATCH] D120111: [AArch64] Default HBC/MOPS features in clang

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM, please give @nickdesaulniers some time to respond though. I do agree that 
iterating over the features repeatedly is less than ideal, but also that this 
patch is probably not the place to try to fix it.


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[PATCH] D120111: [AArch64] Default HBC/MOPS features in clang

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson requested changes to this revision.
tmatheson added inline comments.
This revision now requires changes to proceed.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:269
 success = getAArch64MicroArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Features);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Features, AF);
 

Looks like you could do `AF = Features.back()` below all these if/else 
conditions (where it is first used) based on the value of `success`. Maybe 
there is no need to pass it into `getAArch64MicroArchFeaturesFromMcpu` and the 
other functions?

Adding an extra output parameter to each of these functions (which duplicates 
an existing output parameter) seems unnecessary and makes the interfaces more 
complicated.


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[PATCH] D116415: [Arm] Remove duplicate CPU tests

[Tomas Matheson via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8aea5d5951dc: [Arm] Remove duplicate CPU tests (authored by 
tmatheson).

Changed prior to commit:
  https://reviews.llvm.org/D116415?vs=396681=397297#toc

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Files:
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Index: clang/test/Driver/arm-cortex-cpus.c
===
--- clang/test/Driver/arm-cortex-cpus.c
+++ clang/test/Driver/arm-cortex-cpus.c
@@ -28,7 +28,6 @@
 // RUN: %clang -target armv5 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V5-THUMB %s
 // RUN: %clang -target arm -march=armv5 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V5-THUMB %s
 // RUN: %clang -target armv5t -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V5-THUMB %s
-// RUN: %clang -target arm -march=armv5 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V5-THUMB %s
 // CHECK-V5-THUMB: "-cc1"{{.*}} "-triple" "thumbv5-{{.*}} "-target-cpu" "arm10tdmi"
 
 // RUN: %clang -target armv5e -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V5E %s
@@ -143,7 +142,7 @@
 // RUN: %clang -target arm -march=armv8 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
 // RUN: %clang -target armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
 // RUN: %clang -target arm -march=armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
-// RUN: %clang -target arm -mlittle-endian -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
+// RUN: %clang -target arm -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
 // CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armv8r-linux-gnueabi -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8R %s
@@ -176,7 +175,7 @@
 // RUN: %clang -mcpu=generic -target arm -march=armv8 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
 // RUN: %clang -mcpu=generic -target armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
-// RUN: %clang -mcpu=generic -target arm -mlittle-endian -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
+// RUN: %clang -mcpu=generic -target arm -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
 // CHECK-V8A-GENERIC: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V8A %s
@@ -214,17 +213,15 @@
 // RUN: %clang -target arm -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target arm -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -target arm -mlittle-endian -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
+// RUN: %clang -target arm -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -mcpu=generic -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -mcpu=generic -target arm -mlittle-endian -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
+// RUN: %clang -mcpu=generic -target arm -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // CHECK-V81A: "-cc1"{{.*}} "-triple" "armv8.1a-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A 

[PATCH] D116154: [ARM] Adding macros for coprocessor intrinsics as per ACLE

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 397127.
tmatheson added a comment.

Combine V8 and V9 macros


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116154/new/

https://reviews.llvm.org/D116154

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm-acle-coproc.c
  clang/test/Preprocessor/aarch64-target-features.c

Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -43,6 +43,7 @@
 // CHECK-NOT: __ARM_PCS_VFP 1
 // CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1
 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
+// CHECK-NOT: __ARM_TARGET_COPROC 1
 // CHECK-NOT: __ARM_FEATURE_SVE
 // CHECK-NOT: __ARM_FEATURE_DOTPROD
 // CHECK-NOT: __ARM_FEATURE_PAC_DEFAULT
Index: clang/test/CodeGen/arm-acle-coproc.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-acle-coproc.c
@@ -0,0 +1,350 @@
+// RUN: %clang_cc1 -triple armv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s
+// RUN: %clang_cc1 -triple armv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s
+// RUN: %clang_cc1 -triple armv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5 %s
+// RUN: %clang_cc1 -triple armv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s
+// RUN: %clang_cc1 -triple armv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s
+// RUN: %clang_cc1 -triple armv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6 %s
+// RUN: %clang_cc1 -triple armv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s
+// RUN: %clang_cc1 -triple armv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
+// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6k %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6kz %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s
+// RUN: %clang_cc1 -triple thumbv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-BASE %s
+// RUN: %clang_cc1 -triple thumbv8m.main %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-MAIN %s

[PATCH] D116154: [ARM] Adding macros for coprocessor intrinsics as per ACLE

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 397071.
tmatheson added a comment.

Add 8.8 and 9.3; patches adding these were merged first in the end.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116154/new/

https://reviews.llvm.org/D116154

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm-acle-coproc.c
  clang/test/Preprocessor/aarch64-target-features.c

Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -43,6 +43,7 @@
 // CHECK-NOT: __ARM_PCS_VFP 1
 // CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1
 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
+// CHECK-NOT: __ARM_TARGET_COPROC 1
 // CHECK-NOT: __ARM_FEATURE_SVE
 // CHECK-NOT: __ARM_FEATURE_DOTPROD
 // CHECK-NOT: __ARM_FEATURE_PAC_DEFAULT
Index: clang/test/CodeGen/arm-acle-coproc.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-acle-coproc.c
@@ -0,0 +1,350 @@
+// RUN: %clang_cc1 -triple armv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s
+// RUN: %clang_cc1 -triple armv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s
+// RUN: %clang_cc1 -triple armv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5 %s
+// RUN: %clang_cc1 -triple armv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s
+// RUN: %clang_cc1 -triple armv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s
+// RUN: %clang_cc1 -triple armv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6 %s
+// RUN: %clang_cc1 -triple armv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s
+// RUN: %clang_cc1 -triple armv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
+// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6k %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6kz %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s
+// RUN: %clang_cc1 -triple thumbv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-BASE %s
+// RUN: %clang_cc1 -triple thumbv8m.main %s -E -dD -o - | 

[PATCH] D116159: [ARM][AArch64] clang support for Armv9.3-A

[Tomas Matheson via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4435d1819efe: [ARM][AArch64] clang support for Armv9.3-A 
(authored by tmatheson).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116159/new/

https://reviews.llvm.org/D116159

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c

Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -879,6 +879,11 @@
 // CHECK-V92A: #define __ARM_ARCH_9_2A__ 1
 // CHECK-V92A: #define __ARM_ARCH_PROFILE 'A'
 
+// RUN: %clang -target armv9.3a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V93A %s
+// CHECK-V93A: #define __ARM_ARCH 9
+// CHECK-V93A: #define __ARM_ARCH_9_3A__ 1
+// CHECK-V93A: #define __ARM_ARCH_PROFILE 'A'
+
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
Index: clang/test/Driver/arm-cortex-cpus.c
===
--- clang/test/Driver/arm-cortex-cpus.c
+++ clang/test/Driver/arm-cortex-cpus.c
@@ -437,6 +437,22 @@
 // RUN: %clang -target arm -march=armebv9.2-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s
 // CHECK-BE-V92A: "-cc1"{{.*}} "-triple" "armebv9.2{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// CHECK-V93A: "-cc1"{{.*}} "-triple" "armv9.3{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// CHECK-BE-V93A: "-cc1"{{.*}} "-triple" "armebv9.3{{.*}}" "-target-cpu" "generic"
+
 // Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
 // on and off. Cortex-A53 is a placeholder for now.
 // RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1 | FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
Index: clang/test/Driver/aarch64-cpus.c
===
--- clang/test/Driver/aarch64-cpus.c
+++ clang/test/Driver/aarch64-cpus.c
@@ -876,6 +876,22 @@
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s
 // GENERICV92A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.2a" "-target-feature" "+i8mm" "-target-feature" "+bf16" "-target-feature" "+sve" "-target-feature" "+sve2"
 
+// RUN: %clang -target aarch64 -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// GENERICV93A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.3a"
+
+// RUN: %clang -target 

[PATCH] D116159: [ARM][AArch64] clang support for Armv9.3-A

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 397044.
tmatheson added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116159/new/

https://reviews.llvm.org/D116159

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c

Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -879,6 +879,11 @@
 // CHECK-V92A: #define __ARM_ARCH_9_2A__ 1
 // CHECK-V92A: #define __ARM_ARCH_PROFILE 'A'
 
+// RUN: %clang -target armv9.3a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V93A %s
+// CHECK-V93A: #define __ARM_ARCH 9
+// CHECK-V93A: #define __ARM_ARCH_9_3A__ 1
+// CHECK-V93A: #define __ARM_ARCH_PROFILE 'A'
+
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
Index: clang/test/Driver/arm-cortex-cpus.c
===
--- clang/test/Driver/arm-cortex-cpus.c
+++ clang/test/Driver/arm-cortex-cpus.c
@@ -437,6 +437,22 @@
 // RUN: %clang -target arm -march=armebv9.2-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s
 // CHECK-BE-V92A: "-cc1"{{.*}} "-triple" "armebv9.2{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// CHECK-V93A: "-cc1"{{.*}} "-triple" "armv9.3{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// CHECK-BE-V93A: "-cc1"{{.*}} "-triple" "armebv9.3{{.*}}" "-target-cpu" "generic"
+
 // Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
 // on and off. Cortex-A53 is a placeholder for now.
 // RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1 | FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
Index: clang/test/Driver/aarch64-cpus.c
===
--- clang/test/Driver/aarch64-cpus.c
+++ clang/test/Driver/aarch64-cpus.c
@@ -876,6 +876,22 @@
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s
 // GENERICV92A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.2a" "-target-feature" "+i8mm" "-target-feature" "+bf16" "-target-feature" "+sve" "-target-feature" "+sve2"
 
+// RUN: %clang -target aarch64 -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// GENERICV93A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.3a"
+
+// RUN: %clang -target aarch64_be -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A-BE %s
+// RUN: %clang -target aarch64_be -march=armv9.3-a -### -c %s 2>&1 

[PATCH] D115694: [ARM] Introduce an empty "armv8.8-a" architecture.

[Tomas Matheson via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd50072f74e3e: [ARM] Introduce an empty armv8.8-a 
architecture. (authored by simon_tatham, committed by tmatheson).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115694/new/

https://reviews.llvm.org/D115694

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -18,21 +18,21 @@
 
 namespace {
 const char *ARMArch[] = {
-"armv2",   "armv2a",   "armv3",   "armv3m",   "armv4",
-"armv4t",  "armv5","armv5t",  "armv5e",   "armv5te",
-"armv5tej","armv6","armv6j",  "armv6k",   "armv6hl",
-"armv6t2", "armv6kz",  "armv6z",  "armv6zk",  "armv6-m",
-"armv6m",  "armv6sm",  "armv6s-m","armv7-a",  "armv7",
-"armv7a",  "armv7ve",  "armv7hl", "armv7l",   "armv7-r",
-"armv7r",  "armv7-m",  "armv7m",  "armv7k",   "armv7s",
-"armv7e-m","armv7em",  "armv8-a", "armv8","armv8a",
-"armv8l",  "armv8.1-a","armv8.1a","armv8.2-a","armv8.2a",
-"armv8.3-a",   "armv8.3a", "armv8.4-a",   "armv8.4a", "armv8.5-a",
-"armv8.5a","armv8.6-a","armv8.6a","armv8.7-a","armv8.7a",
-"armv8-r", "armv8r",   "armv8-m.base","armv8m.base",  "armv8-m.main",
-"armv8m.main", "iwmmxt",   "iwmmxt2", "xscale",   "armv8.1-m.main",
-"armv9-a", "armv9","armv9a",  "armv9.1-a","armv9.1a",
-"armv9.2-a",   "armv9.2a",
+"armv2",   "armv2a", "armv3",   "armv3m","armv4",
+"armv4t",  "armv5",  "armv5t",  "armv5e","armv5te",
+"armv5tej","armv6",  "armv6j",  "armv6k","armv6hl",
+"armv6t2", "armv6kz","armv6z",  "armv6zk",   "armv6-m",
+"armv6m",  "armv6sm","armv6s-m","armv7-a",   "armv7",
+"armv7a",  "armv7ve","armv7hl", "armv7l","armv7-r",
+"armv7r",  "armv7-m","armv7m",  "armv7k","armv7s",
+"armv7e-m","armv7em","armv8-a", "armv8", "armv8a",
+"armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a", "armv8.2a",
+"armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",  "armv8.5-a",
+"armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a", "armv8.7a",
+"armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r","armv8-m.base",
+"armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt","iwmmxt2",
+"xscale",  "armv8.1-m.main", "armv9-a", "armv9", "armv9a",
+"armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
 };
 
 template 
@@ -501,6 +501,8 @@
   EXPECT_TRUE(
   testARMArch("armv8.7-a", "generic", "v8.7a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
@@ -765,15 +767,17 @@
 
 TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   const char *Arch[] = {
-  "v2",   "v2a","v3","v3m","v4","v4t","v5","v5t",
-  "v5e",  "v5te",   "v5tej", "v6", "v6j",   "v6k","v6hl",  "v6t2",
-  "v6kz", "v6z","v6zk",  "v6-m",   "v6m",   "v6sm",   "v6s-m", "v7-a",
-  "v7",   "v7a","v7ve",  "v7hl",   "v7l",   "v7-r",   "v7r",   "v7-m",
-  "v7m",  "v7k","v7s",   "v7e-m",  "v7em",  "v8-a",   "v8","v8a",
-  "v8l",  "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a",
-  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8.7-a", "v8.7a", "v8-r",
-  "v8m.base", "v8m.main", "v8.1m.main"
-  };
+  "v2","v2a","v3","v3m","v4",   "v4t",
+  "v5","v5t","v5e",   "v5te",   "v5tej","v6",
+  

[PATCH] D115694: [ARM] Introduce an empty "armv8.8-a" architecture.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 396780.
tmatheson added a comment.

Minor fix after rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115694/new/

https://reviews.llvm.org/D115694

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -18,21 +18,21 @@
 
 namespace {
 const char *ARMArch[] = {
-"armv2",   "armv2a",   "armv3",   "armv3m",   "armv4",
-"armv4t",  "armv5","armv5t",  "armv5e",   "armv5te",
-"armv5tej","armv6","armv6j",  "armv6k",   "armv6hl",
-"armv6t2", "armv6kz",  "armv6z",  "armv6zk",  "armv6-m",
-"armv6m",  "armv6sm",  "armv6s-m","armv7-a",  "armv7",
-"armv7a",  "armv7ve",  "armv7hl", "armv7l",   "armv7-r",
-"armv7r",  "armv7-m",  "armv7m",  "armv7k",   "armv7s",
-"armv7e-m","armv7em",  "armv8-a", "armv8","armv8a",
-"armv8l",  "armv8.1-a","armv8.1a","armv8.2-a","armv8.2a",
-"armv8.3-a",   "armv8.3a", "armv8.4-a",   "armv8.4a", "armv8.5-a",
-"armv8.5a","armv8.6-a","armv8.6a","armv8.7-a","armv8.7a",
-"armv8-r", "armv8r",   "armv8-m.base","armv8m.base",  "armv8-m.main",
-"armv8m.main", "iwmmxt",   "iwmmxt2", "xscale",   "armv8.1-m.main",
-"armv9-a", "armv9","armv9a",  "armv9.1-a","armv9.1a",
-"armv9.2-a",   "armv9.2a",
+"armv2",   "armv2a", "armv3",   "armv3m","armv4",
+"armv4t",  "armv5",  "armv5t",  "armv5e","armv5te",
+"armv5tej","armv6",  "armv6j",  "armv6k","armv6hl",
+"armv6t2", "armv6kz","armv6z",  "armv6zk",   "armv6-m",
+"armv6m",  "armv6sm","armv6s-m","armv7-a",   "armv7",
+"armv7a",  "armv7ve","armv7hl", "armv7l","armv7-r",
+"armv7r",  "armv7-m","armv7m",  "armv7k","armv7s",
+"armv7e-m","armv7em","armv8-a", "armv8", "armv8a",
+"armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a", "armv8.2a",
+"armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",  "armv8.5-a",
+"armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a", "armv8.7a",
+"armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r","armv8-m.base",
+"armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt","iwmmxt2",
+"xscale",  "armv8.1-m.main", "armv9-a", "armv9", "armv9a",
+"armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
 };
 
 template 
@@ -501,6 +501,8 @@
   EXPECT_TRUE(
   testARMArch("armv8.7-a", "generic", "v8.7a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
@@ -765,15 +767,17 @@
 
 TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   const char *Arch[] = {
-  "v2",   "v2a","v3","v3m","v4","v4t","v5","v5t",
-  "v5e",  "v5te",   "v5tej", "v6", "v6j",   "v6k","v6hl",  "v6t2",
-  "v6kz", "v6z","v6zk",  "v6-m",   "v6m",   "v6sm",   "v6s-m", "v7-a",
-  "v7",   "v7a","v7ve",  "v7hl",   "v7l",   "v7-r",   "v7r",   "v7-m",
-  "v7m",  "v7k","v7s",   "v7e-m",  "v7em",  "v8-a",   "v8","v8a",
-  "v8l",  "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a",
-  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8.7-a", "v8.7a", "v8-r",
-  "v8m.base", "v8m.main", "v8.1m.main"
-  };
+  "v2","v2a","v3","v3m","v4",   "v4t",
+  "v5","v5t","v5e",   "v5te",   "v5tej","v6",
+  "v6j",   "v6k","v6hl",  "v6t2",   "v6kz", "v6z",
+  "v6zk",  "v6-m",   "v6m",   "v6sm",   "v6s-m","v7-a",
+  "v7","v7a",

[PATCH] D115694: [ARM] Introduce an empty "armv8.8-a" architecture.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 396779.
tmatheson added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115694/new/

https://reviews.llvm.org/D115694

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -18,21 +18,21 @@
 
 namespace {
 const char *ARMArch[] = {
-"armv2",   "armv2a",   "armv3",   "armv3m",   "armv4",
-"armv4t",  "armv5","armv5t",  "armv5e",   "armv5te",
-"armv5tej","armv6","armv6j",  "armv6k",   "armv6hl",
-"armv6t2", "armv6kz",  "armv6z",  "armv6zk",  "armv6-m",
-"armv6m",  "armv6sm",  "armv6s-m","armv7-a",  "armv7",
-"armv7a",  "armv7ve",  "armv7hl", "armv7l",   "armv7-r",
-"armv7r",  "armv7-m",  "armv7m",  "armv7k",   "armv7s",
-"armv7e-m","armv7em",  "armv8-a", "armv8","armv8a",
-"armv8l",  "armv8.1-a","armv8.1a","armv8.2-a","armv8.2a",
-"armv8.3-a",   "armv8.3a", "armv8.4-a",   "armv8.4a", "armv8.5-a",
-"armv8.5a","armv8.6-a","armv8.6a","armv8.7-a","armv8.7a",
-"armv8-r", "armv8r",   "armv8-m.base","armv8m.base",  "armv8-m.main",
-"armv8m.main", "iwmmxt",   "iwmmxt2", "xscale",   "armv8.1-m.main",
-"armv9-a", "armv9","armv9a",  "armv9.1-a","armv9.1a",
-"armv9.2-a",   "armv9.2a",
+"armv2",   "armv2a", "armv3",   "armv3m","armv4",
+"armv4t",  "armv5",  "armv5t",  "armv5e","armv5te",
+"armv5tej","armv6",  "armv6j",  "armv6k","armv6hl",
+"armv6t2", "armv6kz","armv6z",  "armv6zk",   "armv6-m",
+"armv6m",  "armv6sm","armv6s-m","armv7-a",   "armv7",
+"armv7a",  "armv7ve","armv7hl", "armv7l","armv7-r",
+"armv7r",  "armv7-m","armv7m",  "armv7k","armv7s",
+"armv7e-m","armv7em","armv8-a", "armv8", "armv8a",
+"armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a", "armv8.2a",
+"armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",  "armv8.5-a",
+"armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a", "armv8.7a",
+"armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r","armv8-m.base",
+"armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt","iwmmxt2",
+"xscale",  "armv8.1-m.main", "armv9-a", "armv9", "armv9a",
+"armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
 };
 
 template 
@@ -501,6 +501,8 @@
   EXPECT_TRUE(
   testARMArch("armv8.7-a", "generic", "v8.7a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
@@ -765,15 +767,17 @@
 
 TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   const char *Arch[] = {
-  "v2",   "v2a","v3","v3m","v4","v4t","v5","v5t",
-  "v5e",  "v5te",   "v5tej", "v6", "v6j",   "v6k","v6hl",  "v6t2",
-  "v6kz", "v6z","v6zk",  "v6-m",   "v6m",   "v6sm",   "v6s-m", "v7-a",
-  "v7",   "v7a","v7ve",  "v7hl",   "v7l",   "v7-r",   "v7r",   "v7-m",
-  "v7m",  "v7k","v7s",   "v7e-m",  "v7em",  "v8-a",   "v8","v8a",
-  "v8l",  "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a",
-  "v8.4a", "v8.5-a","v8.5a", "v8.6-a", "v8.6a", "v8.7-a", "v8.7a", "v8-r",
-  "v8m.base", "v8m.main", "v8.1m.main"
-  };
+  "v2","v2a","v3","v3m","v4",   "v4t",
+  "v5","v5t","v5e",   "v5te",   "v5tej","v6",
+  "v6j",   "v6k","v6hl",  "v6t2",   "v6kz", "v6z",
+  "v6zk",  "v6-m",   "v6m",   "v6sm",   "v6s-m","v7-a",
+  "v7","v7a","v7ve",  "v7hl", 

[PATCH] D116415: [Arm] Remove duplicate CPU tests

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added reviewers: lenary, dmgreen, cpirker, olista01, vsukharev, 
SjoerdMeijer.
tmatheson added a comment.

Thanks for the review @nickdesaulniers. Adding a few more reviewers just to 
check that I'm not missing something.


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[PATCH] D116415: [Arm] Remove duplicate CPU tests

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/test/Driver/arm-cortex-cpus.c:217
 // RUN: %clang -target arm -march=armv8.1-a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V81A %s
-// RUN: %clang -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V81A %s

nickdesaulniers wrote:
> I'm definitely ok with the half of changes in this patch that remove 
> `-mlittle-endian` when it appears twice on one line.
> 
> The other half of the changes remove `-mlittle-endian` when it's not 
> specified more than once. I suspect `-mlittle-endian` is implied by `-target` 
> in this case; was the test validating that by being explicit about 
> endianness?  I guess I don't see how being explicit about the endianness 
> could affect the `-triple`, which is what is being checked, so I guess this 
> LGTM.
The second set of changes that you mention are the duplicate tests that you 
pointed out in D116159. For example, this line that is removed is a duplicate 
of line 219.


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[PATCH] D116159: [ARM][AArch64] clang support for Armv9.3-A

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/test/Driver/arm-cortex-cpus.c:445
+// RUN: %clang -target armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv9.3-a -mlittle-endian 
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s

nickdesaulniers wrote:
> Is this `RUN` line a duplicate of L443? Maybe you meant to test a hyphen in 
> the `march`?
Good catch, I've removed it. The same redundancy has been copy-pasted a few 
times by the look of it. Looks like the origins are in testing that armv8 and 
armv8a are synonymous, which doesn't seem to be the case for later versions.

I have created D116415 for the occurrences.



Comment at: clang/test/Driver/arm-cortex-cpus.c:446
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv9.3-a -mlittle-endian 
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// CHECK-V93A: "-cc1"{{.*}} "-triple" "armv9.3{{.*}}" "-target-cpu" "generic"

nickdesaulniers wrote:
> nickdesaulniers wrote:
> > how about thumb targets? I recognize this test doesn't already do so for 
> > older extensions.
> This test sets `-mlittle-endian` twice. Is that intentional? Should the 
> aarch64 test above `clang/test/Driver/aarch64-cpus.c` also have such a test, 
> or should this `RUN` line be removed? Or was something else meant to be 
> tested?
Also copy-pasted from above; I don't see any point to it, so removed. See also 
D116415.



Comment at: clang/test/Driver/arm-cortex-cpus.c:446
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv9.3-a -mlittle-endian 
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// CHECK-V93A: "-cc1"{{.*}} "-triple" "armv9.3{{.*}}" "-target-cpu" "generic"

tmatheson wrote:
> nickdesaulniers wrote:
> > nickdesaulniers wrote:
> > > how about thumb targets? I recognize this test doesn't already do so for 
> > > older extensions.
> > This test sets `-mlittle-endian` twice. Is that intentional? Should the 
> > aarch64 test above `clang/test/Driver/aarch64-cpus.c` also have such a 
> > test, or should this `RUN` line be removed? Or was something else meant to 
> > be tested?
> Also copy-pasted from above; I don't see any point to it, so removed. See 
> also D116415.
The above tests seem so be considered sufficient since 8.2, nothing much has 
changed afaik so I don't see any need to add them.


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[PATCH] D116415: [Arm] Remove duplicate CPU tests

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added a subscriber: kristof.beyls.
tmatheson requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

There are some duplicate test lines in clang/test/Driver/arm-cortex-cpus.c.
Looks like these were duplicated from the corresponding v8.0a tests, which test
both "-target armv8" and "-target armv8a". "-target armv8.X" without the "a"
doesn't work for later versions though.

Several tests also specify the -mlittle-endian twice, which looks unintentional.


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Files:
  clang/test/Driver/arm-cortex-cpus.c

Index: clang/test/Driver/arm-cortex-cpus.c
===
--- clang/test/Driver/arm-cortex-cpus.c
+++ clang/test/Driver/arm-cortex-cpus.c
@@ -143,7 +143,7 @@
 // RUN: %clang -target arm -march=armv8 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
 // RUN: %clang -target armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
 // RUN: %clang -target arm -march=armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
-// RUN: %clang -target arm -mlittle-endian -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
+// RUN: %clang -target arm -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
 // CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armv8r-linux-gnueabi -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8R %s
@@ -176,7 +176,7 @@
 // RUN: %clang -mcpu=generic -target arm -march=armv8 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
 // RUN: %clang -mcpu=generic -target armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
-// RUN: %clang -mcpu=generic -target arm -mlittle-endian -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
+// RUN: %clang -mcpu=generic -target arm -march=armv8-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
 // CHECK-V8A-GENERIC: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V8A %s
@@ -214,17 +214,15 @@
 // RUN: %clang -target arm -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target arm -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -target arm -mlittle-endian -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
+// RUN: %clang -target arm -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -mcpu=generic -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// RUN: %clang -mcpu=generic -target arm -mlittle-endian -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
+// RUN: %clang -mcpu=generic -target arm -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // CHECK-V81A: "-cc1"{{.*}} "-triple" "armv8.1a-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
@@ -254,10 +252,9 @@
 // RUN: %clang -target armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
 // RUN: %clang -target arm -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
 // RUN: %clang -target arm -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
-// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s

[PATCH] D116159: [ARM][AArch64] clang support for Armv9.3-A

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 396679.
tmatheson marked 2 inline comments as done.
tmatheson added a comment.

Remove redundancies in arm tests


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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c

Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -879,6 +879,11 @@
 // CHECK-V92A: #define __ARM_ARCH_9_2A__ 1
 // CHECK-V92A: #define __ARM_ARCH_PROFILE 'A'
 
+// RUN: %clang -target armv9.3a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V93A %s
+// CHECK-V93A: #define __ARM_ARCH 9
+// CHECK-V93A: #define __ARM_ARCH_9_3A__ 1
+// CHECK-V93A: #define __ARM_ARCH_PROFILE 'A'
+
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
Index: clang/test/Driver/arm-cortex-cpus.c
===
--- clang/test/Driver/arm-cortex-cpus.c
+++ clang/test/Driver/arm-cortex-cpus.c
@@ -437,6 +437,22 @@
 // RUN: %clang -target arm -march=armebv9.2-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s
 // CHECK-BE-V92A: "-cc1"{{.*}} "-triple" "armebv9.2{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// CHECK-V93A: "-cc1"{{.*}} "-triple" "armv9.3{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// CHECK-BE-V93A: "-cc1"{{.*}} "-triple" "armebv9.3{{.*}}" "-target-cpu" "generic"
+
 // Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
 // on and off. Cortex-A53 is a placeholder for now.
 // RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1 | FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
Index: clang/test/Driver/aarch64-cpus.c
===
--- clang/test/Driver/aarch64-cpus.c
+++ clang/test/Driver/aarch64-cpus.c
@@ -876,6 +876,22 @@
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s
 // GENERICV92A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.2a" "-target-feature" "+i8mm" "-target-feature" "+bf16" "-target-feature" "+sve" "-target-feature" "+sve2"
 
+// RUN: %clang -target aarch64 -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// GENERICV93A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.3a"
+
+// RUN: %clang -target aarch64_be -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A-BE 

[PATCH] D116160: [AArch64] ACLE feature macro for Armv8.8-A MOPS

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added a subscriber: kristof.beyls.
tmatheson requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This introduces the new `__ARM_FEATURE_MOPS` ACLE feature test macro,
which signals the availability of the new Armv8.8-A/Armv9.3-A
instructions for standardising memcpy, memset and memmove operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116160

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/Support/AArch64TargetParser.h


Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -69,6 +69,7 @@
   AEK_SME = 1ULL << 37,
   AEK_SMEF64 =  1ULL << 38,
   AEK_SMEI64 =  1ULL << 39,
+  AEK_MOPS =1ULL << 40,
 };
 
 enum class ArchKind {
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -517,3 +517,13 @@
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s 
-o - | FileCheck --check-prefix=CHECK-LSE %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o 
- | FileCheck --check-prefix=CHECK-LSE %s
 // CHECK-LSE: __ARM_FEATURE_ATOMICS 1
+
+// == Check Armv8.8-A/Armv9.3-A memcpy and memset acceleration 
instructions (MOPS)
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+mops -x c -E -dM 
%s -o - | FileCheck --check-prefix=CHECK-MOPS %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.8-a -x c -E -dM %s 
-o - | FileCheck --check-prefix=CHECK-MOPS %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.8-a+nomops -x c -E 
-dM %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv9-a+mops -x c -E -dM 
%s -o - | FileCheck --check-prefix=CHECK-MOPS %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a -x c -E -dM %s 
-o - | FileCheck --check-prefix=CHECK-MOPS %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a+nomops -x c -E 
-dM %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
+// CHECK-MOPS: __ARM_FEATURE_MOPS 1
+// CHECK-NOMOPS-NOT: __ARM_FEATURE_MOPS 1
Index: clang/lib/Basic/Targets/AArch64.h
===
--- clang/lib/Basic/Targets/AArch64.h
+++ clang/lib/Basic/Targets/AArch64.h
@@ -53,6 +53,7 @@
   bool HasMatmulFP32;
   bool HasLSE;
   bool HasFlagM;
+  bool HasMOPS;
 
   llvm::AArch64::ArchKind ArchKind;
 
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -435,6 +435,9 @@
   if (HasRandGen)
 Builder.defineMacro("__ARM_FEATURE_RNG", "1");
 
+  if (HasMOPS)
+Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
+
   switch (ArchKind) {
   default:
 break;
@@ -660,6 +663,17 @@
   HasFlagM = true;
   }
 
+  HasMOPS |= ArchKind == llvm::AArch64::ArchKind::ARMV8_8A ||
+ ArchKind == llvm::AArch64::ArchKind::ARMV9_3A;
+
+  // Check features that are manually disabled by command line options.
+  // This needs to be checked after architecture-related features are handled,
+  // making sure they are properly disabled when required.
+  for (const auto  : Features) {
+if (Feature == "-mops")
+  HasMOPS = false;
+  }
+
   setDataLayout();
 
   return true;


Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -69,6 +69,7 @@
   AEK_SME = 1ULL << 37,
   AEK_SMEF64 =  1ULL << 38,
   AEK_SMEI64 =  1ULL << 39,
+  AEK_MOPS =1ULL << 40,
 };
 
 enum class ArchKind {
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -517,3 +517,13 @@
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s
 // CHECK-LSE: __ARM_FEATURE_ATOMICS 1
+
+// == Check Armv8.8-A/Armv9.3-A memcpy and memset acceleration instructions (MOPS)
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+mops -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
+// 

[PATCH] D116159: [ARM][AArch64] clang support for Armv9.3-A

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added a subscriber: kristof.beyls.
tmatheson requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch introduces support for targetting the Armv9.3-A architecture,
which should map to the existing Armv8.8-A extensions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116159

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Preprocessor/arm-target-features.c

Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -879,6 +879,11 @@
 // CHECK-V92A: #define __ARM_ARCH_9_2A__ 1
 // CHECK-V92A: #define __ARM_ARCH_PROFILE 'A'
 
+// RUN: %clang -target armv9.3a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V93A %s
+// CHECK-V93A: #define __ARM_ARCH 9
+// CHECK-V93A: #define __ARM_ARCH_9_3A__ 1
+// CHECK-V93A: #define __ARM_ARCH_PROFILE 'A'
+
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
Index: clang/test/Driver/arm-cortex-cpus.c
===
--- clang/test/Driver/arm-cortex-cpus.c
+++ clang/test/Driver/arm-cortex-cpus.c
@@ -437,6 +437,23 @@
 // RUN: %clang -target arm -march=armebv9.2-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s
 // CHECK-BE-V92A: "-cc1"{{.*}} "-triple" "armebv9.2{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -march=armv9.3a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv9.3-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V93A %s
+// CHECK-V93A: "-cc1"{{.*}} "-triple" "armv9.3{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target armeb -march=armebv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// RUN: %clang -target arm -march=armebv9.3-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V93A %s
+// CHECK-BE-V93A: "-cc1"{{.*}} "-triple" "armebv9.3{{.*}}" "-target-cpu" "generic"
+
 // Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
 // on and off. Cortex-A53 is a placeholder for now.
 // RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1 | FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
Index: clang/test/Driver/aarch64-cpus.c
===
--- clang/test/Driver/aarch64-cpus.c
+++ clang/test/Driver/aarch64-cpus.c
@@ -876,6 +876,22 @@
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s
 // GENERICV92A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.2a" "-target-feature" "+i8mm" "-target-feature" "+bf16" "-target-feature" "+sve" "-target-feature" "+sve2"
 
+// RUN: %clang -target aarch64 -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A %s
+// 

[PATCH] D116154: [ARM] Adding macros for coprocessor intrinsics as per ACLE

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added a subscriber: kristof.beyls.
tmatheson requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Patch by Ranjeet Singh and Son Tuan Vu.

Change-Id: Ic18ffda35760587673b30c166ac145b0df038973


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116154

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm-acle-coproc.c
  clang/test/Preprocessor/aarch64-target-features.c

Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -43,6 +43,7 @@
 // CHECK-NOT: __ARM_PCS_VFP 1
 // CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1
 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
+// CHECK-NOT: __ARM_TARGET_COPROC 1
 // CHECK-NOT: __ARM_FEATURE_SVE
 // CHECK-NOT: __ARM_FEATURE_DOTPROD
 // CHECK-NOT: __ARM_FEATURE_PAC_DEFAULT
Index: clang/test/CodeGen/arm-acle-coproc.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-acle-coproc.c
@@ -0,0 +1,350 @@
+// RUN: %clang_cc1 -triple armv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s
+// RUN: %clang_cc1 -triple armv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4 %s
+// RUN: %clang_cc1 -triple armv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5 %s
+// RUN: %clang_cc1 -triple armv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s
+// RUN: %clang_cc1 -triple armv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE %s
+// RUN: %clang_cc1 -triple armv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6 %s
+// RUN: %clang_cc1 -triple armv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s
+// RUN: %clang_cc1 -triple armv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple armv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple armv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
+// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5te %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s
+// RUN: %clang_cc1 -triple thumbv5tej %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-TE-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6k %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6kz %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6-THUMB %s
+// RUN: %clang_cc1 -triple thumbv6m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V6M %s
+// RUN: %clang_cc1 -triple thumbv7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv7r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv7m %s -E -dD -o - | FileCheck --check-prefix=CHECK-V7 %s
+// RUN: %clang_cc1 -triple thumbv8a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.1a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.2a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8.7a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8r %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
+// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck 

[PATCH] D116153: [ARM][AArch64] Add missing v8.x checks

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added a subscriber: kristof.beyls.
tmatheson requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116153

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Preprocessor/aarch64-target-features.c


Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -294,7 +294,7 @@
 // CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" 
"+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+sha2" "-target-feature" "+aes"
 
 // RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | 
FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+v8.5a" 
"-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" 
"+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" 
"-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" 
"-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" 
"-target-feature" "+zcz" "-target-feature" "+fullfp16" "-target-feature" 
"+sha2" "-target-feature" "+aes"
+// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+v8.5a" 
"-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" 
"+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" 
"-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" 
"-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" 
"-target-feature" "+zcz" "-target-feature" "+fullfp16" "-target-feature" "+sm4" 
"-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes"
 
 // RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | 
FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s
 // CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+v8.3a" 
"-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" 
"+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" 
"-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" 
"-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" 
"-target-feature" "+sha2" "-target-feature" "+aes"
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -390,6 +390,9 @@
   }
 
   if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd ||
+  std::find(ItBegin, ItEnd, "+v8.5a") != ItEnd ||
+  std::find(ItBegin, ItEnd, "+v8.6a") != ItEnd ||
+  std::find(ItBegin, ItEnd, "+v8.7a") != ItEnd ||
   std::find(ItBegin, ItEnd, "+v9a") != ItEnd ||
   std::find(ItBegin, ItEnd, "+v9.1a") != ItEnd ||
   std::find(ItBegin, ItEnd, "+v9.2a") != ItEnd) {
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -930,6 +930,7 @@
   case llvm::ARM::ArchKind::ARMV8_4A:
   case llvm::ARM::ArchKind::ARMV8_5A:
   case llvm::ARM::ArchKind::ARMV8_6A:
+  case llvm::ARM::ArchKind::ARMV8_7A:
   case llvm::ARM::ArchKind::ARMV9A:
   case llvm::ARM::ArchKind::ARMV9_1A:
   case llvm::ARM::ArchKind::ARMV9_2A:


Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -294,7 +294,7 @@
 // CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+aes"
 
 // RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+v8.5a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+fullfp16" "-target-feature" "+sha2" "-target-feature" 

[PATCH] D115694: [ARM] Introduce an empty "armv8.8-a" architecture.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D114703: [AArch64] Use Feature for A53 Erratum 835769 Fix

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

Makes sense to me


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[PATCH] D110065: [AArch64] Add support for the 'R' architecture profile.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.h:62
   std::string ABI;
+  StringRef getArchProfile() const;
 

tmatheson wrote:
> The equivalent in the ARM backend is named `getCPUProfile`
That's arguably a worse name though.


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[PATCH] D110065: [AArch64] Add support for the 'R' architecture profile.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.h:62
   std::string ABI;
+  StringRef getArchProfile() const;
 

The equivalent in the ARM backend is named `getCPUProfile`


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[PATCH] D105498: [clang] Remove assumption about SourceLocation alignment.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a subscriber: efriedma.
tmatheson added a comment.
This revision is now accepted and ready to land.

LGTM, but it would be good to have someone else comment on the increased number 
of allocations (maybe @rsmith or @efriedma?)




Comment at: clang/include/clang/AST/DeclObjC.h:208
   const ParmVarDecl *const *getParams() const {
-return reinterpret_cast(ParamsAndSelLocs);
+return const_cast(Params);
   }

I don't think you need the `const_cast`


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[PATCH] D105498: [clang] Remove assumption about SourceLocation alignment.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/lib/AST/DeclObjC.cpp:880-882
-  unsigned Size = sizeof(ParmVarDecl *) * NumParams +
-  sizeof(SourceLocation) * SelLocs.size();
   ParamsAndSelLocs = C.Allocate(Size);

Since we know the number of parameters and number of sellocs when we do the 
allocation, is there a reason we can't we split it into two separate 
allocations and reduce the complexity?


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[PATCH] D105495: [clang] Make negative getLocWithOffset widening-safe.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

I'm not a huge fan of this as an API; it is not obvious what the function and 
parameters do without reading the comment or implementation (e.g. whether 
`Offset` is ignored if `NegOffset` is given, and what it means to pass offsets 
to both). It moves the subtraction logic from the call site, where it is 
meaningful, to inside the function where it is not. I also think it's the 
caller's responsibility to make sure what they pass in is correctly signed. 
I've put suggestions for how each call site could be updated without casting 
while keeping `getLocWithOffset` unchanged.




Comment at: clang/lib/AST/SelectorLocationsKind.cpp:41
 ++Len;
-  return ArgLoc.getLocWithOffset(-Len);
 }

These are probably fine as they were



Comment at: clang/lib/CodeGen/CoverageMappingGen.cpp:236
 if (Loc.isMacroID())
-  return Loc.getLocWithOffset(-SM.getFileOffset(Loc));
+  return Loc.getLocWithOffset(0, SM.getFileOffset(Loc));
 return SM.getLocForStartOfFile(SM.getFileID(Loc));

Seems like getFileOffset should now return ui64.



Comment at: clang/lib/Format/FormatTokenLexer.cpp:835
   SourceLocation WhitespaceStart =
-  FormatTok->Tok.getLocation().getLocWithOffset(-TrailingWhitespace);
+  FormatTok->Tok.getLocation().getLocWithOffset(0, TrailingWhitespace);
   FormatTok->IsFirst = IsFirstToken;

This probably would need a cast; widening `TrailingWhitespace` seems overkill.



Comment at: clang/lib/Lex/Lexer.cpp:530
   // Create a lexer starting at the beginning of this token.
-  SourceLocation LexerStartLoc = Loc.getLocWithOffset(-LocInfo.second);
+  SourceLocation LexerStartLoc = Loc.getLocWithOffset(0, LocInfo.second);
   Lexer TheLexer(LexerStartLoc, LangOpts, Buffer.data(), LexStart,

ditto `getDecomposedLoc`



Comment at: clang/lib/Lex/Lexer.cpp:568-570
   std::pair FileLocInfo = SM.getDecomposedLoc(FileLoc);
   std::pair BeginFileLocInfo =
   SM.getDecomposedLoc(BeginFileLoc);

Shouldn't the return type of `getDecomposedLoc` need updating at some stage? If 
so that would take care of this case



Comment at: clang/lib/Parse/ParseStmtAsm.cpp:174-179
   unsigned Offset = SMLoc.getPointer() - LBuf->getBufferStart();
 
   // Figure out which token that offset points into.
   const unsigned *TokOffsetPtr = llvm::lower_bound(AsmTokOffsets, Offset);
   unsigned TokIndex = TokOffsetPtr - AsmTokOffsets.begin();
   unsigned TokOffset = *TokOffsetPtr;





Comment at: clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp:1073-1074
   // Compute the column number of the end.
   unsigned EndColNo = SM.getExpansionColumnNumber(InstantiationEnd);
   unsigned OldEndColNo = EndColNo;
 




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[PATCH] D105491: [clang] Use i64 for the !srcloc metadata on asm IR nodes.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

@dexonsmith I don't think they need upgraded. Most of the places I can see 
referencing `!srcloc` are copying it around and will preserve the i32 type. 
Cases which actually read the value are already reading it as 64 bit via 
`getZExtValue` and have been updated here, e.g. `MachineInstr::emitError`


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[PATCH] D105493: [clang] Change set type used for SourceLocation.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

LGTM


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[PATCH] D105492: [clang] Introduce SourceLocation::[U]IntType typedefs.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

LGTM




Comment at: clang/include/clang/Basic/SourceLocation.h:97
+  using UIntType = uint32_t;
+  using IntType = int32_t;
 

Nit: the `Ty` suffix seems to be slightly more common than `Type`


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[PATCH] D105491: [clang] Use i64 for the !srcloc metadata on asm IR nodes.

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

Looks sensible to me, I don't think slightly expanding the size of the metadata 
and the diagnostic will be an issue.


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[PATCH] D97187: [Clang][Sema] Warn when function argument is less aligned than parameter

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

I believe PR49534 was fixed by D98548  above


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[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb14a6f06cc87: [ARM][MVE] vcreateq lane ordering for big 
endian (authored by tmatheson).

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  clang/test/CodeGen/arm-mve-intrinsics/admin.c

Index: clang/test/CodeGen/arm-mve-intrinsics/admin.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/admin.c
+++ clang/test/CodeGen/arm-mve-intrinsics/admin.c
@@ -1,51 +1,82 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+
 
 #include 
 
-// CHECK-LABEL: @test_vcreateq_f16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f16(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-LE-NEXT:ret <8 x half> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f16(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)
 {
 return vcreateq_f16(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_f32(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
-// CHECK-NEXT:ret <4 x float> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f32(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
+// CHECK-LE-NEXT:ret <4 x float> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f32(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <4 x float> [[TMP2]]
 //
 float32x4_t test_vcreateq_f32(uint64_t a, uint64_t b)
 {
 return vcreateq_f32(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_s16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> 

[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson marked 2 inline comments as done.
tmatheson added a comment.

In D101606#2728320 , @dmgreen wrote:

> Sounds good to me.
>
> Whilst we are here, are any of the other uses of bitcast in arm_mve.td 
> potentially a problem? I took a quick look and because they both converting 
> the inputs and the outputs, I believe they will be OK. (Two wrongs make a 
> right, if you will).

I had a look and came to the same conclusion, I couldn't find any way to make 
them break. Worth noting that they are all converting between vectors with the 
same number of lanes, e.g. typically between the signed and unsigned versions 
of NxM vectors.


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[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 341823.
tmatheson added a comment.

Use --check-prefixes=CHECK,CHECK-BE etc to combine common blocks.
Sorry for the churn.


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Index: clang/test/CodeGen/arm-mve-intrinsics/admin.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/admin.c
+++ clang/test/CodeGen/arm-mve-intrinsics/admin.c
@@ -1,51 +1,82 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+
 
 #include 
 
-// CHECK-LABEL: @test_vcreateq_f16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f16(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-LE-NEXT:ret <8 x half> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f16(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)
 {
 return vcreateq_f16(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_f32(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
-// CHECK-NEXT:ret <4 x float> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f32(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
+// CHECK-LE-NEXT:ret <4 x float> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f32(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <4 x float> [[TMP2]]
 //
 float32x4_t test_vcreateq_f32(uint64_t a, uint64_t b)
 {
 return vcreateq_f32(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_s16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 

[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 341819.
tmatheson added a comment.

remove old check lines that were not automatically removed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101606/new/

https://reviews.llvm.org/D101606

Files:
  clang/include/clang/Basic/arm_mve.td
  clang/test/CodeGen/arm-mve-intrinsics/admin.c

Index: clang/test/CodeGen/arm-mve-intrinsics/admin.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/admin.c
+++ clang/test/CodeGen/arm-mve-intrinsics/admin.c
@@ -1,301 +1,452 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-BE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-BE
+
 
 #include 
 
-// CHECK-LABEL: @test_vcreateq_f16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f16(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-LE-NEXT:ret <8 x half> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f16(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)
 {
 return vcreateq_f16(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_f32(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
-// CHECK-NEXT:ret <4 x float> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f32(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
+// CHECK-LE-NEXT:ret <4 x float> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f32(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <4 x float> [[TMP2]]
 //
 float32x4_t test_vcreateq_f32(uint64_t a, uint64_t b)
 {
 return vcreateq_f32(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_s16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x 

[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson updated this revision to Diff 341818.
tmatheson edited the summary of this revision.
tmatheson added a comment.

Use update_cc_test_checks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101606/new/

https://reviews.llvm.org/D101606

Files:
  clang/include/clang/Basic/arm_mve.td
  clang/test/CodeGen/arm-mve-intrinsics/admin.c

Index: clang/test/CodeGen/arm-mve-intrinsics/admin.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/admin.c
+++ clang/test/CodeGen/arm-mve-intrinsics/admin.c
@@ -1,51 +1,82 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-BE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK-BE
+
 
 #include 
 
-// CHECK-LABEL: @test_vcreateq_f16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f16(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-LE-NEXT:ret <8 x half> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f16(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)
 {
 return vcreateq_f16(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_f32(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
-// CHECK-NEXT:ret <4 x float> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f32(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
+// CHECK-LE-NEXT:ret <4 x float> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f32(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <4 x float> [[TMP2]]
 //
 float32x4_t test_vcreateq_f32(uint64_t a, uint64_t b)
 {
 return vcreateq_f32(a, b);
 }
 
-// CHECK-LABEL: @test_vcreateq_s16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = 

[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added inline comments.



Comment at: clang/test/CodeGen/arm-mve-intrinsics/admin.c:66
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 
[[B:%.*]], i64 1
 // CHECK-NEXT:ret <2 x i64> [[TMP1]]
 //

MarkMurrayARM wrote:
> dmgreen wrote:
> > MarkMurrayARM wrote:
> > > Surely there is a problem here also?
> > I don't see why these would be a problem. Can you elaborate?
> I'm wondering if they need to be swapped in the BE case.
vcreateq is not endianness aware, it just inserts the two given 64 bit values 
`a` and `b` into the low and high lanes respectively. The bit representation of 
each 64 bit int will be different but that is not shown here. Therefore the IR 
is the same for big and little endian.

I have also confirmed locally with runtime output:
```
uint64x2_t w = vcreateq_u64(0x0001, 0x0002);
printf("%d:%llu\n", 0, vgetq_lane_u64(w, 0));
printf("%d:%llu\n", 1, vgetq_lane_u64(w, 1));
```
which gives for both little and bit endian (with this patch):
```
0:1
1:2
```



Comment at: clang/test/CodeGen/arm-mve-intrinsics/admin.c:116
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 
[[B:%.*]], i64 1
 // CHECK-NEXT:ret <2 x i64> [[TMP1]]
 //

MarkMurrayARM wrote:
> And a problem here also (with BE)?
See above


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[PATCH] D101606: [ARM] vcreateq lane ordering for big endian

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson created this revision.
Herald added subscribers: danielkiss, dmgreen, kristof.beyls.
tmatheson requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Use of bitcast resulted in lanes being swapped for vcreateq with big
endian. Fix this by using vreinterpret. No code change for little
endian. Adds IR lit test.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101606

Files:
  clang/include/clang/Basic/arm_mve.td
  clang/test/CodeGen/arm-mve-intrinsics/admin.c

Index: clang/test/CodeGen/arm-mve-intrinsics/admin.c
===
--- clang/test/CodeGen/arm-mve-intrinsics/admin.c
+++ clang/test/CodeGen/arm-mve-intrinsics/admin.c
@@ -1,6 +1,9 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
+
 
 #include 
 
@@ -8,7 +11,8 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
 // CHECK-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)
@@ -20,7 +24,8 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v2i64(<2 x i64> [[TMP1]])
 // CHECK-NEXT:ret <4 x float> [[TMP2]]
 //
 float32x4_t test_vcreateq_f32(uint64_t a, uint64_t b)
@@ -32,7 +37,8 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x i16>
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x i16>
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v2i64(<2 x i64> [[TMP1]])
 // CHECK-NEXT:ret <8 x i16> [[TMP2]]
 //
 int16x8_t test_vcreateq_s16(uint64_t a, uint64_t b)
@@ -44,7 +50,8 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v2i64(<2 x i64> [[TMP1]])
 // CHECK-NEXT:ret <4 x i32> [[TMP2]]
 //
 int32x4_t test_vcreateq_s32(uint64_t a, uint64_t b)
@@ -67,7 +74,8 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 

[PATCH] D98548: [clang][Sema] Don't try to initialize implicit variable of invalid anonymous union/struct

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson accepted this revision.
tmatheson added a comment.
This revision is now accepted and ready to land.

That makes sense, you are correct that that warning is not prevented. I'm not 
sure what I did differently when I checked. LGTM.


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[PATCH] D98548: [clang][Sema] Don't try to initialize implicit variable of invalid anonymous union/struct

[Tomas Matheson via Phabricator via cfe-commits]

tmatheson added a comment.

This seems quite an early point to bail out, so it will prevent some 
errors/warnings associated with initialization from being emitted. For example, 
this warning is currently emitted but would be suppressed by this patch:

  union {
virtual int a();
int b = 'c'; // expected-warning {{in-class initialization of non-static 
data member is a C++11 extension [-Wc++11-extensions]}}
  }

I don't know how much that matters seeing as the union is invalid by this point.


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