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Ping
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Address review comments.
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This patch adds the fix for undef virtual register reading failure when trap
NeHuang added a comment.
-
Comment at: clang/lib/Headers/altivec.h:19050
+}
+
+static __inline__ long __bcdcmpeq(vector unsigned char __a,
Do we need to add a case for "__CR6_SO_REV"? It is defined in line 25 but not
used.
Comment at:
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Addressed review comments
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Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1020
+// We can only do the optimization for the "reg + reg" form.
+if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8)))
+
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Address review comments from @nemanjai
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Addressed review comments from @amy
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Comment at:
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+; CHECK: # %bb.0:
+; CHECK-NEXT:tdi 3, 3, 32767
+; CHECK-NEXT:blr
amyk wrote:
> amyk wrote:
> > nemanjai wrote:
> > > Can we add
NeHuang updated this revision to Diff 383506.
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Addressed review comments from @nemanjai and @amyk
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gentle ping
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This patch adds the backend optimization to match XL behavior for the two
builtins
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gentle ping
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This revision is now accepted and ready to land.
Thanks. LGTM. One minor can be addressed when commit it.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c:71
+
+ /*shift = 31, mask = 0x1FF =
NeHuang added a comment.
Please check and add a test in
`clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c` with `shift` as a variable.
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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-error.c:46
unsigned int mask;
- unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+ unsigned int res =
NeHuang accepted this revision as: NeHuang.
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This revision is now accepted and ready to land.
LTGM
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clang-format
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This patch adds PPC back end optimization to analyze the
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Comment at: clang/test/Sema/ppc-mma-builtins.c:1
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -target-feature -mma -fsyntax-only %s -verify
can you please add `// REQUIRES:
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Do we already have a backend test case for `fdiv` emitting a software estimate
when `-Ofast` is used?
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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:27
char test_lbarx(volatile unsigned char *a) {
// CHECK-LABEL: @test_lbarx
Do you also need to update the input argument type here as well to match
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Comment at: clang/test/CodeGen/builtins-ppc-int128.c:4
+// RUN: -triple powerpc64-unknown-unknown -target-cpu pwr8 \
+// RUN: -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature
NeHuang updated this revision to Diff 370428.
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Address review comments
- typo update
- use proper mcpu in the test case.
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Address review comment.
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This patch marks splat immediate instructions `XXSPLTIDP` and
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This patch renames the vector clear left/right
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This patch adds a fix to do early if conversion to select when conditional
branch
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Address review comment from Nemanja.
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LGTM
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LGTM
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LGTM.
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Address review comments on the test case.
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- Rebased with ToT
- Clang-format
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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c:17
+// CHECK-LABEL: @test_swdiv(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
nit:
NeHuang added inline comments.
Comment at: clang/test/Driver/ppc-mprivileged-support-check.c:25
+// HASPRIV: test() #0 {
+// HASPRIV: attributes #0 {
+// HASPRIV-SAME: +privileged
maybe check for `attributes #0 = {`
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When depth > 0, callee frame address is used to compute the return address of
NeHuang added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:45
+ // CHECK-AIX-NEXT: ret { double, double } %.fca.1.insert
+ return __cmplxl(lda, ldb);
+}
nemanjai wrote:
> We really only need this test case and we should be
NeHuang added inline comments.
Comment at: llvm/test/CodeGen/PowerPC/O3-pipeline.ll:211
ret void
-}
\ No newline at end of file
+}
unrelated change?
Comment at: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll:7
+; RUN: llc
NeHuang added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
`// REQUIRES: powerpc-registered-target`
NeHuang added inline comments.
Comment at: clang/lib/Sema/SemaChecking.cpp:3426
+ case PPC::BI__builtin_ppc_addex: {
+if (SemaFeatureCheck(*this, TheCall, "power9-vector",
+ diag::err_ppc_builtin_only_on_arch, "9") ||
I think we
NeHuang accepted this revision as: NeHuang.
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This revision is now accepted and ready to land.
LGTM.
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Closed by commit rG26ea4a443243: [PowerPC] Add PowerPC __stbcx
builtin and intrinsic for XL compatibility (authored by
NeHuang marked an inline comment as done.
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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:31
+ return __builtin_ppc_stbcx(c_addr, c);
+}
lei wrote:
> Why not just add this tc to
>
NeHuang updated this revision to Diff 360803.
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- Addressed review comments from Lei
- Rebased the patch
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This
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@jroelofs committed `f6769b663a0d4432b5e00e0c03904a5dfba7b077` to move the
backend test cases from `CodeGen` -> `CodeGen/PowerPC` so they don't fail when
the PPC backend isn't built.
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Thanks @jroelofs for moving the test cases! Those cases were added in
https://reviews.llvm.org/D105946 and I have notified the author.
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clang-format
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Rebased the patch with ToT.
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Address review comments from Nemanja.
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LGTM
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Address review comment to rework 32 bit handling.
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Closed by commit rG4eb107ccbad7: [PowerPC] Add PowerPC population count,
reversed load and store related… (authored by
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Address review comments from Nemanja.
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Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081
}
+ case PPC::BI__builtin_ppc_cmpb: {
+llvm::Type *Ty = Ops[0]->getType();
NeHuang wrote:
> nemanjai wrote:
> > I find it rather
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Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081
}
+ case PPC::BI__builtin_ppc_cmpb: {
+llvm::Type *Ty = Ops[0]->getType();
nemanjai wrote:
> I find it rather surprising that we are emitting this complex sequence for
>
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Addressed review comments from Nemanja.
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Semachecking (authored by NeHuang).
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Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll:9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
amyk wrote:
> Does it
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Need to merge with https://reviews.llvm.org/D105501 changes once approved for
pwr9 (or later processor) only sema checking.
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Remove entry check in test case.
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Comment at: clang/lib/Sema/SemaChecking.cpp:3356
+ case PPC::BI__builtin_ppc_maddld:
+return SemaFeatureCheck(*this, TheCall, "power9-vector",
+diag::err_ppc_builtin_only_on_pwr9);
amyk wrote:
>
NeHuang updated this revision to Diff 357625.
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Address review comments on test case and remove change not needed.
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gentle ping
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gentle ping.
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gentle ping.
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This revision is now accepted and ready to land.
LGTM. Thanks for addressing the comments!
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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN:
NeHuang updated this revision to Diff 356701.
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Address review comments on the test case. Target cpu sema checking covered in
front end test cases. will keep current coverage in backend test.
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This revision is now accepted and ready to land.
Overall LGTM.
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Comment at:
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c:1
+// RUN: not %clang_cc1 -triple=powerpc-unknown-aix -O2 -S -emit-llvm %s -o -
2>&1 |\
+// RUN: FileCheck %s --check-prefix=CHECK32-ERROR
NeHuang added a comment.
Please add the sema check & error test case for the two 64 bit only builtins
`ldarx` and `stdcx`
Comment at:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64-only.ll:10
+declare i64 @llvm.ppc.ldarx(i8*)
+define dso_local i64
NeHuang added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c:240
+void test_icbt() {
+ __icbt(c);
}
From the document, `__icbt` only valid when -qarch is set to target pwr8 or
higher processors. It looks like target cpu sema
NeHuang added inline comments.
Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll:18
+
+define dso_local double @test_fsel(double %a, double %b, double %c)
local_unnamed_addr #0 {
+; CHECK-PWR7-LABEL: test_fsel
you can remove `#0`, `#1` and `#2`
NeHuang added a comment.
Overall looks good. Some nits as below.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-fp.c:9
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+double test_fric(double a) {
- You can define three extern variables for
NeHuang requested changes to this revision.
NeHuang added inline comments.
This revision now requires changes to proceed.
Comment at: clang/include/clang/Basic/BuiltinsPPC.def:32
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, lei, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton.
NeHuang requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
This patch is in a
NeHuang updated this revision to Diff 354082.
NeHuang added a comment.
- Rebased the patch with ToT and the patch https://reviews.llvm.org/D102875
- Create the patch with all contexts. (Thanks @qiucf)
Repository:
rG LLVM Github Monorepo
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NeHuang updated this revision to Diff 354081.
NeHuang added a comment.
- Added Sema check for the pwr9 only builtins and updated the test cases.
- Rebased the patch with ToT.
- Cleaned up the test cases and address review comments
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added projects: LLVM, clang.
Herald added subscribers: shchenz, kbarton.
NeHuang requested review of this revision.
Herald added a subscriber: cfe-commits.
This patch is in a series of patches to provide
NeHuang accepted this revision.
NeHuang added a comment.
This revision is now accepted and ready to land.
LGTM. Please give it some time (~24hrs) before commit to wait for the other
reviewers' comment.
Repository:
rG LLVM Github Monorepo
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NeHuang updated this revision to Diff 352560.
NeHuang added a comment.
- Add AIX 32&64 bit run line checks (front and back end test cases)
- Create builtin-ppc-xlcompat-error.c for arguments related error check, add
error test case for `__builtin_ppc_cmprb`
- Remove 32 bit linux run line checks
NeHuang updated this revision to Diff 351989.
NeHuang added a comment.
Rebased the patch with changes in https://reviews.llvm.org/D104125
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102875/new/
https://reviews.llvm.org/D102875
Files:
NeHuang updated this revision to Diff 350991.
NeHuang added a comment.
- Renamed the XLCompat builtin as `__builtin_ppc_*` and add them to
`definedXLCompatMacros` and update the test cases.
- Report error in SemaChecking when 64 bit only builtins run on a 32 bit target
and update the test
NeHuang created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
NeHuang requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.
This is patch is in a series of patches to provide builtins for
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG46475a79f85b: [AIX][TLS] Diagnose use of unimplemented TLS
models (authored by NeHuang).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST
NeHuang updated this revision to Diff 344258.
NeHuang added a comment.
Address review comment for the diagnostic message.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102070/new/
https://reviews.llvm.org/D102070
Files:
NeHuang updated this revision to Diff 343743.
NeHuang added a comment.
Addressed review comment for the diagnostic message and update the test cases.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102070/new/
https://reviews.llvm.org/D102070
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